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In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%–72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory. [ABSTRACT FROM AUTHOR]

Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM. [ABSTRACT FROM AUTHOR]

From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures—in the example of NAND and NOR gates—which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption. [ABSTRACT FROM AUTHOR]

This paper reports on the potential benefits of a vertically stacked ${n}$ - and ${p}$ -type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention time (RT) of capacitorless dynamic random access memory (1T-DRAM), with a significant improvement $(\sim \!\!\times 10^{3})$ compared with a conventional JL transistor with a doping (${N}_{\text{d}}$) of 1019 cm−3. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top ${n}$ -type JL transistor) and storage region (bottom ${p}$ -type JL), while maintaining an electrostatic coupling between them. The charge stored in the ${p}$ -type JL determines RT, and also impacts the read currents, and thus, influences the sense margin of DRAM. Stacked JL (SJL) 1T-DRAM achieves a maximum RT of ~2.5 s for ${N}_{\text{d}} = 5 \times 10^{18}$ cm−3 and ~1 s for 1019 cm−3 with a gate length (${L}_{\text{g}}$) of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The enhanced DRAM metrics (better scalability and high RT) are attributed to optimal architecture due to the vertical stacking of ${n}$ - and ${p}$ -type regions. [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

This paper presents a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word line (WL)/bit line (BL) disturbance, which is verified using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4 \mathrmF^2 and with processes that are fully compatible with conventional CMOS technology. Extended simulations reveal three key findings. First, the WT-SGT achieves a high-speed programming operation (1.17 ns) at a low operating voltage (1.6 V) and with a programming window that can be further extended by widening its trenched body. Second, the recombination rate is also reduced, thereby yielding an acceptable retention time (RT) of 625.6 ms. Third, the decreased RT after a 100-ns WL/BL disturbance is improved by 33%, as compared with a conventional SGT 1T-DRAM. We, therefore, believe that this new device will become a competitive candidate for use in future DRAM cells. [ABSTRACT FROM PUBLISHER]

In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]

In this paper, we illustrate how high-resolution 2-D carrier profiles from scanning spreading resistance microscopy (SSRM) can be used to predict and understand device performance of dynamic random access memory peripheral transistors with high-k metal gate and ultrashallow junctions. In an earlier study on high-speed complementary metal–oxide–semiconductor logic, the 2-D carrier profiles from SSRM were used as the active 2-D dopant profile input to the device simulator as they are virtually identical. The extensive mobile carrier diffusion caused by the lower concentrations, however, implies a strong difference between the mobile carrier distribution and the dopant distribution such that the same approach is no longer valid. Ideally one would have to generate, based on the carrier profiles, the active dopant distribution through the inverse solution of the Poisson equation (in two dimensions) which is, however, numerically nontrivial and often leads to nonunique results. Therefore, an alternative approach is proposed here, whereby we fine-tune the process simulations such that the resulting simulated carrier profiles match the 2-D SSRM profiles. Upon reaching satisfactory agreement, the simulated profiles can be used as input for a device simulator and be used to predict sensitive device parameters such as drain-induced barrier lowering and threshold voltage rolloff. [ABSTRACT FROM AUTHOR]

A novel one transistor and one diode (1T-1D) dynamic random access memory cell for embedded applications is proposed. This memory cell consists of a floating-gate (FG) MOSFET and a gated diode. The anode of the diode is connected to the FG, so that the threshold voltage of the FG MOSFET can be modulated by the current through the diode. In this paper, basic device operations, speed, retention, and disturb performance are investigated using Silvaco technology computer-aided design simulation tools. The process compatibility is also investigated by integrating the memory array and specific sense amplifier. [ABSTRACT FROM PUBLISHER]