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Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ($\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

Recent studies of electroluminescent cooling (ELC) in III–V structures demonstrate the need to better understand the factors affecting the efficiency of light emission and energy transport in light-emitting diodes (LEDs). In this paper, we establish the physical and operational requirements for reaching the efficiencies needed for observing ELC in the III–V intracavity double-diode structures at high powers. The experimentally validated modeling framework used in this paper, coupling the drift-diffusion charge transport model with a photon transport model, indicates that the bulk properties of the III–V materials are already sufficient for ELC. Furthermore, the results suggest that the bulk power conversion efficiency of the LED in the devices, which allowed the experimentally measured record high coupling quantum efficiency of 70%, already exceeds 115%. However, as shown here, direct observation of ELC by electrical measurements still requires a combination of a more efficient suppression of the nonradiative surface recombination at the LED walls and the reduction of the detection losses in the photodetector of the intracavity structures. [ABSTRACT FROM AUTHOR]

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

This paper presents a new method for modeling the nonideal conductance response (CR) of synaptic devices. Unlike previous studies, which utilize physical device properties for modeling, this paper only uses the measured CR data. This allows the proposed modeling method to be easily applied to various types of synaptic devices without considering the unique physical properties of each device. An efficient piecewise linear approximation method which offers a tradeoff between computational complexity and simulation accuracy of neural networks is also presented to generate a linear device model out of nonlinear CR data. In addition, model parameters, which reflect the nonideal characteristics of the CR such as abrupt and asymmetric conductance changes, conductance variation, and limited conductance dynamic range, are introduced to evaluate the network performances in the presence of the nonidealities. By adjusting the model parameters, the desired CR satisfying the network performance requirements can be derived for device development. A three-layer neural network employing the device model has been designed and trained for the MNIST data set in order to demonstrate the application of the model to system-level simulations and verify the effectiveness of the modeling method. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we systematically evaluate the variation in the reversal delay of a nanomagnet driven by a longitudinal spin current under the influence of thermal noise. We then use the results to evaluate the performance of an all-spin-logic (ASL) circuit. First, we review and expand on the physics of previously published analytical models on stochastic nanomagnet switching. The limits of previously established models are defined, and it is shown that these models are valid for nanomagnet reversal times <200 ps. Second, the insight obtained from previous models allows us to represent the probability density function (pdf) of the nanomagnet switching delay using the double exponential function of the Fréchet distribution. The pdf of a single nanomagnet is extended to more complex nanomagnet circuit configurations. It is shown that the delay-variation penalty incurred by nanomagnets arranged in parallel configuration is dwarfed by the average delay increase for nanomagnets arranged in a series configuration. Finally, we demonstrate the impact of device-level performance variation on the circuit behavior using ASL logic gates. While the analysis presented in this paper uses an ASL-AND gate as the prototype switching circuit in the spin domain, the physical concepts are generic and can be extended to any complex spin-based circuit. [ABSTRACT FROM PUBLISHER]

In this paper, we present a comprehensive study of multisection, velocity-tapered slow wave structures (SWSs) for highly efficient backward-wave oscillators (BWOs). The SWS velocity variation profiles are characterized by mathematical functions. Using particle-in-cell (PIC) simulations, the efficiencies of these SWSs are obtained along with their oscillation frequency response to variations in beam voltage. This paper is aimed at determining the optimum SWS profiles for high-efficiency BWO operation along with the corresponding tunability. The profile with the highest possible efficiency is fabricated and cold tested to experimentally determine and validate the underlying efficiency enhancement mechanisms. This resulting cold test experiment demonstrates higher order dispersion in the form of multiple secondary inflection points. PIC simulations using this SWS design predict an output power of 8.25 MW at 2.62 GHz corresponding to a peak power conversion efficiency of 70%. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

Efficiency roll-off defined as the rapid efficiency drop by increasing the electrical current density is a major issue in the design of novel organic light-emitting diodes (OLEDs) based on thermally activated delayed fluorescence (TADF). In this paper, it is shown that efficiency enhancement and suppression of efficiency roll-off in TADF OLEDs can be accomplished by broadening the exciton generation zone by precisely tuning the doping concentration of the TADF emissive material in the host matrix. This universal and simply tunable parameter can be applied to any TADF OLED to further enhance its performance characteristics. In this paper, a typical TADF OLED with realistic parameters is numerically investigated by solving the charge carrier transport and excitonic equations and taking into account all relevant processes such as triplet–triplet annihilation, triplet–polaron, and singlet–triplet quenching, and (reverse) intersystem crossing. It is shown that the internal quantum efficiency (IQE) decreases at very low and very high doping densities due to exciton distribution nonuniformity and charge balance factor reduction, respectively. Power efficiency depends on the IQE as well as the potential drop across the emissive layer and decreases at very low doping densities even for a perfectly balanced device; however, the reduction for an unbalanced device is much more substantial. For a perfectly balanced device with an emissive layer thickness of 30 nm, at a current density of 10 mAcm−2, the IQE can be increased from 18% to more than 58% by decreasing the doping concentration from ${c}= {15}$ % to 0.5%. Power efficiency reaches its peak value of 38 lm/W at 1.4% doping. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

Modeling of the packaged wind sensor operating on constant power (CP) mode is proposed in this paper. The proposed model is based on the theory of heat conduction and forced convection. The presented model indicates that the total output dc voltage is proportional to the square root of the wind speed, and ${V}_{x}$ , as well as ${V}_{y}$ , varies with the wind direction based on cosine function. The wind sensor is fabricated by microelectromechanical systems (MEMS) technology and packaged with the glue. The test is performed in the wind tunnel and the measured results indicate an agreement with the presented model. The relative error of voltage for the wind speed is less than 14% up to 30 m/s, while that for the wind direction is no more than 10.7% from 0° to 360°. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{\text {sp,on}}$). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge (${Q}_{g}$) and miller capacitance (${c}_{\text {rss}}$) compared to SJ MOSFET. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage (${V} _{\textsf {TH}}$) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance (${I}$ – ${R}$) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs. [ABSTRACT FROM AUTHOR]

This paper illustrates the usefulness of the physics-based compact device models in investigating the impact of device behavioral nuances on the operation and performance of the circuits and systems. The industry standard MIT virtual source gallium nitride high electron-mobility transistor (GaN HEMT) (MVSG) model is used as the modeling framework to understand the operation of the GaN HEMTs and study the key device–circuit interactions in the GaN-based high-frequency and power conversion circuits. Details of the core model equations along with their physical underpinnings are presented along with the benchmark tests to verify the model’s convergence robustness and simulation accuracy. The usefulness of such a compact model in circuit design is highlighted through examples of the GaN-based high-voltage converter and RF-power amplifiers. It is shown that the slew-rates in hard-switched buck converters are determined by the dynamic charge distribution among the field plates in GaN HEMTs, indicating the importance of the device-level effect on circuit performance. Likewise, it is shown using the MVSG model that the performance metrics, such as drain efficiency and linearity, of the GaN RF-power amplifiers are heavily dependent on the device-level effects, such as access-region depletion, thermal effects, and charge-trapping effects. These GaN-based circuits designed using the MVSG model can be used as the example cases to demonstrate the importance of the accurate physical compact models in designing high performance circuits and systems in emerging technologies. [ABSTRACT FROM AUTHOR]

Ballistic (collision free) and drift-diffusive (collision dominated) transport mechanisms are both present in graphene, and they together contribute in the current conduction in a graphene FET (GFET). In this paper, we propose an analytical drain current model based on ballistic (${n}_{B}$) and drift-diffusive (${n}_{D}$) charge densities, backscattering coefficient (${R}$), and quasi-ballistic mobility ($\mu _{\text {eff}}$). ${n}_{B}$ is calculated using the McKelvey flux theory and ${n}_{D}$ using the surface potential approach. A closed-form analytical expression is derived for the backscattering coefficient, which is valid under both low and high electric field conditions. The effective quasi-ballistic mobility is obtained by considering both scattering-dominated and scattering free mobilities. The proposed model is well aligned with experimental data, in all regions of operation, for single- and double-gate GFETs. [ABSTRACT FROM AUTHOR]

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model. [ABSTRACT FROM AUTHOR]

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion. [ABSTRACT FROM AUTHOR]

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior. [ABSTRACT FROM AUTHOR]

In this paper, the impact of charge transfer doping on the variability of multiwalled carbon nanotube (MWCNT) local interconnects is studied by experiments and simulations. We calculate the number of conducting channels of both metallic and semiconducting carbon nanotubes as a function of Fermi level shift due to doping based on the calculation of transmission coefficients. By using the MWCNT compact model proposed in Part I of this paper, we study the charge transfer doping of MWCNTs employing Fermi level shift to reduce the performance variability due to changes in diameter, chirality, defects, and contact resistance. Simulation results show that charge transfer doping can significantly improve MWCNT interconnect performance and variability by increasing the number of conducting channels of shells and degenerating semiconducting shells to metallic shells. As a case study on an MWCNT of 11 nm outer diameter, when the Fermi level shifts to 0.1 eV, up to ~80% of performance and standard deviation improvements are observed. Furthermore, a good match between experimental data and simulation results is observed, demonstrating the effectiveness of doping, the validity of the MWCNT compact model and proposed simulation methodology. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

Tremendous improvements in the fabrication technology have allowed to scale the physical dimensions of the transistors and also to develop different promising 3-D architectures that may allow continuing Moore’s law. In this paper, we perform a comparative delay analysis of different 3-D device architectures and study the impact of surface roughness and self-heating on the on-current using a comprehensive in-house simulation framework comprising Schrödinger, Poisson, and Boltzmann transport equation solvers and comprising relevant scattering mechanisms and self-heating. Our results highlight that parasitic capacitance can alter the relative ranking of the architectures from delay point of view. We demonstrate that surface roughness can cause architecture and material-dependent current degradation, and hence, it is necessary to account for it in simulation-based benchmarking different architectures. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. [ABSTRACT FROM AUTHOR]

This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction to the infinite quantum well. When restricting the analysis to the first and second quantized states, the free carrier charge distribution and the current in an ultrathin body JLDG FETs are in agreement with numerical TCAD simulations in all the regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. [ABSTRACT FROM AUTHOR]

Silicon-on-insulator (SoI) technology has been reported as a technique to improve electrical characteristics over those of bulk MOSFETs. However, this approach results in the disadvantage of increased drain-induced barrier lowering (DIBL) due to drain electric flux (or field) passing through the buried oxide (BOX) layer. Against such a background, the development of a method to easily estimate the amount of this electric flux is expected to support the prediction of BOX-related DIBL. This paper involved the investigation of a model-derived analytically using conformal mapping techniques to represent the amount of flux in subthreshold regions of ground-plane SoI MOSFETs. To create the model, this paper was divided into two parts. In Part I, as preparation for model development, the relationships between coordinates in MOSFETs and potential/stream function were derived using conformal mapping, and related validity was verified. In Part II, the model’s development was considered based on these relationships, and its validity was also verified. [ABSTRACT FROM PUBLISHER]

This paper presents a compact analytical I – V model for short-channel double-gate transition metal dichalcogenide filed-effect transistors in the subthreshold region. A closed-form expression is proposed for the characteristic length in the scale length approach, which is based on physical device parameters. It is then used to find the channel potential and drain current in the subthreshold region. This model is verified with the numerical results of a nonequilibrium Green’s function (NEGF) simulator. There is good agreement between the results of the proposed model and the numerical NEGF simulations in the subthreshold region, while it captures the effects of the device’s physical parameters. [ABSTRACT FROM PUBLISHER]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

This paper reports the performance of midwave infrared (MWIR) electron-injection avalanche photodiode (e-APD) fabricated using graded bandgap HgCdTe epilayers. Carrier transport in the e-APD is dominated by drift transport due to the built-in electric field associated with gradient in the bandgap. Carriers encounter fewer collision events before entering the multiplication region as the dead space effect is reduced. On-set of generation and multiplication processes is controlledmore effectively. High gain indicates a reduced in-elastic scattering by phonon-emission due to gradient. Quantum efficiency above 80% is achieved in merely 2–3- \mu \textm -thick absorbing layer because of more efficient collection of the photogenerated carriers. Lower generation volume is beneficial in terms of low dark current. The generation is confined in the vicinity of themultiplication region. Generated carriers are readily evacuated from the absorber region under the built-in electric field. An order of magnitude improvement over the state-of-the art performance in MWIR e-APD is achieved by introducing a controlled energy bandgap gradient in the HgCdTe epilayers. [ABSTRACT FROM AUTHOR]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]

Closed form model for skin and proximity effect is necessary for GSI interconnects. In this paper, exact formulation for current distribution inside multiwall carbon nanotube (MWCNT) bundles is derived using multiconductor transmission line model. The current distribution is different from copper wires and it is geometry dependent because of kinetic inductance and quantum capacitance. This current distribution is used to compute and formulate high frequency resistance of MWCNT bundles. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections $+$ silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more. [ABSTRACT FROM AUTHOR]

This paper exhibits systematic results for lateral light emitting diodes (LEDs) with various conditions. The simulation results and circuit model are both included to describe the current spreading effect at the same time. A fully 2-D model that solves Poisson and drift-diffusion equations to investigate the current flow and radiative recombination distribution specifies the uniformity of the carrier distribution, which is combined with the Monte Carlo ray tracing technique to calculate the light extraction efficiency (LEE). This paper focuses on the modulation of the transparent conducting layer. In addition, this paper will discuss bottom emission LEDs addressing the current spreading effect and LEE compared with top emission LEDs. We also examine the droop effect to verify our discussion. A thorough analysis provides deep insights for achieving high efficiency lateral LEDs. [ABSTRACT FROM PUBLISHER]

Investigating random telegraph signals (RTS) observed in MOS devices is important for studying the gate-oxide defect characteristics and developing simulation and modeling tools in highly scaled devices. In this paper, we are presenting a comprehensive, variable-temperature, single-to-multitrap scalable RTS model and a simulation tool (RTSSIM) based on the first principles, and supported by experimental data. The physical and electrical characteristics of the actual oxide defects are considered, such as trapping barrier energy, capture cross section, trap-binding enthalpy, entropy change with emission, Coulombic scattering effect, and the trap location. Experimentally obtained time-domain switching data and RTS traces reconstructed by the developed simulation tool are compared for assessing the accuracy of the modeling. In this paper, we identified the trap species responsible for the RTS as an unrelaxed neutral oxygen deficiency center ( V^0 ODC II) with measured and theoretically verified relaxation energy of 1.11, 1.25, and 0.60 eV. RTSSIM is a tool used to mimic or reproduce a given noise measurement on a particular device. The simulation tool shows over 92% accuracy in replicating the RTS and trap characteristics. The model also represents the first realistic simulation of multilevel RTS. [ABSTRACT FROM AUTHOR]

As a promising new generation of nonvolatile memory, HfO2-based resistive random-access memory (RRAM) has attracted extensive research. However, the problem of data retention has prevented its industrial production as embedded memory. In this paper, from the microscopic understanding, a Monte Carlo simulator is developed to investigate the effects of an oxygen reservoir layer (ORL) on the resistance instability of HfO2-based RRAM. The evolution of conductive filaments (CF) during the retention degradation is visualized by our simulation considering the physical mechanisms of oxygen ions absorbed and released by the ORL. The simulation results are further validated with experiments to provide the prediction of retention performance of RRAMs with different ORLs and operation schemes. [ABSTRACT FROM AUTHOR]

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters. [ABSTRACT FROM AUTHOR]

In this paper, an improved physics-based virtual-source (VS) model to describe transport in quasi-ballistic transistors is discussed. The model is based on the Landauer scattering theory, and incorporates the effects of: 1) degeneracy on thermal velocity and mean free path of carriers in the channel; 2) drain-bias dependence of gate capacitance and VS charge, including the effects of band nonparabolicity; and 3) nonlinear resistance of the extrinsic device region on gm -degradation at high drain currents in the channel. The improved charge model captures the phenomenon of reduction in VS charge under nonequilibrium transport conditions in a quasi-ballistic transistor. [ABSTRACT FROM AUTHOR]

In spite of the reporting of several mathematical approaches dealing with the behavior of the superjunction MOSFET’s specific resistance, a study for the asymmetrical pillar (when the width of the n-pillar and the p-pillar are not the same at a given cellpitch) has not been carried out yet. When the width of one of the pillar (say n-pillar) is modified, the doping concentration (say donor) should be changed to maintain a charge balance condition. This in turn, changes the width of the depletion region, due to the parasitic JFET effect and as a result the effective on-state conduction path. This raises the question whether the best tradeoff between the specific on-state resistance and the breakdown voltage could be achieved by employing the conventional assumption of the same width of the n and p pillars. This paper clarifies the best option for the width of each pillar when designing a superjunction MOSFET and adapts the figures of merit to take into account the asymmetrical superjunction cell. [ABSTRACT FROM AUTHOR]

This paper presents a charge compensation phototransistor for high-dynamic-range CMOS image sensors (CIS). With a built-in charge compensation mechanism, the photoresponse of the proposed device can switch between the linear mode and the logarithmic mode automatically, according to the incident light intensity. In particular, the device does not saturate until approximately 0.5 W/cm2, almost 5 times the brightness of the sun. Therefore, CIS with this proposed phototransistor demonstrates a measured dynamic range of 167 dB, and an output swing of more than 2 V without amplification. The nonideal behavior of the proposed device due to the thermal effect and the parasitic resistances is investigated when exposed with high incident light intensity. In addition, the nonuniform response of the pixel array is exhibited and analyzed. [ABSTRACT FROM AUTHOR]

In this paper, the effect of a choice of the tunneling path approach on electrical characteristics of the silicon tunnel field-effect transistor (TFET) is theoretically investigated with the use of a developed 2-D semiclassical numerical simulator and a nonlocal band-to-band tunneling generation model. Three different tunneling path approaches are defined and examined: horizontal path, maximum valence band gradient, and minimum tunneling distance. Double-gate (DG) and single-gate (SG) transistor structures are considered, and effects of the silicon body thickness and the gate–source overlap are investigated. The differently defined tunneling paths lead to significantly different on currents. It is shown that the minimum tunneling distance approach results in the highest tunnel current, whereas the horizontal path approach underestimates the current, especially for thick semiconductor body layers and the SG transistor structures. A choice of the tunneling path approach can be crucial for the accuracy of modeling the drain current of the TFETs. [ABSTRACT FROM AUTHOR]

Controlling the electron and hole current is a crucial requirement in organic light-emitting devices (OLEDs) as it has a significant impact on the charge balance factor and the location of exciton generation zone. In this paper, via a self-consistent solution of the 3-D master equation approach coupled to Poisson’s equation, it is shown that the charge carrier and current density can be controlled in a wide range in OLEDs by utilizing a host–guest structure in the charge carrier transporting layers of the device. To this end, first, the impact of the injection energy barrier height, trap depth, and blending ratio on the charge carrier and current density is investigated. Second, the strategy of partially blending the hole or electron transporting material with an appropriate guest material is presented, and it is shown that by employing this strategy, current density can be enhanced over two orders of magnitude for high injection energy barriers, where the charge injection is most difficult. Moreover, this strategy guarantees that the transport of charge carriers to the emissive layer is conducted by the hole or electron transporting material itself rather than the guest material which is important as hole and electron transporting materials must fulfill other requirements such as high charge carrier mobility or specific excitonic energy levels. [ABSTRACT FROM AUTHOR]