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Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

In this paper, a distributed circuit model for on-die power distribution network in single and 3-D ICs is developed, and a set of difference equations are derived based on the circuit model and numerically solved using the finite-difference method. Both IR-drop and simultaneous switching noise, two components of power supply noise (PSN), are iteratively solved in time domain, thereby enabling a transient analysis of PSN. Under the assumptions that on-die power/ground pads, power density, and decoupling capacitors are uniformly distributed, PSN within a unit cell is accurately simulated with <1% error compared with HSPICE simulation. By reducing modeling grid fineness, the numerical modeling approach is applied to a full chip that has multiple blocks with nonuniform power/ground pads, power density, and decoupling capacitance density. Based on full-chip modeling, the PSN distribution of a two-die stack is simulated, and the impact of increasing decoupling capacitance and power/ground pads is investigated. [ABSTRACT FROM PUBLISHER]

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the \FOMT. [ABSTRACT FROM PUBLISHER]

To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, the study of the application of a lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-\mu\m LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. [ABSTRACT FROM AUTHOR]

A two-point expression of effective drive current ( Ieff\PG) for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of Ieff\PG estimates the PG latency with a reasonable accuracy (relative error <15%) under different technology nodes from 90 to 20 nm and a wide range of biasing conditions including gate overdrive voltage up to 0.4 V and nonzero body bias between −0.3 and 0.3 V. The effective drive current expression is simple to use, independent of process technologies, and maintains accuracy when transistors are scaled down to deep submicron regime with severe nonidealities such as drain-induced barrier lowering. Ieff\PG provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( Ieff\inv) is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of Ieff\PG is discussed, which illustrates the Ieff\PG does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( Ieff\inv) do. [ABSTRACT FROM PUBLISHER]

Resistive switching memory (RRAM) devices generally rely on the formation/dissolution of conductive filaments through insulating materials, such as metal oxides and chalcogenide glasses. Understanding the mechanisms for filament formation and disruption in resistive switching materials is a critical step toward the development of reliable and controllable RRAM for future-generation storage. In particular, the capability to control the filament resistance and the reset current through the compliance current during filament formation may provide a key signature to clarify the switching mechanism. This paper provides a physically based explanation for the universal resistance switching in bipolar RRAM devices. A numerical model of filament growth based on thermally activated ion migration accounts for the resistance switching characteristics. The same physical picture is extended to numerically model the reset transition. The impact of migration parameters and experimental setup on the set/reset characteristics is discussed through numerical simulations. [ABSTRACT FROM AUTHOR]

The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current–voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior. [ABSTRACT FROM PUBLISHER]

This paper presents a nanotechnology-based high-power-density and low-power-loss on-chip power inductor for dc–dc switching power converters. This power inductor utilizes a composite of bundled multiwalled (concentric) carbon nanotubes (BMWCNTs) and Fe (iron) in order to achieve high performance in a small size. Titanium (Ti) is then added as a coating material on the BMWCNT-based power inductor. The BMWCNT-based power inductor with a single layer and three turns occupies an area of \200\ \mu\m \times \200\ \mu\m. It exhibits an inductance of 206 nH, a quality factor of 427 at 20 MHz, and a dc rated current of 100 mA. The power inductor size and the performance characteristics are competitive with state-of-the-art power inductors. The design, analysis, modeling, and simulation results of the BMWCNT-based power inductor are presented and compared with state-of-the-art conventional power inductors from the literature. [ABSTRACT FROM AUTHOR]

The resistive-switching memory (RRAM) is currently under consideration for fast nonvolatile memory thanks to its relatively low cost and high performance. A key concern for RRAM reliability is stochastic switching, which impacts the operation of the digital memory due to distribution broadening. On the other hand, stochastic behaviors are enabling mechanisms for some computing tasks, such as physical unclonable function (PUF) and random number generation (RNG). Here, we present new circuit blocks for physical RNG, based on the coupling of two RRAM devices. The two-resistance scheme allows to overcome the need of probability tracking, where the operation voltage must be tuned to adjust the generation probabilities of 0 and 1. Probability tests are proved successful for one of the three proposed schemes. [ABSTRACT FROM AUTHOR]

A 250 V thin-layer SOI technology based on a 1.5- \mu \textm -thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 \mu \textm to only 1.5 \mu \textm . The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird’s beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of −329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology. [ABSTRACT FROM AUTHOR]

For the first time, this work demonstrates a switchless dual-frequency (472 MHz and 1.94 GHz) reconfigurable CMOS oscillator using a single piezoelectric AlN microelectromechanical-systems resonator with coexisting S\0 and S\1 Lamb-wave modes of vibration. High performance (high quality factor Q and electromechanical coupling factor kt^{2} for a resonator and low phase noise for an oscillator) has been achieved for both the resonator and oscillator in terms of dual-mode operation. In particular, 1.94-GHz operation has the best phase noise performance at 1-MHz offset when compared with all previously reported CMOS oscillators that work at a similar frequency. [ABSTRACT FROM AUTHOR]

Reports a study which described a highly reliable and fast-switching intelligent power integrated circuit (IPIC) for a high-side solenoid drive. Design of IPIC; Experimental framework of the study; Conclusion.

A novel “slingshot” pull-in operation is proposed to lower the operation voltage (${V}_{\text {DD}}$) of nanoelectromechanical (NEM) memory switches for the implementation of monolithic 3-D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. According to the theoretical calculation and experimental data, the proposed “slingshot” pull-in operation lowers ${V}_{\text {DD}}$ of the NEM memory switches by ~0.84 times. It contributes to the overall ${V}_{\text {DD}}$ reduction and chip density boost of M3D CMOS-NEM RL circuits. [ABSTRACT FROM AUTHOR]

A polymer solid-electrolyte (PSE) switch has been embedded in a 90-nm-node CMOS featuring a forming-less programming and extremely high on/off ratio of \10^5. A fast programming of 10 ns is also demonstrated for 50-\nm\phi 1 k-b array by introducing the PSE switches integrated with a fully logic compatible process below 350 ^\circ\C. A high free volume in the PSE is supposed to result in the smooth formation of the Cu bridge without destroying the electrolyte, thereby also resulting in forming-less programming and high breakdown voltage. High disturbance reliability (T50; 50% fail) is extracted to be over 10 years at operation condition. The improved switching characteristics enable us to accurately program the crossbar circuit in a practical scale (32 \times 32) without cell transistors. The developed switch is a strong candidate for realizing a low-power and low-cost nonvolatile programmable logic. [ABSTRACT FROM AUTHOR]

A valid resistive dielectric film with excellent state switching is successfully demonstrated in a contact resistive RAM (CR-RAM) structure fabricated by 90-nm CMOS logic technology. This unique CR-RAM cell is realized by placing the RRAM material on top of the \N+ silicon with a very small resistive switching area limited by the source line contact. In addition, the set and reset current of the new RRAM cell can be both well controlled and reduced by the choice of 1T + 1R structure. Furthermore, by adjusting operation conditions, an optimized high-speed and good-sensing margin cell is obtained with low levels of set and reset currents. Finally, the lower operation voltages and less current stress significantly improve data reliability, even after long-term high temperature and more than 1000 K cycling stresses. [ABSTRACT FROM AUTHOR]

Two-terminal switching performances are observed in a new AlGaAs--GaAs--InAlGaP npn bulk-barrier optoelectronic switch (BBOS) with an AlGaAs--δ(n+)--GaAs--InAlGaP collector structure. The device shows that the switching action takes place from a low-current state to a high-current state through a region of negative differential resistance (NDR). The transition from either state to the other may be induced by an appropriate optical or electrical input. It is seen that the effect of illumination increases the switching voltage Vs, holding voltage VH, and holding current IH, and decreases the switching current IS, which is quite different from other results reported. In addition, it possesses obvious NDR even up to 160 °C. This high-temperature performance provides the studied device with potential high-temperature applications. [ABSTRACT FROM AUTHOR]

Deals with a study which examined a fabricated novel multiple-state switching device based on an InP/A1InGaAs heterojunction bipolar transistor structure. Experimental setup; Results and discussion; Conclusion.