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It is my great pleasure to introduce the Seventh Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, and November 2009. During the six-year interval since the last special issue, significant changes have occurred in the field of solid-state image sensors. This is due, in particular, to the drive for low-power, high integration, compact imaging systems. Now that the speed of pixel shrinkage is slowing down, various new technologies are being developed to increase the functionality of the sensors, to make them more compact, to make them faster, to increase their dynamic range, etc. Papers reflecting these trends in the image sensor technology are well represented in this special issue. [ABSTRACT FROM AUTHOR]

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node. [ABSTRACT FROM PUBLISHER]

In this paper, we develop a statistical model for random telegraph noise (RTN) related low-frequency noise (LFN). With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We clarify why the variability of RTN/LFN does not follow a 1/ $\surd $ area dependence. The model explains the effect of the halo implanted regions on the LFN statistics and the large variability of long channel devices found under certain bias conditions, which can be as large as that of short channel devices. We show that the LFN of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results, we derive that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. We also demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. [ABSTRACT FROM AUTHOR]

In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( L\mathrm{ ch} ) from 100 to 40 nm, a NW height ( H\mathrm{ NW} ) of 10 nm, the NW widths ( W\mathrm{ NW} ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( g\max ) as high as 1057~\mu \textS/\mu \textm are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters. [ABSTRACT FROM PUBLISHER]

In this paper, we report the development of a high- k /metal gate stacking process to reduce the effective gate resistance, and circuit level validation results in 28-nm gate first integrated high- k /metal gate CMOS devices. To achieve this, millisecond annealing was adopted and the silicon (Si) gate and TiN gate electrode thicknesses were controlled. The recrystallized poly-Si gate by millisecond annealing improved the performance of the ring oscillator (RO) by 15% and the minimum operating voltage ( V\min ) of the high-frequency test pattern (HFTP) by 34 mV. The poly-Si gate improved the uniformity of the boron concentration and suppressed localized low doping area at the bottom of the gate. When the Si gate thickness was reduced by 10 Å with respect to the reference (POR) value, the performance of the RO improved by 5% and V\min of HFTP improved by 20 mV due to the shorter boron diffusion distance. A 10- Å thicker TiN gate electrode improved V\min of HFTP by 30 mV, since the thicker TiN reduced the TiN/Si gate interface resistance. [ABSTRACT FROM AUTHOR]

In this paper, a novel CMOS single-photon avalanche diode (SPAD) is presented, and the device is designed using a vertical p-i-n diode construction. The p-i-n diode with a wide depletion region enables a low-noise operation. The proposed design achieves dark count rates of 1.5 cps/ \mu \textm^2 at 11 V excess bias, while the photon detection probability (PDP) is greater than 40% from 460 to 600 nm. Through the operation at very high excess bias voltages, it is possible to reach the PDP compression point where sensitivity to the breakdown voltage is low, thus ensuring high PDP uniformity; this feature makes it, especially, suitable for multimegapixel SPAD arrays. [ABSTRACT FROM AUTHOR]

This paper presents a time-of-flight (TOF) range imager with high-range resolution. The range imager employs a TOF measuring technique using an impulse photocurrent response and a high-speed lock-in pixel based on a draining-only modulation. To address a skew problem in a 2-D array of the pixels, a column-wise gating-clock skew calibration was implemented. Each pixel has an in-pixel buffer and decoupling capacitor to reduce row-wise skew. A test-implemented imager has $132 \times 120$ effective pixels. The skew calibration circuit successfully reduce the skew from 173 to 8 psrms. The range resolution was achieved to be 0.25 mm with a 32-mm range, which corresponds to a 1.7-ps time resolution. [ABSTRACT FROM AUTHOR]

This paper presents a pathfinder binary image sensor for exploring low-power dissipation needed for future implementation of gigajot single-bit quanta image sensor (QIS) devices. Using a charge-transfer amplifier design in the readout signal chain and pseudostatic clock gating units for row and column addressing, the 1-Mpixel binary image sensor operating at 1000 frames/s dissipates only 20-mW total power consumption, including I/O pads. The gain and analog-to-digital converter stages together dissipate 2.5 pJ/b, successfully paving the way for future gigajot QIS sensor designs. [ABSTRACT FROM AUTHOR]

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect. [ABSTRACT FROM AUTHOR]

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- \mu \textm technology with 110 column-parallel ADC channels and 10.08- \mu \textm \times 750 - \mu \textm column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- \mu \texts sampling rate with 120- \mu \textW power consumption per channel. [ABSTRACT FROM AUTHOR]

In this paper, an inverter logic gate has been successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates. [ABSTRACT FROM PUBLISHER]

The RC-based power-rail electrostatic discharge (ESD) clamp with nMOS of large size has been widely utilized to enhance the ESD robustness of CMOS integrated circuits. However, such circuit design that only detects the rising time of ESD pulse may be accidentally triggered in some conditions, such as fast power-ON, hot-plug, and envelope tracking applications. In this paper, a new power-rail ESD clamp circuit with transient and voltage detection function has been proposed and implemented in a 0.18-µm 1.8-V CMOS technology. The measurement results from the silicon chip have demonstrated that the new proposed power-rail ESD clamp circuit with adjustable minimum starting voltage (Vstarting) can achieve good ESD robustness and avoid triggering under fast power-ON condition. In addition, the proposed circuit has a low standby leakage current of 270 nA at 125 °C under normal power-ON condition. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate, for the first time, 3-D Monolithic integration of short-channel replacement metal gate InGaAs n-FinFETs on fully-depleted silicon-on-insulator CMOS, with TiN/W interlayer contacts. Top layer InGaAs nFETs feature raised source-drain and bottom layer CMOS has Si raised source-drain for nFETs, SiGe raised source-drain for pFETS, implants, silicide, and TiN/W plug contacts. Scaled gate length (Lg) of 15 nm is achieved on bottom layer Si n- and pFETs, while the top layer InGaAs n-FinFETs are scaled to Lg of 25 nm. A densely integrated 3-D 6T-static random access memory circuit with planar InGaAs nFETs stacked on Si pFETs is demonstrated by taking advantage of the interlayer contacts. This yields significant area reduction when compared with 2-D layouts. [ABSTRACT FROM AUTHOR]

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V \(_{\rm TH}\) shifts and fluctuations, which are even visible during the I \(_{D}\) –V \(_{G}\) tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times \(\tau _{c}\) and \(\tau _{e}\) , and their impact on V \(_{\rm TH}\) as a function of gate voltage V \(_{G}\) and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V \(_{G}\) swing and operational temperatures. [ABSTRACT FROM PUBLISHER]

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits. [ABSTRACT FROM PUBLISHER]

As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead. [ABSTRACT FROM PUBLISHER]

This paper investigates feasible inverter configurations based on co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb platform. Based on 3-D full-quantum simulations, the considered devices feature steep subthreshold slopes and relatively high on- currents and are combined into two inverter designs. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights potential of the proposed TFET implementations to perform up to 10\times and 100\times faster in low operating power and low standby power environments, respectively. The comparison is conducted at low supply voltages (VDD=0.25~\rm V) and for equal levels of static power consumption. The proposed TFET-based platform is thus expected to be a good candidate for low-voltage/low-power applications in near-future technology generations. [ABSTRACT FROM AUTHOR]

In this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, which indicates that the LWR ACF is composed of two parts: one involves LER information; the other involves the cross-correlation of the two edges. Additional characteristic parameters for LER/LWR are proposed to represent the missing cross-correlation information in conventional approaches of LER/LWR description, other than LER/LWR amplitude and auto-correlation length. An improved simulation method for correlated LERs is also proposed, which can provide helpful guidelines for the characterization, modeling, and the optimization of LER/LWR in nanoscale CMOS technology. The experimental results and device simulation results are discussed in detail in the part II of this paper. [ABSTRACT FROM PUBLISHER]

Bulk FinFET is the main technology option for sub-20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsic electrostatic discharge (ESD) performance. In this paper, the impact on ESD performance induced by the process options beyond 20-nm nodes is explored on the ESD protection diodes. [ABSTRACT FROM AUTHOR]

A new approach for protecting sensitive receivers through large attenuation and its realization on-chip is presented for the first time. This paper demonstrates the use of absorptive bandstop filters that gives anomalously deep notches for a given quality factor. This approach is used in a fabricated design example to isolate a sensitive wideband LNA from interference in 45-nm SOI complementary metaloxide-semiconductor (CMOS). For reconfigurable RF front-ends, a frequency-agile design is newly developed with Q tunable resonators because an absorptive bandstop filter must balance both intrinsic Q of the resonators and the resonant frequency of the filter. Therefore, the design requires variable resistors, variable capacitors, and intimate coupling of inductors of disparate values. The layout of overlapping inductors on closely spaced metal layers is required for proper absorptive properties. The size of one filter presented in this paper is 310 by 340 μm, making it the smallest absorptive bandstop filter demonstrated so far. Despite using small-size, on-chip low-Q resonators in the bandstop filter design, an attenuation level from 31 to 63 dB and a frequency tuning range from 2.9 to 4.3 GHz are achieved with potential to suppress potential interference or an image frequency signal. [ABSTRACT FROM AUTHOR]

This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the ION current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the ION current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate. [ABSTRACT FROM PUBLISHER]

As 3-D displays become more common, the demand for 3-D-related products is rapidly increased. Three-dimensional image sensors based on the time-of-flight (TOF) technique are one of these products and are applied to many applications. In this paper, a new pixel based on the continuous-wave modulation method was proposed to measure the TOF and was embedded in a test complementary metal–oxide–semiconductor (CMOS) image sensor. Compared with other range imagers, no complex control signals, high operating voltage, or multilevel control voltages are needed in this pixel. The chip, with 92 \times 30 pixels, was fabricated using the Taiwan Semiconductor Manufacturing Company's 0.18-\mu\m CMOS standard process, and a time-switched color measurement was applied to this rangefinder system. A pulse train of red, green, and blue lights is emitted sequentially from a light-emitting diode array. The distance is easily calculated from the phase differences, and the color information is estimated using the difference in reflection coefficients under a different light. The measured distance and color are compared with the actual distance and color-corrected images. A color range image with a distance error of 3.56 cm and an L^\ast a^\ast b color difference of 40.23 can be observed. This rangefinder system provides a new perspective to capturing a colored range image. [ABSTRACT FROM PUBLISHER]

In this paper we discuss the development of an indirect time-of-flight (ToF) pixel in the 0.11- \mu \textm CMOS image sensor technology. The pixel design is based on a pinned-photodiode structure with a novel vertical overflow drain (VOD) shutter mechanism used for fast modulation. We present the second generation of the pixel, with a greatly improved VOD structure that enables a fast shutter efficiency better than 1:100 and a deeper photodiode collection depth for better quantum efficiency in the near-infrared wavelengths. We present a new 6.7- \mu \textm pixel design with four pinned storage diodes (SDs) that feature in-pixel complete charge transfer and enable correlated-double-sampling readout as well as an almost simultaneous global shutter exposure of up to four interleaved frames to be used for the scene depth computation. The novel design features a low readout noise of 7.5e- and a full-well-capacity of 9500e- per SD (a total of 38 000e- per pixel). [ABSTRACT FROM PUBLISHER]

Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifinger gate structure (MFGS) empirically using 3-D technology computer aided design simulations. Thereafter, we use these stress models along with a model for INWE to establish a physics-based relationship between effective drive current and number of fingers in MFGS. We also design single-stage combinational standard cells and predict the values of their logical effort using our approach. The performance of the standard cells using our approach improves significantly compared with the conventional approach. Inverter chains (buffers) are representative and extensively used multistage circuits. Using our model of effective drive current, we propose a methodology to optimize the buffer designed and layout to maximize performance in stress-enabled technologies. We observe that the proposed methodology results in a significant reduction in power dissipation up to 35% and reduction in silicon area up to 43% as compared with the existing methodologies. [ABSTRACT FROM AUTHOR]

Electrical control of a magnetic tunnel junction (MTJ) through spin–orbit torques (SOTs) offers opportunities to introduce MTJs into high-performance, low energy applications. SOTs support a high-speed and energy-efficient three terminal MTJ with perpendicular-to-the-plane magnetization (PMTJ). The read path is separated from the write path, enhancing the reliability of the device. SOTs exhibit two coexisting contributions: 1) a damping-like torque and 2) a field-like torque. In this paper, a physics-based compact model for a three terminal PMTJ is presented, which accurately models the magnetic, electrical, and thermal behaviors of a PMTJ controlled through SOTs. The proposed compact model is validated with experimental data, exhibiting reasonable accuracy with an average error of <5.4%. The integration capability of the proposed compact model with CMOS technology is also demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P− implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P−/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications. [ABSTRACT FROM AUTHOR]

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of different iron (Fe) buffer doping profiles on trapping effects in microwave AlGaN/gallium nitride (GaN) high electron mobility transistors (HEMTs). We characterize not only the current collapse due to trapping in the buffer, but also the recovery process, which is important in the analysis of suitable linearization schemes for amplitude modulated signals. It is shown that the simple pulsed dc measurements of current transients can be used to investigate transient effects in the RF power. Specifically, it is revealed that the design of the Fe-doping profile in the buffer greatly influences the recovery time, with the samples with lower Fe concentration showing slower recovery. In contrast, traditional indicators, such as S-parameters and dc as well as pulsed $I$ – $V$ characteristics, show very small differences. An analysis of the recovery shows that this effect is due to the presence of two different detrapping processes with the same activation energy (0.6 eV) but different time constants. For highly doped buffers, the faster process dominates, whereas the slower process is enhanced for less doped buffers. [ABSTRACT FROM AUTHOR]

The manufacturing of high-efficiency III–V on Si multijunction solar cells needs the development of hybrid, i.e., adapted to both families of materials, solar cell processing techniques, able to extract the full photovoltaic potential of both the subcells. This fact especially impacts the processing of the silicon rear surface of the tandem, which cannot receive treatments commonly used in the single-junction Si solar cell industry [Al-back surface field (BSF), thermal SiO2, and so on], since these would result in an excessive thermal load that would deteriorate the III–V upper layers (top cell, tunnel junction, and buffer layer). However, the Si bottom cell requires an advanced design with good rear passivation, a good ohmic contact, and good carrier selectivity, so that its contribution to the efficiency of the tandem is maximized. Accordingly, in this paper, several low-temperature compatible rear-surface passivation techniques for the Si bottom subcell in a monolithic III–V/Si tandem solar cell are explored. In particular, aluminum BSFs, passivated emitter and rear cell (PERC)-like architecture, passivated emitter and rear locally diffused (PERL)-like architecture formed with low thermal loads, and heterojunction with intrinsic thin layer (HIT)-like processes are assessed using numerical simulations, and a comparison of the Si bottom cell performance for the mentioned alternatives in a GaAsP/Si dual-junction solar cell is presented. [ABSTRACT FROM AUTHOR]

Microelectromechanical switches are of interest for low-power circuit applications due to their minimal OFF state leakage current. This paper uses 22-nm CMOS fabrication technology and the clamped cantilever geometry as the basis for establishing design rules for electrostatic nanorelays and estimates the design parameters needed for nanorelay actuation. The adhesive pull-off force of various substrate/cantilever combinations is simulated using molecular dynamics with a force field that parameterizes van der Waals interactions, and measured using atomic force microscopy. Both methods show that for the substrates studied, H-passivated Si produces the least adhesive surface with adhesive pressure close to the critical pressure required for pull-out. Experimental results quantifying adhesion and electrical current conduction show that it is impossible to simultaneously meet the adhesion and current conduction requirements of a nanorelay. We show that contact adhesion is the key parameter limiting the scalability of electromechanical relays at the nanoscale. [ABSTRACT FROM AUTHOR]

In this paper, we propose and demonstrate an implantable CMOS image sensor with self-resetting pixels. The self-resetting function is implemented using a four-transistor Schmitt trigger inverter. The pixel has no counter for the number of self-resets, because the application does not require radiometric (linear) response. The pixel is fabricated using the 0.35- \mu \textm 2-poly 4-metal standard CMOS technology, which results in the pixel size of 15~\mu \text m \times 15 ~\mu \textm and a fill factor of 31%. The effective peak signal-to-noise ratio is >59 dB. An image sensor prototype comprising a $60\times 134$ pixel array is designed, and an implantable device is fabricated. As an example imaging experiment, we demonstrate blood-flow imaging of a rat-brain surface using the sensor. Intensity-change images are successfully obtained from the self-resetting pixel outputs with the image processing. [ABSTRACT FROM AUTHOR]

This paper presents a fast-gated CMOS image sensor (CIS) with a vertical overflow drain (VOD) shutter mechanism. The prototype imager includes two novel features: 1) the adaptation of the VOD shutter structure into a 0.18- \mu \textm CIS process and 2) the application of the VOD shutter for the purposes of time-resolved imaging with down to 5-ns pulsewidth. A 360-pixel $\times $ 180-pixel array with several 5.4- \mu \text{m} \times 5.4 - \mu \textm pixel types was implemented and tested, demonstrating 2-ns shutter rise/fall times and the 1:20 shutter contrast ratio for 850-nm pulsed illumination. These parameters, together with the uniformity of the shutter and the large full-well capacity of the pixel, are on par with the state-of-the-art of indirect time-of-flight and time-resolved imagers. The device structure and the special mode of operation that enables a fast gating are studied through the TCAD simulations and experimental results. Important design features that affect the pixel performance are illustrated in detail. [ABSTRACT FROM AUTHOR]

Stacks of metal gratings placed above a photodiode have been demonstrated to show a strong sinusoidal response to angle. Although these devices, called angle sensitive pixels (ASPs), enable new imaging modalities on CMOS, such as light field capture, their optical sensitivity is limited by the metallic gratings. In this paper, we provide a detailed characterization of the angular response of ASPs and report on a new set of optically efficient structures for angle detection. By analyzing the properties of the Talbot effect, we present a quantitative model for the angular sensitivity, $\beta $ , of an ASP and qualitatively describe the dependence of modulation depth, $m$ , on the grating parameters. We then describe structures that employ phase gratings and interleaved diffusion diodes to provide angle sensitivity while improving the quantum efficiency by $4\times $ . A post-CMOS process flow for the fabrication of phase gratings is described. Finally, we show that ASPs that use p+ diffusion diodes embedded in an n-well diode improve their modulation efficiency by over 50% compared with interleaved diodes that share the p-substrate. [ABSTRACT FROM AUTHOR]

In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on 1/f and thermal noise for a low-noise CMOS image sensor (CIS) readout chain. It is shown that dramatic noise reduction is obtained by using a thin-oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed in a 180-nm CIS process and embedding small arrays of the proposed new pixels together with state-of-the-art 4T pixels for comparison. The new pixels feature a pitch of 7.5 \mu \text{m} and a fill factor of 66%. A 0.4e- rms input-referred noise and a 185- \mu \text{V}$ /e- conversion gain are obtained. Compared with state-of-the-art pixels, also present onto the test chip, the rms noise is divided by more than 2 and the conversion gain is multiplied by 2.2. [ABSTRACT FROM AUTHOR]

This paper proposes a multibit pulsewidth modulated (PWM) delta–sigma ( \Delta \Sigma ) analog-to-digital converter (ADC) using a single-slope (SS) quantizer for a CMOS image sensor (CIS). In the proposed ADC, the multibit \Delta \Sigma modulation is performed by converting the pulsewidth of the PWM signal into multibit data using an SS quantizer. This suppresses the random noise by the multisampling operation and reduces the area of the multibit \Delta \Sigma ADC by adding a ramp signal to a single-bit \Delta \Sigma CIS process with a pixel array which has a Bayer patterned color filter and an image format of 580 \times 450 with a pixel size of 5 \mu \textm\times 5 \mu \textm . The size of the test chip is 4 mm \times 5 mm, including the area of the proposed channel ADC, which occupies only 10 \mu \text{m}\times 400 \mu \text{m}$ per channel. The measured results show a random noise of 65 \mu \text{V} and a dynamic range of 70.4 dB. [ABSTRACT FROM AUTHOR]

A growing number of on-chip inductors have been applied in the millimeter-wave IC design. The coupling effects between them have a negative impact on the performance of the circuit and each on-chip inductor. In this paper, a new equivalent-circuit model and a parameter extraction method for multiple on-chip inductors in the millimeter-wave region are proposed. The impacts of coupling effects on every on-chip inductor are comprehensive considered in the proposed parameter extraction method. The characteristics of the multiple on-chip-coupled inductors are analyzed, modeled, and measured. The test structures were fabricated by 0.18- \mu \textm and 90-nm CMOS processes. The inductances, quality factors, and S-parameters of the model agree well with the measured performance of on-chip-nested and side-by-side-coupled inductors over a wide frequency range from 10 MHz up to millimeter-wave frequency band. [ABSTRACT FROM PUBLISHER]

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R\mathrm{{\scriptscriptstyle ON}} and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device. [ABSTRACT FROM PUBLISHER]

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions. [ABSTRACT FROM PUBLISHER]

In this paper, a compact fractional-order equivalent circuit model is developed to characterize three types of metamaterial transmission lines (T-lines): 1) composite right-/left-handed transmission line T-line; 2) split ring resonator T-line; and 3) complimentary split ring resonator T-line, all designed in 65-nm CMOS process at millimeter-wave frequency region. With the consideration of frequency-dependent dispersion loss and nonquasistatic effect, the proposed fractional-order equivalent circuit model can compactly characterize the measured results with good agreement up to 325 GHz. [ABSTRACT FROM AUTHOR]

This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay. [ABSTRACT FROM AUTHOR]

We demonstrate a 980-nm laser-driven CMOS-enabled interdigitated back-contact (IBC) solar cell for biomedical applications. The design of this device leverages from the CMOS process to allow 2-D junction formation and uniform series resistance, but suffers from poor minority carrier properties in bulk substrate. This issue is partially solved in this paper by thinning down the substrate to 60~\mu m, leading to an ultimate efficiency of 15%. After inserting an emulated tissue loss, an 1.67- \mathrm{mm}^{2} IBC solar cell is capable of generating an electrical power of 159~\mu $ W under a concentrated illumination intensity of 10 mW, which is within the conservative limit to human skin. [ABSTRACT FROM AUTHOR]

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts. [ABSTRACT FROM AUTHOR]

In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]

In this paper, we report on an image sensor with an integrated focal-plane 2\,\times\,2 wire-grid polarizer for the visible spectrum, fabricated in a 65-nm standard CMOS technology. This imager enables the reconstruction of the polarization response for each pixel. Finite-difference time-domain method has been used to optimize the extinction ratio (ER) in the visible spectrum of a multilayered focal-plane wire-grid polarizer. Experimental results show that an ER of 16.35 dB is achieved with a standard error of \sim0.25\% between the experimental results and the fitting sinusoidal polarization response curve. Design guidelines for the wire-grid polarizer are derived based on numerical analysis and experimental results. Sensitivity ratio is defined to balance the tradeoff between the intensity sensitivity and polarization sensitivity of the imager. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power robust static random access memory (SRAM) using a novel quasi-Schottky-barrier ultrathin body and ultrathin buried oxide (UTBB) silicon-on-insulator (SOI) device. In the proposed device, the drain terminal is highly doped and a metallic source terminal is used. Given the proposed structure, asymmetric characteristics will be achieved according to the drain–source bias voltage ( V\text {DS}) . These characteristics of the proposed device are extensively analyzed and compared with a conventional symmetric UTBB SOI device. The asymmetry nature of the proposed device will lead to the mitigated read–write conflict of the 6T-SRAM cell. The simulation results show a leakage reduction of 18% at V\text {DD} = 1 V in comparison with the 6T-SRAM cell realized by conventional symmetric UTBB SOI device. Furthermore, in comparison with the conventional 6T-SRAM, the realized cell shows a 54% improvement in read static noise margin, 6.6% higher write margin, and $3.1\times $ faster write at the cost of a longer access time. To achieve a practical read access time, we utilize split bitline approach. [ABSTRACT FROM PUBLISHER]

Several emerging devices have been proposed to continue the CMOS scaling. To assess scalability, device and circuit variability estimation is essential. Variability in static noise margin (SNM) in a 6T-SRAM cell is a key metric to assess the impact of device-level variability at the circuit level. This is usually enabled by SPICE simulations, which needs device compact models. However, the development of a SPICE model usually takes a significant amount of time (e.g., a few years). In this paper, we present a method to enable the evaluation of the SRAM cell SNM variability based on the ID – VG distribution at various V\mathrm{ DS} values of a device (obtained either experimentally or from TCAD), which can enable this assessment before the development of a SPICE model. Thus, it enhances the accuracy by being able to capture the effects of full ID – VG distribution rather than just VT distribution. The method is validated against HSPICE for a variety of SRAM parameters, such as Read, Hold, and Write SNM, write trip point, and read current ( I\mathrm{ READ} ) to show excellent accuracy. The method also shows a $30\times $ improvement in computational efficiency over mixed-mode TCAD-based stochastic SRAM simulation. A case study for the comparison of recently proposed low-variability EDFinFET with FinFET is presented using this method. [ABSTRACT FROM AUTHOR]

We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18- \mu\m CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11\times faster speeds and 1.54\times lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics. [ABSTRACT FROM AUTHOR]

This paper presents an extended model for the CMOS-based ion-sensitive field-effect transistor, incorporating design parameters associated with the physical geometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics by taking into account the effects of nonidealities such as threshold voltage variation and sensor noise. The model is evaluated through a number of devices with varying design parameters (chemical sensing area and MOSFET dimensions) fabricated in a commercially available 0.35- \mu\m CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift, and noise were measured and compared with the simulated results. The first- and second-order effects are analyzed in detail, and it is shown that the sensors' performance was in agreement with the proposed model. [ABSTRACT FROM AUTHOR]

Through-silicon vias (TSVs) in 3-D integrated circuits (ICs), which are used for connecting different active layers, introduce an important source of coupling noise arising from electrical coupling between TSVs and the active regions. This paper, for the first time, presents compact models based on a fully analytical approach for the electrical coupling from a TSV to the active regions for a comprehensive set of 3-D IC substrate technologies including those with and without the high-conductivity buried layer in dual-well bulk CMOS technology in the presence of VDD/VSS rails. The models can be used during design validation of emerging 3-D ICs. The compact physical models are verified against full-wave electromagnetic (EM) simulations. A comparative analysis of the magnitude of the EM coupling noise for different 3-D technology scenarios, including both dual-well bulk CMOS and partially depleted silicon-on-insulator, is also presented. The compact models presented for dual-well bulk CMOS are subsequently employed for estimating the stay-away radius (safe distance) from the center of the TSVs to the active regions to minimize the impact of such coupling noise. In order to highlight the significance of the TSV to active-region EM coupling noise, a comparison is also made with the white noise in the active region and the flicker noise from the interface between the TSV oxide and silicon. [ABSTRACT FROM PUBLISHER]