Back to Search
Start Over
Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects.
- Source :
- IEEE Transactions on Electron Devices; Jan2013, Vol. 60 Issue 1, p383-390, 8p
- Publication Year :
- 2013
-
Abstract
- We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18- \mu\m CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11\times faster speeds and 1.54\times lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 60
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 84489926
- Full Text :
- https://doi.org/10.1109/TED.2012.2225150