Search

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

In this paper, the impact of charge transfer doping on the variability of multiwalled carbon nanotube (MWCNT) local interconnects is studied by experiments and simulations. We calculate the number of conducting channels of both metallic and semiconducting carbon nanotubes as a function of Fermi level shift due to doping based on the calculation of transmission coefficients. By using the MWCNT compact model proposed in Part I of this paper, we study the charge transfer doping of MWCNTs employing Fermi level shift to reduce the performance variability due to changes in diameter, chirality, defects, and contact resistance. Simulation results show that charge transfer doping can significantly improve MWCNT interconnect performance and variability by increasing the number of conducting channels of shells and degenerating semiconducting shells to metallic shells. As a case study on an MWCNT of 11 nm outer diameter, when the Fermi level shifts to 0.1 eV, up to ~80% of performance and standard deviation improvements are observed. Furthermore, a good match between experimental data and simulation results is observed, demonstrating the effectiveness of doping, the validity of the MWCNT compact model and proposed simulation methodology. [ABSTRACT FROM AUTHOR]

We report on the fabrication and characterization of field-effect transistors (FETs) based on chemical vapor deposited (CVD) graphene encapsulated between few layer CVD boron nitride (BN) sheets with complementary metal–oxide–semiconductor (CMOS) compatible nickel edge contacts. Noncontact terahertz time-domain spectroscopy (THz-TDS) of large-area BN/graphene/ BN (BN/G/BN) stacks reveals average sheet conductivity >1 mS/sq. and average mobility of 2500 cm2/V $\cdot $ s. Improved output conductance is observed in dc measurements under ambient conditions, indicating the potential for radio frequency (RF) applications. Moreover, we report a maximum voltage gain of 6 dB from a low-frequency signal amplifier circuit. RF characterization of the GFETs yields an ${f}_{T}\times {L}_{g}$ product of 2.64 GHz $\cdot ~\mu \text{m}$ and an ${f}_{{\textsf {Max}}}\times {L}_{g}$ product of 5.88 GHz $\cdot ~\mu \text{m}$. This paper presents for the first time THz-TDS usage in combination with other characterization methods for device performance assessment on BN/G/BN stacks. The results serve as a step toward scalable, all CVD 2-D material-based FETs for CMOS compatible future nanoelectronic circuit architectures. [ABSTRACT FROM AUTHOR]

This paper reports ultralow contact resistivities ( \rho c) achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; \rho c achieved was \sim 2.9\times 10^-9~\Omega \cdot cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; \rho c achieved was \sim 1.7\times 10^-9~\Omega \cdot cm2. When \rho c reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates. [ABSTRACT FROM PUBLISHER]

We demonstrate InGaAs quantum-well (QW) MOSFET arrays with Mo contact lengths between 40 and 800 nm fabricated by a self-aligned process. A gate pitch of 150 nm is realized, which is the smallest at present for any type of InGaAs FET structure. Fabricated gated MOSFET arrays and gate-less arrays are used to study the properties of nanoscale ohmic contacts in InGaAs MOSFETs with different contact lengths. A three-layer resistive-network model is developed to analyze the contact electrical characteristics. From this paper, we extract a contact resistivity from Mo to n+ InGaAs of 8 \times 10^\mathrm -9~\Omega \cdot \mathrm cm^2 , and from n+ InGaAs to the QW channel of 2\times 10^\mathrm -8~\Omega \cdot \text cm^2 . When benchmarked with other ohmic contact technologies for n-type InGaAs MOSFETs, our refractory metal contact approach represents the lowest film resistivity and is among the lowest contact resistivity that has been demonstrated. The contact model developed here infers a contact resistance from the Mo contact to the channel of 260 \Omega \cdot \mu \textm for a contact length of Lc=10 nm. This suggests that further research on low-resistance ohmic contacts is required before InGaAs MOSFETs can deliver the required performance. [ABSTRACT FROM PUBLISHER]

In this paper, a microfluidic device is introduced based on direct current (dc) dielectrophoresis for the separation of circulating tumor cells from normal blood cells. Differential sidewall electrodes are designed inside the channel and two middle-channel outlets are located after the end of the electrodes, which are assigned to collect the normal blood cells. A maximum dc potential of 3 V is applied to the electrodes, resulting in a differential dielectrophoretic forces acting on the cells. This paper involves isolating MCF-7 breast cancer cells from white blood cells (WBCs) and red blood cells (RBCs), eliminating the demand for primary RBC lysis. Numerical simulation results revealed that the differential electrodes not only suppressed successfully the need for high applied voltages by dc dielectrophoresis but also diminished the joule heating effects. Besides that, the arrangement of the differential electrodes was observed to play a critical role in the separation performance. In particular, designing the outlets, as well as adjusting the electrode potentials, has effectively assisted the device to be tunable for different cancer cells even with different radii. More strikingly, the ability of the device to deflect the waste cells (WBCs and RBCs) to out of the microchannel prior to the cancer cells was proven to positively affect the separation efficiency and purity. The proposed device was capable of separating different cells leveraging various diameters with capture purity and efficiency of higher than 83% and 100%, respectively. [ABSTRACT FROM AUTHOR]

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are a suitable replacement for metals commonly used as a fill material for through substrate vias (TSVs). The electrical and thermal contact resistance, however, between the CNT TSVs and the horizontal metal interconnects (typically copper) can limit the use of CNT technology. A replacement for the horizontal metal interconnects in the form of graphite material is proposed in this paper. Electrical and thermal models of the interface between CNT TSVs and graphite interconnect are compared to the interface between CNT TSVs and copper interconnect. The proposed models include electrical and thermal crowding effects as well as the skin effect. The CNT/graphite interface exhibits up to 72.6% and 71.9%, respectively, lower electrical and thermal resistance as compared to the CNT/copper interface. [ABSTRACT FROM AUTHOR]

This paper proposes a La/ultrathin TiSix metallic bilayer contact (MBC) on moderately doped n+-Si, which can simultaneously reduce contact resistivity ( $\rho _{c}$ ) and at the same time improve the contact thermal endurance. In such an MBC, the top La defines the work function (WF), whereas the ultrathin (~1 nm) TiSix (WF-transparent) interlayer acts as a Si-diffusion barrier and improves the thermal endurance of the whole contact. Moreover, incorporation of oxygen (O) into MBC further improves the contact performance. On n+-Si with a donor concentration of $\textsf {1} \times \textsf {10}^{\textsf {19}}$ cm−3, an O-incorporated MBC can achieve an $18.3\times $ and $2.2\times $ reduction in $\rho _{c}$ as compared with Ti/n+-Si and La/n+-Si references, respectively. [ABSTRACT FROM AUTHOR]

Due to high surface-to-volume ratio, surface traps play crucial role in electronic properties of semiconductor nanowires and nanowire-based devices. Recently, it was experimentally demonstrated that surface traps even can induce conductivity type inversion in semiconductor nanowires. Here, we have performed theoretical and numerical analyses to investigate the influence of surface traps on semiconductor nanowire conductivity including possible inversion due to surface traps. The Poisson equation with consideration of both type of mobile charges and ionized donors was solved having surface trapped charges in Neumann boundary conditions. Different semiconductor materials and surface trap densities have been considered. Calculations were done considering single energy level of surface traps and then the results were generalized to exponential energetic distribution of surface states density. The effect of surface traps was analyzed both for low-doped and highly doped nanowires. It was shown that for moderate or lightly doped NWs, the conductivity type switching from n- to p-type can occur at small radii. The developed potential-based analytical model allows calculating the inversion charge raised due to surface traps. The accuracy of analytical calculations has been validated with TCAD simulations and qualitatively compared with published experimental data. This paper is useful for design optimization of nanowire-based photodetectors, sensors, and reconfigurable FETs. [ABSTRACT FROM AUTHOR]

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (D'S) of SiO2/Al2O3 insulator. Devices with contact area of 500 × 20 nm and lengths of 2 μm show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the D'S enables a 60% reduction in reset energy compared with SiO2-isolated devices. [ABSTRACT FROM PUBLISHER]

With the increasing demand of high-power light-emitting diode (LED), multichip modules have made great progress. A die-attach layer as the first-level packaging has a most significant impact on the thermal performance of a power module. In this paper, we introduce a novel die-attach material, nanosilver paste, which can be used for connecting multichips on the substrate. This nanosilver paste has a higher melting temperature and thermal/electrical conductivity than the conventional Sn3Ag0.5Cu solders and silver epoxy films. In addition, Al2O3 ceramic substrates were used to form a high-power LED chip-on-board architecture because of their high thermal conductivity and low coefficient of thermal expansion. Recently, because of their ability to emit high brightness, LED packages are being exploited for the automotive, aircraft, space exploration, nuclear industries, and in most cases are exposed to harsh environments. Therefore, the performance and stability of LED packages will be the key to assuring the reliability of LED modules. In this paper, the properties of the LED modules bonded separately with nanosilver, Sn3Ag0.5Cu, and silver epoxy and operating under various ambient temperatures from 27 °C to 100 °C were determined. The test results showed that the nanosilver paste is a very promising die-attach material for high-power multichip modules packaging. [ABSTRACT FROM PUBLISHER]

In this paper, for the first time, we study the impact of self-heating on the statistical variability of bulk and Silicon-on-insulator FinFETs designed to meet the requirements of the 14/16-nm technology node. The simulations are performed using the Gold Standard Simulations atomistic simulator GARAND using an enhanced electrothermal model that considers the impact of the fin geometry on the thermal conductivity. In the simulations, we have compared the statistical variability obtained from full-scale electrothermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electrothermal simulations. The combined effects of line edge roughness and metal gate granularity are considered. The distributions and the correlations between key figures of merit, including the threshold voltage, ON-current, subthreshold slope, and leakage current are presented and analyzed. [ABSTRACT FROM PUBLISHER]

This paper provides engineering models of a simple and robust approach for creating electrical connections to silicon using reduced temperature (<200 °C substrate) soldering. This removes a significant hurdle to the fabrication of high performance, custom silicon piezoresistors. The approach focuses on reducing the resistance of diodes that are undergoing reverse bias behavior, commonly considered to be unacceptable for electrical connections. Reverse bias Schottky barrier analytical models based on quantum mechanical first principles are developed to explain how the behavior is affected by doping, soldering temperature, and geometry. This understanding is encapsulated within parametric models that enable rapid design and optimization of the electrical contacts to silicon. Using this model, one may design contacts for practical applications that do not require the conventional microfabrication processing or the high-temperature processing. Indium solder is found to be the best solder for this process, with ohmic contact resistances of \approx 1\Omega -cm ^{2} for \langle 110\rangle p-type wafers at 10^17 cm ^-3 doping. [ABSTRACT FROM AUTHOR]

We have evaluated the density of interface trap states (${D}_{\textsf {it}}$) at the surface of a GaN/AlGaN/GaN heterojunction by the previously described gated van der Pauw experiments, as well as by a UV-assisted gated van der Pauw method, described in this paper. The obtained ${D}_{\textsf {it}}$ values are about two orders of magnitude lower than the assumed by the surface-donor theory and three orders of magnitude lower than the required to compensate the polarization surface charge in GaN. Previous experimental studies using a variety of other techniques reported similarly low ${D}_{\textsf {it}}$ values. We, hence, conclude that the variable midgap surface charge is not responsible for the formation of the 2-D electron gas, and cannot compensate for the large surface polarization charge in GaN. A yet unexplained polarization self-compensating (PSC) surface charge must be invoked to account for experiments. A few comments about the physical nature of the proposed PSC charge are provided. [ABSTRACT FROM AUTHOR]

In this paper, self-heating effects (SHEs) in three-stacked nanoplate FETs were investigated through the TCAD simulation. In order to obtain high reliability, the evaluation of SHEs was performed after ${I}_{D}$ – ${V}_{G}$ curve fitting based on the experimental data. First, general analysis on SHEs was conducted to confirm the influence of SHEs to electrical characteristics. The optimized nanoplate width for great electrical properties was proposed by using the figure-of-merit factor under the consideration of SHEs. In addition, difference of heat flux between FinFET and stacked nanoplate FET was analyzed. Based on the analysis, the two-step thermal resistance (${R}_{\text {th}}$) model depending on drain voltage was proposed. The two-step ${R}_{\text {th}}$ model in the stacked nanoplate FET matched well with the Berkeley short-channel IGFET model—common multigate model compared the other ${R}_{\text {th}}$ models. A seven-stage ring oscillator with the proposed ${R}_{\text {th}}$ model was demonstrated, and SHEs in the circuit level were confirmed. [ABSTRACT FROM AUTHOR]

In this paper, we report a hierarchical simulation study of the electromigration (EM) problem in Cu-carbon nanotube (CNT) composite interconnects. This paper is based on the investigation of the activation energy and self-heating temperature using a multiscale electrothermal simulation framework. We first investigate the electrical and thermal properties of Cu-CNT composites, including contact resistances, using the density functional theory and reactive force field approaches, respectively. The corresponding results are employed in macroscopic electrothermal simulations taking into account the self-heating phenomenon. Our simulations show that although Cu atoms have similar activation energies in both bulk Cu and Cu-CNT composites, Cu-CNT composite interconnects are more resistant to EM thanks to the large Lorenz number of the CNTs. Moreover, we found that a large and homogenous conductivity along the transport direction in interconnects is one of the most important design rules to minimize the EM. [ABSTRACT FROM AUTHOR]

The current filament phenomena in high gain gallium arsenide (GaAs) photoconductive semiconductor switches (PCSS) always draw a significant influence on the lifetime of the devices. This paper presents a study on the influence of the current filament over the material properties and output characteristics of the GaAs PCSS. The working principle of the current filaments has been analyzed and it is shown that the performance of GaAs PCSS degrades due to the heating effects of the current filaments. It is observed that the heating effect of current filament reduces the dark resistivity of the GaAs material; furthermore, it gradually damages electrode of PCSS, leading to the breakdown of PCSS. This paper presents the relationship between the turn-ON process and damage of the PCSS. [ABSTRACT FROM AUTHOR]

In this paper, the effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal–semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (${I}_{ \mathrm{OFF}}$) and extremely low on-state current (${I}_{ \mathrm{ON}}$). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, ${I}_{ \mathrm{OFF}}$ of $9.42 \times 10^{-10}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{ON}}$ of $6.09 \times 10^{{-4}}$ A/ $\mu \text{m}$ , and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node. [ABSTRACT FROM AUTHOR]

Selector-less resistive random-access memory (RRAM) devices require high nonlinearity (NL) in low-resistance state current ( ${I}_{\textsf {LRS}}$ ). In this paper, we investigate the effect of composition (here, Ca%)-dependent material properties, viz., ion migration barrier, and thermal conductivity, on memory performance of recently demonstrated Pr1–xCaxMnO3-based selector-less RRAM with high NL. First, the NL increases as “ $\mathit {x}$ ” decreases. This is attributed to higher self-heating in $\textsf {PCMO}{(}\mathit {x}{)}$ films as composition-dependent thermal conductivity ( $\kappa $ ) decreases as “ $\mathit {x}$ ” is decreased. This enables selector-less operation. Second, larger memory window is observed as “ $\mathit {x}$ ” increases due to decrease in the voltage required for onset of RESET process (i.e., $V_{\textsf {MIN, RESET}}$ ) as “ $\mathit {x}$ ” is increased. Lower $V_{\textsf {MIN, RESET}}$ at higher “ $\mathit {x}$ ” is due to higher oxygen-ion conductivity attributed to lower migration barrier ( ${E}_{m}$ ). Third, retention is measured at different temperatures to extract composition-dependent ${E}_{m}$. The poor memory retention performance for $\mathit {x}= 1$ is consistent with lower ${E}_{m}$ estimated. Finally, enhanced endurance is observed for lower ${E}_{m}$ due to low-energy requirement for switching. Based on these observations, an interrelation between ${E}_{m}$ , retention, and endurance is established. Therefore, an interplay of composition-dependent thermal conductivity and oxygen-ion migration barrier enables tunable memory characteristics in Pr1–xCaxMnO3-based RRAM. [ABSTRACT FROM AUTHOR]

A novel composite device structure named self-adjust conductivity modulation lateral insulated gate bipolar transistor (SCM-LIGBT), including normal LIGBT region (NLT region), the EM-nMOS region (ENM region), and the series diode region (DIO region), is proposed in this paper. By adding the enhanced-mode nMOS region and the series diodes region, the parasitic NPN transistor (NPN) bipolar structure in the normal LIGBT structure can be triggered in on-state and the conductivity modulation is dramatically enhanced, which leads to the improvement on the current capability and the forward voltage. In addition, due to the base voltage of the parasitic NPN bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe operating area. Numerous simulations and measurements are presented to investigate the electrical characteristics of the proposed structure. The length of the fabrication SCM-LIGBT is 78.5~\mu \textm , and the width of the DIO and NLT is 830 \mu \textm , while the width of the ENM is 4100~\mu \textm . The results demonstrate that the proposed SCM-LIGBT achieves a high-current capability ( JA) of 2428 A/cm2 at VG= 10 V, a low on-state voltage drop of 1.15 V at JA= 150 A/cm2 with its breakdown voltage of 590 V. [ABSTRACT FROM PUBLISHER]

In this paper, we intensively investigated the proposed nanocontact phase-change memory (nano-C PCM) with incorporated nanostructures and high-resistivity nanolayer (nano-L) for reducing reset current. The high resistivity was able to be tuned by doping N into the conventional Ge2Sb2Te5 phase-change material. The analysis based on finite-element method exhibited that the current density in the nano-C PCM could be locally enhanced to about two times that of both conventional and nano-L PCM devices. This resulted in the localization of Joule heating in the nano-C PCM, making it have the highest temperature at the same programming current among the three types of PCM devices. Reset current of nano-C PCM could be greatly reduced to 8.2% of that of the conventional one, owing to its high-efficiency heating for amorphization. [ABSTRACT FROM PUBLISHER]

Dimensional scaling of interconnects at future technology generations presents major limitations to the improvement of the performances of integrated circuits. In this paper, we investigate the impact of highly scaled Cu/low- $\kappa $ interconnects on the speed and power dissipation of multiple circuit blocks based on timing-closed full-chip Graphic Database System II (GDSII)-level layouts with detailed routing. First, we build multiple standard cell libraries for 45-, 22-, 11-, and 7-nm technology nodes and model their timing/power characteristics. Next, we pair these standard cell libraries with various interconnect files and build GDSII-level layouts for multiple benchmark circuits to study the sensitivity of the circuit performance and power dissipation to multiple interconnect technology parameters such as resistivity, barrier/liner thickness, and via resistance. We investigate the implications of slowing down interconnect dimensional scaling below 11-nm technology node. [ABSTRACT FROM AUTHOR]

To allow for novel memory and computing schemes based on the resistive switching memory (RRAM), physically based compact models are needed. This paper presents a new analytical model for HfO2-based RRAM, relying on a simplified description of the conductive filament (CF) in terms of its diameter and gap length. The set and reset operations are described by CF growth and gap opening, respectively, activated by the local field and temperature. The analytical model is then used to describe the switching dynamics in the complementary resistive switch (CRS), consisting of an antiserial connection of two resistive devices. The impact of the gap resistivity on the CRS characteristics is discussed, highlighting the tradeoff between off-state leakage and set/reset window. [ABSTRACT FROM AUTHOR]

A high density symmetric inductor using a novel combination of solenoidal wound series stacked spirals is proposed in this paper. Series stacking in the individual sections increases overall inductance density, while solenoidal winding pushes the quality factors (Q) to higher frequencies. The proposed inductor achieves more than 65% improvement in peak-Q value and 100% higher peak-Q frequency and self resonance frequency, while occupying 20% lesser area when compared with a standard symmetric inductor with crossovers. Implemented in a high resistivity 0.18 \(\mu \) m CMOS silicon-on-insulator process with dual-thick metal stack, the proposed inductor achieves 70-nH inductance and a Q of 11.3 operating at 1.6 GHz within \(250\times 250\) \(\mu \) m \(^2\) area. This translates to a record figure-of-merit of 12.2, which is highest in air core symmetric inductor literature. Further, the proposed inductor configuration is extended to realize a planar transformer with very high turns ratio of 9.25 using only two metals. [ABSTRACT FROM AUTHOR]

In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge2Sb2Te5 . A novel procedure, named R–SET technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R–SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R–SET pulse based on a time reference scheme is proposed and discussed. [ABSTRACT FROM PUBLISHER]

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step. [ABSTRACT FROM PUBLISHER]

This paper presents the optimization of a bismuth tellurium (Bi1.8Te3.2)–antimony tellurium (Sb2Te3)-based thermoelectric generator (TEG) fabricated by screen-printing technology on flexible polyimide (Kapton) and textile substrates. New formulations of screen printable thermoelectric pastes are presented with optimized composition, curing conditions, and printing parameters. The modifications of the thermoelectric materials enable them to be successfully deposited on flexible textile substrates. The optimized values of resistivity of the BiTe and SbTe thick films on Kapton were 9.97 \times 10^-3 and 3.57 \times 10^-3 ~\Omega \cdot \text cm , respectively. The measured figure of merit at room temperature was 0.135 and 0.095 for BiTe and SbTe thick films on Kapton, respectively. The dimension of each printed thermoleg was 20~\text mm \times 2~\text mm \times 70.5~\mu \textm . For the TEG on Kapton, the printed assembly comprising eight thermocouples was coiled up and generated a voltage of 26.6 mV and a maximum power output of 455.4 nW at a temperature difference of 20 °C. For a printed TEG on textile, the maximum power output reached 2 \mu \textW from the same temperature difference. [ABSTRACT FROM PUBLISHER]

Aiming at overcoming the Fermi-level pinning (FLP) occurring at the metal/semiconductor interfaces, metal/insulator/semiconductor (MIS) contacts to n-Si and p-Si are usually treated in separate optimization studies, yet with no particular insight on their technological compatibility. In this paper, using 1-D analytical modeling of MIS contacts, it is shown that in order to fully benefit from FLP mitigation on both n- and p-type Si, a single-insertion/single-metallization scheme cannot be considered. In addition, it is demonstrated that associating given numerical values of contact resistivity with MIS contacts results in a thorny problem, since their I–V characteristics are nonsymmetric nonlinear. [ABSTRACT FROM AUTHOR]

The physical mechanisms that regulate carrier transport in polycrystalline chalcogenides, such as \Ge2\Sb2\Te5 (GST), are still debated. Recently, self-induced Joule-heating (SJH) effect has been claimed to be the key factor in explaining the nonlinearity of the I–V characteristics of polycrystalline GST-based phase-change memory (PCM). In this paper, we carefully investigate the SJH occurring in the GST material by analyzing the I–V characteristics of PCM cells at low voltages, i.e., in the memory-cell readout region. To accomplish the study, we use ad hoc fabricated PCM devices allowing an easier evaluation of SJH occurring in the chalcogenide layer. A novel procedure to test the SJH effect is also proposed. A comparison between numerical simulations and compact modeling is discussed as well. Our paper shows that the SJH effect is not sufficient to reproduce the experimental I–V nonlinearity, claiming for new experiments and theoretical investigations. Therefore, this paper can be considered a step forward toward the comprehension of the transport properties of polycrystalline GST, which is a key aspect for robust modeling of PCM devices. [ABSTRACT FROM PUBLISHER]

In this paper, metallic thermoelectric generators were studied and fabricated using copper (Cu) and cobalt (Co) as their respective positive and negative thermoelements. Thus, the chosen Cu-clad polyimide substrate alleviated the deposition of Cu and eased the microfabrication. A lateral device structure might assist in generating larger output power through its longer thermoleg length. Hence, the fabricated thick-film devices had planar and lateral structures with lateral heat flow and lateral thermopile layout. The strong correlations of electrical and thermal conductivities in metal thermoelements have resulted in lower Seebeck coefficient along with reduced thermoelectric power-generating performances. Alternatively, a thermoleg cross-sectional area (${A}$) optimization approach may optimize these disrupting correlations and improve their power-generating effectiveness, whereas a sandwiched planar structure can allow more thermopiles to be integrated without influencing the generator’s size. Both A optimization and sandwiched planar structure have rarely been applied and studied in the past works and have never been implemented using metal thermoelements. Hereafter, a Cu–Co device was enhanced through ${A}$ optimization by increasing the thickness of Co over 3.86 times the Cu thickness, and the implementations of a sandwiched planar structure. Herein, a flexible sandwiched planar thermoelectric generator was fabricated for the first time, using simpler microfabrication. This enhanced Cu–Co generator achieved a thermoelectric efficiency factor of ${6.6} \times {10}^{-{3}}\,\,\mu $ Wcm−2K−2($12.89~\mu $ Wcm−2) at a temperature difference of 44.2 K. It remarked 3.1 times of improvement (by stacking three sets of thermopile) than its similar single Cu–Co thermopile of ten thermocouples. [ABSTRACT FROM AUTHOR]

In this paper, we investigate, by combining electrical measurements with an atomistic-to-circuit modeling approach, the conductance of doped standalone multiwall carbon nanotubes (CNTs) as a viable candidate for the next generation of back-end-of-line interconnects. Ab initio simulations predict a doping-related shift of the Fermi level, which reduces shell chirality variability and improves electrical resistivity up to 90% by converting semiconducting shells to metallic. Electrical measurements of Pt-salt-doped CNTs provide up to 50% of resistance reduction, which is a milestone result for future CNT interconnect technology. Moreover, we find that defects and contacts introduce additional resistance, which limits the efficiency of doping, and are the primary cause for the mismatch between theoretical predictions and experimental measurements on doped CNTs. [ABSTRACT FROM AUTHOR]

In this paper, RF sputtered magnesium oxide (MgO) thin films (225 nm) on Aluminum (Al6061) grade and Copper substrates were used as thermal interface materials for high-power LED. X-ray diffraction spectra showed the presence of polycrystalline MgO with (200) and (220) oriented cubic MgO (c-MgO) phase as preferred. Thermal conductivity measurement showed an improvement from 17.26 to 22.63 W/mK for Al6061 substrates and from 15.04 to 20.18 W/mK for Cu substrates, respectively. An impressive decrease in junction temperature (${T}_{j}$) was recorded for MgO thin films interfaced LED on both substrates, especially 2 h annealed MgO on Cu and Al6061 showed a noticeable difference in junction temperatures ${\Delta } {T}_{j}$ of 32.91 °C and 23.08 °C, respectively. Consequently, the difference in total thermal resistance ($\Delta {R}_{\textit {th-tot}}$) of 5.15 and 3.69 K/W were recorded for MgO film coated Cu and Al6061 substrates, respectively, when compared to their values of bare substrates measured at 700 mA. From surface analysis by atomic force microscope, smooth surfaces for annealed MgO thin films were evidenced when compared to the unannealed films and bare substrates, which was making the LED package with low junction temperature and thermal resistance. Overall, MgO thin film synthesized over Cu substrates showed good performance on reducing ${T}_{j}$ and ${R}_{\textsf {th}}$ of LED at higher driving currents when compared to that of LED on MgO coated Al6061 substrates. [ABSTRACT FROM AUTHOR]

In this paper, we have devised on shallow trench isolation (STI) design considering leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ tendency is considered in terms of the interface trap density (${D}_{\textsf {it}}$) difference depending on the STI material type and STI thickness. In the case of Bulk FinFET, the STI design for each of high performance (HP) and low power (LP) is presented. On the other hand, in the case of SOI FinFET and VFET, STI designs which do not distinguish HP/LP are presented. Max lattice temperature (${T}_{\textsf {L,max}}$)/thermal resistance (${R}_{\textsf {th}}$)/on current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) degradation rate according to STI design in each structure are also analyzed. Finally, we compare the hot carrier injection (HCI)/bias temperature instability (BTI) lifetime as a function of the device temperature which is varied depending on STI design. In conclusion, our proposed STI design effectively reduces the self-heating effect in each structure and increases the HCI/BTI lifetime accordingly. [ABSTRACT FROM AUTHOR]

This paper provides the first detailed insights into the ultrahigh-frequency behavior of graphene ribbons (GRs) and analyzes their consequences in designing interconnects and low-loss on-chip inductors. In the companion paper (part I), an accurate impedance modeling methodology has been developed based on the Boltzmann equation with the magnetic vector potential Green's function approach incorporating the dependency of current on the nonlocal electric field. Based on the developed methodology, this paper for the first time embarks on the rigorous investigation of the intricate processes occurring at high frequencies in GRs, such as anomalous skin effect (ASE), high-frequency resistance and inductance saturation, intercoupled relation between edge specularity and ASE, and the influence of the linear dimensions on impedance. A comparative study of the high-frequency response of GRs with that of carbon nanotubes (CNTs) and Cu is made to highlight the potential of GR interconnects for high-frequency applications. Subsequently, the high-frequency performance of GR inductors is analyzed, and it is shown that they can achieve 32% and 50% improvements in maximum Q-factor compared to Cu and single-walled CNT inductors with 1/3 metallic fraction, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a simulation-based assessment of the design, characteristics, and feasibility of a lateral SiGe heterojunction bipolar transistor with a graded base on a silicon on insulator. A device was created with a focus on integration with the CMOS process, THz ${f}_{T}/f_{\max}$ , and low-power dissipation. These characteristics are achieved with an ultrathin base width of 22 nm, grading of the base, and modification of standard doping profiles. In TCAD simulations, the n-p-n device has a unity gain cutoff frequency (${f}_{T}$) of 1.2 THz and maximum oscillation frequency (${f}_{\max}$) of 2 THz. The p-n-p of the same design has ${f}_{T}$ of 900 GHz and ${f}_{\max}$ of 1.8 THz. Additional Monte Carlo plots that show electron velocity and carrier densities across the length of the device, and a discussion on ballistic effects in the proposed devices are presented. To demonstrate the feasibility of the device, a possible process flow for fabrication is also summarized. [ABSTRACT FROM AUTHOR]

In this paper, the impact of different Ge preamorphization implantation (PAI) conditions on the formation of ultrathin TiSix as well as on the specific contact resistivity ($\rho _{c}$) in TiSix/n-Si contacts was investigated systematically. Extensive material characterizations, such as cross-sectional transmission electron microscopy, X-ray diffraction, and angle-resolved X-ray photoelectron spectroscopy, as well as electrical characterizations such $\rho _{c}$ values, Schottky barrier height (SBH), and leakage current of p-n junctions, were performed. It is found that Ge PAI indeed promotes Ti silicidation at 550 °C and the resultant ${t}_{\text {TiSix}}$ values are strongly dependent on the thickness of amorphous Si (${t}_{\boldsymbol {\alpha -{\mathrm{ Si}}}}$) created by Ge PAI. The stoichiometry of TiSix films is rather graded than constant from the TiN/Ti side to Si side. Proper Ge PAI is beneficial in reducing the $\rho _{c}$ values in TiSix/n-Si contacts, and this reduction in $\rho _{c}$ cannot attribute to the reduction of SBH. Though proper Ge PAI leads to reduced $\rho _{c}$ values, the leakage current of p-n diodes is increased as a penalty which needs to be compromised in practical applications. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) have shown attractive device performance making them a potential candidate to replace MOSFETs in future technologies. However, the inherent ambipolar characteristic of TFETs poses challenge in digital applications. The gate–drain overlap in conventional TFETs efficiently suppresses the ambipolar conductivity. On the other hand, in dopingless TFETs (DLTFETs), due to the requirement of separate gate and drain electrodes for electrostatically creating doped and intrinsic regions, gate–drain overlap cannot be realized. However, gate–drain overlap can be effectively realized using oversized back gate (OBG). Therefore, in this paper, we have proposed a DLTFET with an OBG that effectively suppresses ambipolar behavior even upto gate voltage ${V}_{\textsf {GS}} = -\textsf {1}$ V. Misalignment study is also performed for the gate length ${L}_{G} = \textsf {20}$ nm which has been reported to degrade the tunneling phenomenon at gate–source interface. It is observed that the proposed device is more tolerant to misalignment due to its OBG. The OBG also provides improvement in ${I}_{\textsf {on}}$ ($\sim 1.4\times $) due to enhanced band bending at gate–source interface. To demonstrate the advantage of proposed device architecture over existing architectures, we compare the performance of proposed device with other existing techniques such as dual material gate and dual material drain architectures. The OBG-DLTFET has shown better ambipolar and on-state characteristics in comparison to the existing techniques. [ABSTRACT FROM AUTHOR]

This paper proposes a new concept of Schottky contact insulated-gate bipolar transistor (SC-IGBT), which uses a top surface Schottky contact to the p-base as a hole barrier to enhance the conductivity modulation effect. TCAD simulation shows that the SC-IGBT offers a saturation voltage decrease of 19% or turn-OFF loss reduction of 46% when compared with a conventional field-stop IGBT. Furthermore, it potentially offers an alternative method of fabricating injection enhancement IGBTs, which is simpler than the existing buried n-type layer or narrow mesa trench structures. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the RF properties of Cu nanolines that are arranged in a coplanar waveguide (CPW) configuration. The signal tracks for the CPW transmission lines (CPW TLines) were either single Cu nanolines or multiple parallel Cu nanolines of equal total width and varying number. The total width was kept constant in order to study the validity of the litz-wire concept on the on-chip integrated CPW TLines. The metallization thickness was 100 nm and their width ranged from 50 nm to 1 \mu \textm . The RF characteristics of the nanolines were measured in the frequency range 40 MHz–40 GHz and the results were compared with those obtained from electromagnetic simulations. For these frequencies and nanolines dimensions, no improvement was observed when splitting the single line into multiple parallel lines. On the contrary, the resistance was increased according to the corresponding resistivity increase. [ABSTRACT FROM AUTHOR]

This paper presents an enhanced, closed-form expression for the thermal resistance, and thus, the channel temperature of AlGaN/gallium nitride (GaN) HEMTs, including the effect of the temperature-dependent thermal conductivity of GaN and SiC or Si substrates. In addition, the expression accounts for temperature increase across the die-attach. The model’s validity is verified by comparing it with experimental observations. The model results also compare favorably with those from finite-element numerical simulations across the various device geometric and material parameters. The model provides a more accurate channel temperature than that from a constant thermal conductivity assumption; this is particularly significant for GaN/Si HEMTs where the temperature rise is higher than in GaN/SiC. The model is especially useful for device and monolithic microwave integrated circuit designers in the thermal assessment of their device design iterations against required performance for their specific applications. [ABSTRACT FROM PUBLISHER]

This paper presents a statistical simulation study of contact resistivity ($\rho _{c}$) variability (CRV) of TiN and TaN metal–semiconductor (MS) and metal–interfacial layer–semiconductor (MIS) n-Ge(Si) source/drain (S/D) contacts resulting from variation in contact metal work function ($\phi _{m}$) due to its different grain orientations, and its impact on FinFET performance at 7-nm node using 3-D TCAD simulations. Fermi-level unpinning enables MIS contacts to exhibit lower $\rho _{c}$ than MS contacts but increases their sensitivity to $\phi _{m}$ variation leading to higher CRV. CRV is shown to get worse with device scaling, especially for MIS contacts. However, increasing S/D doping, reducing grain size, and doping the interfacial layer (for MIS contacts) demonstrate reduction in CRV. At high S/D dopings, TiN MS contacts on Ge as well as Si meet International Technology Roadmap for Semiconductors requirements with nearly the same $\rho _{c}$ as MIS contacts but with significantly lower CRV. [ABSTRACT FROM AUTHOR]

The thermal simulation using ANSYS was carried out for estimating the maximum temperature and the temperature distribution in a high-average power broadband helix traveling-wave tube (TWT). The simulation was first carried out independently for the subassemblies such as the slow-wave structure, the output coupler, and the depressed collector; and the combined effect on the overall temperature inside the TWT was estimated subsequently. The simulation was carried out using several options of thermal interface resistances such as 100% contact and 50% contact, apart from considering various structural configurations, and an optimal thermal management solution was evolved for the device under consideration. [ABSTRACT FROM AUTHOR]

A simple structure of planar silicon nanowire (SiNW)-based thermoelectric (TE) generators (TEGs) is presented in this paper, which has the ability to sustain temperature difference along SiNW under ultrashort channel length for achieving mW/cm2-class power output from environmental heat energy. The TE performance of the proposed SiNW-based TEGs was evaluated by finite-element simulation and analytic modeling. The channel length, pad length, and the thickness of the SiO2 layer were varied in the model while keeping a series of constant proportions toward finding the optimal SiNW-based TEG structure for high power generation. Based on the analysis, we demonstrated that decreasing the dimension of SiNW-based TEG is beneficial to improving the total TE power density. A very high power density of 4.2 mW/cm2 is possible to be achieved at SiNW length of $0.1~\mu \text{m}$ and pad length of $0.1~\mu \text{m}$ under a temperature difference of 5 K across the hot and cold regions. The miniaturized SiNW-based TEG has a great potential to obtain the output power density which is 100–1000 times higher than conventional planar TEGs with air cavity but has a simple structure and can easily be fabricated. [ABSTRACT FROM AUTHOR]

This paper focuses on the comparison of the RF performances of various advanced trap-rich (TR) silicon-on-insulator (SOI) and porous silicon (PSi) substrates. The PSi substrates are produced by electroporisification starting either from cheap standard resistivity ( $10~\Omega \cdot $ cm) silicon (PSi-S) or from the most widespread highly doped milliohm-centimeter Si wafers (PSi-M). Through small-signal RF measurements, it is shown that TR-enhanced high-resistivity silicon and both types of PSi are acceptable for RF applications, showing high effective resistivities and low RF substrate losses. What is more the substrate effective permittivity is decreased in the PSi substrates providing higher coupling isolation at high frequencies. Furthermore, large-signal harmonic distortion measurements reveal very strong linearity for both PSi substrates, with PSi-S achieving 50-dB improvement over the already highly linear TR substrate. Finally, RF characterization was carried out over temperature from 25 °C to 175 °C. While the performances of TR and PSi-M substrate rapidly deteriorate above 120 °C, the cost-effective PSi-S substrate maintains high performance all the way up to 175 °C, allowing it a wider range of potential applications. [ABSTRACT FROM AUTHOR]

Mott materials have been investigated since late 1950s for their remarkably abrupt insulator to metal transition (IMT) in response to changes in temperature, strain, or electrical stimulus. Interest in these materials has been revived by recent demonstration of nanosecond-scale switching along with reproducible and fully reversible transitions in VO2-based thin film devices. These phenomena make VO2-based Mott insulator devices technologically relevant for various applications, such as memory selectors, logic switches, and building blocks for neuromorphic computing. Several groups have provisionally attributed the IMT switching to Joule heating. However, an electrothermal device simulation framework that self-consistently reproduces IMT phase transition, and in addition, explaining a variety of electrical/optical phenomena associated with IMT is still lacking. In this paper, we develop a self-consistent electrothermal device simulation framework which captures these key experimental attributes of IMT using VO2 as a model material. This framework will enable predictive modeling as well as provide insight on switching mechanisms and design of novel Mott insulator devices. [ABSTRACT FROM AUTHOR]

The dc and RF circuit performance of memristor circuits, including transient behavior, is developed by considering current contributions arising from different conduction mechanisms, namely, filament-assisted and bulk tunneling currents and currents flowing through low and high conductivity filaments. The dc circuit model explains the observed I-V hysteresis and most importantly allows scaling and optimization. A transient circuit model of memristive system is developed, based upon the dynamics, incorporating underlying electrochemistry that suggests SET and RESET transitions for a 50-nm TiO2-based memristor take approximately 120 ps to stabilize. A faster READ/WRITE operation would require appropriate conditioning circuitry. RF analysis suggests for a maximum allowable frequency of 7.5 GHz beyond which memristors can no longer be used as RRAM. These values can be pushed to higher limits by increasing the device cross-sectional area or choosing lower permittivity materials. The developed model allows its incorporation in commercial circuit simulators. The derived model is validated by incorporating it in Chua's chaotic circuit. [ABSTRACT FROM PUBLISHER]

Although horizontally-aligned carbon nanotube (HACNT) interconnects are the most common scenarios that have been modeled and analyzed in theoretical research, fabrication of HACNT test structures has remained an enigma until now. Through addressing several fabrication challenges, this paper reports a novel process that enables fabrication of high-density, long (over hundred microns), and thick (up to micrometer) HACNT interconnects. Furthermore, horizontal CNT-based 2-D Manhattan structure is demonstrated by properly designing the catalyst and flattening process. These structures are crucial for building angled interconnects and on-chip passive devices. In addition, to address the contact issue between metal and thick HACNT bundles, a multistep lithography combined with specifically designed metal deposition technique is performed to ensure full contact configuration. Using such a process, test structures with arrays of various sizes of HACNT bundle interconnects are fabricated. The process developed in this paper provides an important platform for future research and technology development of CNT-based interconnects and passive elements. [ABSTRACT FROM AUTHOR]

Due to the enormous challenges of fabricating long horizontally aligned carbon nanotube (HACNT) bundle interconnects, there exists little research on characterization of long HACNT interconnects. In this paper, taking advantage of our unique HACNT fabrication process outlined in the companion paper, the electrical and self-heating characterization of long HACNT bundles are reported. Negative temperature coefficients of resistance for both per unit length resistance and metal-CNT contact resistance are confirmed from measurements. This first report on the electrical and thermal characterization fills the wide gap between CNT interconnect modeling efforts and corresponding experimental efforts by providing many important extracted parameters that are critical in various modeling and analyses. [ABSTRACT FROM AUTHOR]

High electric fields and temperatures in high-voltage ICs (HV-ICs) can induce charge transport phenomena in the encapsulation material leading to reliability test failures. In this paper, the resistivity of epoxy-based resins with insulating microfiller weight fraction exceeding 70% has been experimentally and theoretically investigated for the first time. Electrical conductivity has been measured at high temperature (150 °C) using both dielectric spectroscopy analysis on bulk samples and charge-spreading characterizations on a dedicated test chip with integrated charge sensors. The use of a charge sensor close to the internal HV metallization leads to results more pertinent with the active area of HV-ICs. Remarkably, both experiments show an unexpected increase and a significant variability of the electrical conductivity as the microfiller fraction is increased. The strong correlation between bulk and lateral experiments clearly indicates that those features should be attributed to the bulk material. Numerical simulations of diffusion phenomenon in mold structures with random arrangements of spherical microfillers demonstrate that the conductivity increase with filler content can be ascribed to the role of the epoxy/filler interfaces. [ABSTRACT FROM AUTHOR]