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Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

The understanding of failure behavior is one of the basic requirements for further development of nonvolatile resistive random access memory (RRAM) devices. In this paper, we show a detailed analysis of a temperature-dependent low-resistance state (LRS) retention failure behavior of RRAM based on TiOx/Al2O3 bilayer structure. The device is capable of showing good resistive switching properties with stable operating parameters. The LRS current conduction process is mostly dominated by the Fowler-Nordheim tunneling. Retention behavior has been studied with a wide range of temperatures from room temperature to 200 °C with different compliances. The experimental results of TiOx/Al2O3 bilayer resistive switching memory are further supported theoretically by the Meyer-Neldel rule, which is fit well to the retention failure time. [ABSTRACT FROM AUTHOR]

Partial bias schemes reduce the disturbance during the writing of crossbar arrays (CBAs). Detailed analysis of two partial bias schemes is presented in this paper: 1) 1/2 bias scheme for low-power operation and 2) 1/3 bias scheme for high-performance (i.e., high Vdd) operation. With partial bias schemes, a sneak leakage reversal phenomenon may occur due to line-resistance-induced voltage degradation, which provides a measure of voltage driving range along access lines. Voltage dividing effect of selector devices reduces disturbance in CBAs and leads to similar writing voltage margin in both bias schemes. Matching a proper partial bias scheme with the selector device choice optimizes the performance of CBAs. [ABSTRACT FROM AUTHOR]

The memristor, a promising candidate for synaptic interconnections in artificial neural network, has gained significant attention for application to neuromorphic systems. One common method is using two memristors as one synapse to represent the positive and negative weights. In this paper, the synaptic behavior of a Ag/AgInSbTe/Ta (AIST)-based memristor is experimentally demonstrated. In addition, a neural architecture using one AIST memristor as a synapse is proposed, where both the plus and minus weights of the neural synapses are realized in a single memristive array. Moreover, the memristor-based neural network is extended to a multilayer architecture, and modified memristor-based backpropagation learning rules are implemented on-chip to achieve pattern recognition. The effects of device variations and input noise on the performance of a memristor-based multilayer neural network (MNN) are also described. The proposed MNN is capable of pattern recognition with high success rates and exhibits several advantages, such as good accuracy, high robustness, and noise immunity. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive crossbar array model that incorporates line resistance and nonlinear device characteristics. The model can be solved using matrix algebra and is suitable for statistical analysis. The nonlinear device solution enables the assessment of crossbar arrays with diode or nonlinear select devices. The calculation based on this model shows that voltage and current degradation due to line resistance are not negligible even for small crossbar arrays, which constrains feasible array size. Diode and nonlinear select devices significantly improve the sensing margin of reading operation and the voltage window of writing operation. This model provides a quantitative tool for accurate analysis of crossbar arrays and the evaluation of memory select devices. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector–one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonnegligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed. [ABSTRACT FROM AUTHOR]

Introducing a threshold switching selector in a resistive random access memory (RRAM) is essential for implementing a crossbar array that accurately accelerates neuromorphic computations. But, at an expense, a read voltage (${V}_{\text {read}}$) to be used for inference tasks is inevitably boosted. Therefore, this brief shows the effect of the enlarged ${V}_{\text {read}}$ on the stability of conductance states of the RRAM relevant to the inference robustness. The multiple conductance states of the analog RRAM achieved by a SPICE simulation are stable under consecutive 106 cycles of nominal ${V}_{\text {read}}$. However, each state of the one selector and one RRAM begins to be disturbed at ~104 cycles due to the boosted ${V}_{\text {read}}$. More importantly, when a certain state exceeds to the next state due to the accumulated ${V}_{\text {read}}$ stress, a classification accuracy of the neural network is significantly degraded. We, thus, introduce a two-step read scheme that separates the roles of turning on the selector and reading the states. As the selector is turned on rapidly with an additional large pulse, the following ${V}_{\text {read}}$ can be lowered. As a result, the read disturbance is minimized, and the optimized two-step pulse scheme allows 106 MNIST images to be recognized with >95% accuracy in the neural network. [ABSTRACT FROM AUTHOR]

Switching voltage variation of a Cu atom switch (AS) is improved to \(\sigma =9.5\) % by adjusting the buffer oxidation state and electrode surface roughness. The complementary AS (CAS) connects two Cu lines at each edge and is composed of a dual-layered electrolyte of oxidized Ti buffer metal/polymer solid electrolyte. A sufficiently oxidized Ti buffer layer prevents both Cu oxidation and Ti diffusion during the fabrication processes, reducing the OFF-state leakage current and making the ON/OFF current ratio high. A dry cleaning process reduces the Cu electrode surface roughness, tightening the set voltage distribution and enabling the use of a low programming voltage, 1.8 V. A large-scale crossbar switch block consisting of CASs has been operated by the improved switches. [ABSTRACT FROM AUTHOR]

A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation. [ABSTRACT FROM AUTHOR]

In-memory computing based on memristor is a promising solution to accelerate on-chip deep neural networks. Concerning the nonideal factors of the device analog behaviors, binary neural network (BNN) with ±1 weight and 0/+1 neuron is an alternative route to better employ the binary memristors with high technical maturity. In this article, we demonstrate a select column scheme for the BNN inference accelerator. By incorporating the performance of a W/AlOx/Al2O3/Pt memristor, the BNN shows high robustness and achieves a high recognition accuracy of 98.31% on the MNIST data set. We further propose a bit error model to investigate the impact of device error on recognition accuracy. The effects of device variation and nonideal input are also considered. The results show that the accuracy keeps satisfying (more than 90%) even under a high invalid rate, high input swing (0.21 standard deviation), and 7% salt noise in binary input, respectively, whereas the device variation has a trivial effect on the network. [ABSTRACT FROM AUTHOR]

The transient response of a crossbar array is investigated with HSPICE circuit simulation. A crossbar array contains many parasitic elements. This brief focuses on the parasitic capacitances of the selector devices and resistors. The read access time is determined for various array sizes and parasitic capacitances. The results show that the read access time increases with the array size and parasitic capacitance, particularly the selector capacitance. The effect of selector capacitance is analyzed with a time-dependent, unit-cell voltage model and simulation. The simulation results reveal that the selector capacitance has a greater effect than the resistor capacitance on the read access time because of the large time constant. The effect of the selector capacitance on the read access time remains significant for larger values of the other parasitic capacitances. [ABSTRACT FROM AUTHOR]

We present an investigation on the role of temperature and electric field as driving forces in the initiation of the resistive switching processes. The impact of temperature in both on- and off-states is analyzed in detail, using an electrothermal numerical model formulation. dc and pulsed temperature-dependent data, collected on scaled crossbar test structure cells, serially connected with an on-chip control transistor, are used to extract material information and are furthermore analyzed in conjunction with model outputs. With these results, further discussion is presented, suggesting points of attention for scaled cell design in the below-10-nm realm. [ABSTRACT FROM AUTHOR]