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The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

Esaki diodes based on interband tunneling have the characteristics of negative differential resistance (NDR) and ultrafast transient time, which lead to broad applications including oscillators, multivalue memories, and terahertz detectors. In this paper, we present the first demonstration of Esaki diodes based on 2-D/3-D heterojunctions—more specifically, chemical vapor deposition MoS2 on degenerately doped silicon. As compared to traditional 3-D heterostructures, these 2-D/3-D heterostructures have the following advantages: dislocation-free 2-D crystals even when the lattices are mismatched, dangling bond-free surface, and capability for large-scale synthesis at low cost. In this paper, monolayer, bilayer, and trilayer MoS2 are synthesized directly on degenerated Si substrate, forming the ultraclean heterostructures without surface contamination from tape and resist. Based on these pristine heterostructures, we are able to observe prominent NDR effect at room temperature. This NDR effect is attributed to the degenerately p-type doping in silicon and the natural n-type doping in MoS2. We also found that the peak voltage corresponding to the local maximum tunneling current depends on the MoS2 thickness. While MoS2 is changing from the monolayer (0.7 nm) to bulk (9.5 nm), the peak voltage increases from 0.8 to 1.6 V. This phenomenon can be explained by the energy-level differences between the monolayer and bulk MoS2. This paper provides the experimental groundwork for the synthesis of transition metal dichalcogenides on degenerately doped Si substrates and opens up new and exciting opportunities for electronic applications of 2-D/3-D heterostructures. [ABSTRACT FROM AUTHOR]

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

The effects of gamma rays on two kinds of GaN high-electron-mobility transistors (HEMTs) have been investigated in this paper. We have identified a gate degradation using a combination of optical and electrical measurements. We have demonstrated that the channel current under the degradation position is outside of the gate’s control. This degradation prevents the gate from fully pinching off the channel, creating a current concentration region when applying a reverse gate voltage. An integrated analysis, including ${I}$ – ${V}$ characterization, the emission microscope (EMMI) technique, and temperature-dependent measurements, was applied to study its mechanism. It is attributed to an irradiation-induced degradation in the Schottky contact. [ABSTRACT FROM AUTHOR]

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing. [ABSTRACT FROM PUBLISHER]

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage (${V} _{\textsf {TH}}$) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance (${I}$ – ${R}$) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs. [ABSTRACT FROM AUTHOR]

This paper demonstrates that—for high-electric fields and drain current levels—the electroluminescence (EL) versus VGS curves of GaN-on-Si radio frequency HEMTs significantly deviate from the well-known bell-shape, due to the turn-on of a secondary EL process that has not been described so far in the literature. Based on the combined EL measurements, electrical characterization, and thermal analysis, we demonstrate that: 1) for moderate gate and drain voltages, the EL versus VGS curve has the characteristic bell shape, and light emission originates from hot electrons injected from the source; EL signal is stronger at the edges of the gate, due to the higher electric field; 2) at high drain/gate bias and temperature, a second process induces a monotonic increase in the EL versus VGS curve; in this case, the EL signal is stronger at the center of the gate, and the EL intensity is directly correlated with the gate leakage current. Based on the experimental evidence collected within this paper, the secondary luminescence process is ascribed to: 1) the injection of carriers from the gate metal to the channel; 2) the acceleration of these electrons by the high gate–drain field; and c) the subsequent radiative emission. [ABSTRACT FROM AUTHOR]

High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 °C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 °C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 °C are 0.79 and 1.01 LSB, respectively, while at 500 °C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 °C and 500 °C, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we explore the electrical characteristics of ring oscillator (RO) by optimizing fabrication inline windows of 16-nm high- \kappa /metal-gate bulk FinFET devices. Key process parameters are ranked according to ROs’ performance, including effective capacitance ( C_{\mathrm {eff}}) , effective resistance ( R_{\mathrm {eff}}) , and integrated circuit quiescent current (IDDQ). Process-dependence factors are then extracted and classified to reveal the actual root cause of each cluster. The findings of this paper indicate the dual gate spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant affect C\mathrm {eff} , R\mathrm {eff} , and IDDQ significantly, but the variation source of these parameters is the thickness of the dual gate spacer. Furthermore, impacts of the ON-state current ratio of N/P devices on delay and IDDQ of RO are examined by replacing dual spacers with single ones, the uniformity of implantation can be enhanced. Thus, the fluctuation of IDDQ is seven times reduced (from 252 to 37 nA) and RO characteristic can fit to designing target. [ABSTRACT FROM PUBLISHER]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

Light-emitting diode (LED) luminous flux and efficacy as a function of temperature and current is important to qualify and optimize the design of an LED system. In this paper, the extension of light output equation was used to estimate luminous flux and efficacy of low-power surface-mounted device LED. The photometric and thermal test reports of LED parameters at a certain range of injection current and ambient temperature were obtained by the combination of T3ster and TeraLED systems. The luminous flux and efficacy as a function of injection current and ambient temperature were predicted. The agreement between the experimental and theoretical results validates the extended equation used in this paper. The optimized operating conditions of LED under test are determined. [ABSTRACT FROM PUBLISHER]

In this paper, several experimental methods (electrical and optical) for channel temperature detection in AlGaN/GaN high-electron mobility transistors have been studied and experimentally benchmarked. This paper encompasses four electrical methods (two dc characterization methods, low-RF output conductance measurement, and gate-resistive sensing technique) and one optical method (micro-Raman spectroscopy), which have been frequently used to sense temperature in AlGaN/GaN transistors. The experiments are carried out on identical test structures on wafer-level conditions as well as on single dies mounted on printed circuit board for power densities up to 12 W/mm. Due to a large temperature distribution along the channel of the devices and due to the physics on which each method is based, it was shown that the differences between the measured temperatures using the different methods can be as high as 50%. Experimental results are discussed and compared with coupled TCAD and finite element modeling simulations, where significant agreements have been observed. [ABSTRACT FROM AUTHOR]

The tunable negative differential resistance (NDR) characteristics of metal-insulator-semiconductor- insulator-metal (MISIM) tunnel diodes (TDs) structure with thin oxide were observed by biasing the substrate simultaneously with one of the TDs under designed voltage drops (AV). An inner circular electrode TD surrounded by a ring-shape electrode TD gate pattern was adopted. The NDR region can be adjusted by varying the AV between the inner TD and the body. Not only the peak-to-valley current ratio (PVCR) but also the voltage range where NDR occurs can be controlled. It is supposed that the injected electrons and the inversion charges increase and decrease with negative bias, respectively, for the MIS(p) TD and play an important role in this observation. Meanwhile, the asymmetry of inner gate and ring gate enhances the coupling efficiency at reverse bias region. In this paper, the PVCR can be tuned to more than two orders and the voltage of the NDR region can be shifted to larger than 1 V. The tunable NDR characteristic of MISIM provides a possible application of MIS TD. [ABSTRACT FROM AUTHOR]

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (D'S) of SiO2/Al2O3 insulator. Devices with contact area of 500 × 20 nm and lengths of 2 μm show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the D'S enables a 60% reduction in reset energy compared with SiO2-isolated devices. [ABSTRACT FROM PUBLISHER]

This paper demonstrates and investigates the time-dependent vertical breakdown of GaN-on-Si power transistors. The study is based on electrical characterization, dc stress tests and electroluminescence measurements. We demonstrate the following original results: 1) when submitted to two-terminal (drain-to-substrate) stress, the AlGaN/GaN transistors show a time-dependent degradation process, which leads to the catastrophic failure of the devices; 2) time-to-failure follows a Weibull distribution and is exponentially dependent on stress voltage; 3) the degradation mechanism is strongly field dependent and weakly thermally activated, with an activation energy of 0.25 eV; and 4) emission microscopy suggests that vertical current flows under the whole drain area, possibly through extended defects. The catastrophic failure occurs at random positions under the drain contact. The time-dependent failure is ascribed to a percolation process activated by the high-electric field that leads to the generation of localized shunt paths between drain and substrate. [ABSTRACT FROM PUBLISHER]

For the experimental determination of the emitter resistance of bipolar junction transistors and HBTs, many methods exist in the literature, which yield quite different results though. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations, including different device types (i.e., high-speed and high-voltage transistors). First, the accuracy of the methods is evaluated based on simulated data using a compact model. Explanations for causes of observed inaccuracy or failure are given and discussed. Second, suitable methods are applied to experimental data. In both cases, the results are compared for a large variety of device sizes. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, device size, and operating range; as well as its requirements in terms of equipment and extraction effort. A guideline for extracting the emitter resistance is also given. [ABSTRACT FROM AUTHOR]

A stress-and-sense charge pumping (SSCP) technique is proposed in this paper to measure the stress-induced interface trap ( $\Delta N_{{\rm {it}}})$ in real-time evolution without stress interruption. Results show that the $\Delta N_{{\rm {it}}}$ measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The $\Delta N_{{\rm {it}}}$ measured by SSCP method after interruption is approximately equal to that by the conventional one. The amount of recoverable $\Delta N_{{\rm {it}}}$ is almost constant and independent of permanent damage. The stress-induced threshold voltage shift ( $\Delta V_{{\rm {th}}})$ and $\Delta N_{{\rm {it}}}$ under various stress frequencies and duty cycles are also measured. The $\Delta V_{{\rm {th}}}$ seems to depend only on the total stress time of stress pulse. The $\Delta N_{{\rm {it}}}$ measured by SSCP with different frequencies and duty cycles is similar. The $\Delta N_{{\rm {it}}}$ also depends on the total stress time of stress pulse, but not the off time during the nonstress half cycle. In addition, it is found that the recovery induced by nonstress half cycle of ac stress is almost negligible as compared with that induced by stress interruption. Moreover, a two-stage phenomenon is observed on $\Delta N_{{\rm {it}}}$ evolution. Results in this paper indicate that the stressing indeed induces trap generation in the first stage. [ABSTRACT FROM AUTHOR]

DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements. [ABSTRACT FROM AUTHOR]

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration ( \textN\text {S}) and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance. [ABSTRACT FROM PUBLISHER]

This paper presents a new nonlinear microwave-based characterization methodology for the study of the deep levels proprieties in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). Currently, it is unique measurement method allowing the extraction of time constants of HEMTs operating under large signal RF conditions. This method improves the conventional dc techniques, since it employs RF excitation during the filling condition to investigate the impact of “real-life” RF excitation on the trapping mechanisms. The experimental results demonstrate that, beyond the presence of Poole–Frenkel effect, the slow detrapping time constant is accelerated by the power dissipation of the trapping bias point. Moreover, it is possible to distinguish the impact of dc and RF conditions on the trapping phenomena. The temperature measurements allow identifying the 0.75-eV deep level, attributed to extended defects in GaN, when ionized under dc excitation. This deep level trap is probably located in the buffer layer and contributes to the RF trapping phenomenon. [ABSTRACT FROM PUBLISHER]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

In the above paper, Kim et al. present a method for extracting source and drain resistance values in MOSFETs. We explain how the proposed method corresponds to a particular case of the method already proposed by Ortiz-Conde et al. in a seminal work published in 1994 and generalized two years later, which was not cited in the above-mentioned paper. We call attention to the fact that the absence in Kim’s method of the threshold voltage dependence on body-source voltage and such disregard might eventually lead to significant errors. [ABSTRACT FROM AUTHOR]

The aim of this paper is to investigate the degradation mechanisms of UV-B AlGaN-based light-emitting diodes (LEDs) submitted to constant current stress beyond the typical application conditions. We demonstrate the existence of two main degradation mechanisms that significantly impact the relative amplitude of the main quantum well (QW) peak at 310 nm and of a parasitic peak at ~340 nm related to the electron overflow toward the last quantum barrier before the p-side. These mechanisms are thoroughly investigated by means of electrical and optical measurements, and by photocurrent (PC) spectroscopy. We demonstrate that in the first 50 h of stress, degradation is caused by an increased defect density in the last quantum barrier and/or carrier escape from the QWs, which results in a decrease in the QW emission and in an increase in the parasitic peak at 340 nm. For longer stress times, degradation is dominated by a diffusion process, causing an increase in defect density and nonradiative recombination in the LED. This has a direct impact on both the QW peak and the parasitic peak, which show a significant decrease for long stress times. PC spectroscopy demonstrates that the defects responsible for degradation are most likely located next to mid-gap, thus acting as efficient nonradiative recombination centers. [ABSTRACT FROM AUTHOR]

This paper focuses on the modeling of the avalanche multiplication coefficient in state-of-the-art SiGe:C HBTs suffering from radical self-heating and impact-ionization effects. Experimental data are measured in a wide current range on devices fabricated during the DOTFIVE project and used as a reference. A comparative analysis of the available empirical descriptions for the avalanche coefficient is made at low current density; the best model is then extended to account for medium/high-current effects by resorting to a suitable parameter optimization methodology. The same procedure is adopted to examine the accuracy of physics-based formulations implemented in advanced transistor models for circuit design. [ABSTRACT FROM AUTHOR]

The aim of this paper is to compare the thermal properties of monocrystalline GaN devices assembled to direct bonding copper (DBC) substrate by silver sintering and solid–liquid interdiffusion (SLID) techniques. The construction of the examined diodes is described and selected results of measurements of thermal parameters of the tested diodes are discussed. It was concluded that the lowest values of thermal resistance between the junction and the case are achieved using the SLID technique, despite the fact that this process was performed at a lower temperature. Moreover, it was concluded that the method of assembly of a package to the heat sink has influence on thermal resistance between the junction and the surroundings. [ABSTRACT FROM AUTHOR]

In ultrathin fully depleted SOI PIN structures with underlapped gate, the front and back gates can be biased such as to emulate electrostatic diodes. The gate-induced electrons and holes result in a virtual P-N junction in the center of an undoped body. The current–voltage I–V curves are essentially diode-like but reconfigurable via gate voltage tuning. The virtual P-N and P-I-N diodes are used, for the first time, to evaluate the carrier lifetime in ultrathin SOI layers. This paper presents novel experiments and simulations. The transition between recombination and diffusion current in I–V characteristics enables quick lifetime extraction. A more evolved and accurate technique consists in monitoring the reverse recovery current in virtual diodes. This method reveals a very short carrier lifetime in 7-nm-thick SOI layers where surface recombination prevails. This result is confirmed by adapting a P-I-N-diode technique to sub-10 nm films. [ABSTRACT FROM AUTHOR]

Low-power circuits are important for many applications, such as Internet of Things. Device variations and fluctuations are challenging their design. Random telegraph noise (RTN) is an important source of fluctuation. To verify a design by simulation, one needs assessing the impact of fluctuation in both driving current $\Delta {I}_{d}$ and threshold voltage $\Delta {V}_{\textsf {th}}$. Many early works, however, only measured RTN-induced $\Delta {I}_{d}$. $\Delta {V}_{\textsf {th}}$ was not directly measured because of two difficulties: its average value is low and it is highly dynamic. Early works often estimated $\Delta {V}_{\textsf {th}}$ from $\Delta {I}_{d}/{g}_{m}$ (${V}_{g} = {V}_{\textit {dd}}$), where ${g}_{m}$ is the transconductance, without giving its accuracy. The objective of this paper is to develop a new Trigger-When-Charged (TWC) technique for directly measuring the RTN-induced $\Delta {V}_{\textsf {th}}$. By triggering the measurement only when a trap is charged, measurement accuracy is substantially improved. It is found that there is a poor correlation between $\Delta {I}_{d}/{g}_{m}$ (${V}_{g} = {V}_{\textit {dd}}$) and the directly measured $\Delta {V}_{\textsf {th}}$ (${V}_{g} = {V}_{\textsf {th}}$). The former is twice of the latter on average. The origin for this difference is analyzed. For the first time, the TWC is applied to evaluate device-to-device variations of the directly measured RTN-induced $\Delta {V}_{\textsf {th}}$ without selecting devices. [ABSTRACT FROM AUTHOR]

This paper investigates the trapping mechanisms in gate-injection transistors (GITs) without and with a pdrain electrode, referred to as GITs and Hybrid-Drain-embedded GITs (HD-GITs), respectively, used to inject holes and reduce charge trapping effects. We compare the two sets of devices under both the OFF-state and semi- ON state, to investigate the role of hot electrons in favoring the charge trapping. The analysis is based on combined pulsed characterization, transient measurements, and electroluminescence (EL) characterization. We demonstrate the following relevant results: 1) GITs and HD-GITs have comparable and negligible dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ when trapping is induced in the OFF-state; under semi- ON state conditions, GITs suffer from significant dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ , while HD-GITs show no additional trapping with respect to OFF-state; 2) EL characterization carried out until ${V}_{\mathsf {DS}}= 500$ V in semi- ON conditions shows comparable features, suggesting that the electric field and hot-carrier density are similar in GITs and HD-GITs. This result indicates that the hot-electron trapping rate is identical for the two sets of samples, so the difference observed in dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ must be ascribed to a different detrapping rate; 3) transient ${R}_{ \mathrm{\scriptscriptstyle ON}}$ measurements indicate that the traps filled in the OFF-state conditions are the same as those filled by hot electrons in semi- ON, with ${E}_{a}= 0.8$ eV (possibly ${C}_{N}$); and 4) EL analysis under constant bias indicates that in GITs there is a time-dependent increase in the luminescence signal at the drain terminal, when the devices are biased with ${V}_{\mathsf {DS}}= 300$ V. Such effect, indicative of hot-electron trapping, is not observed in HD-GITs. Based on the experimental evidence collected within this paper, we conclude that—in the semi- ON state—the main difference between GITs and HD-GITs consists in a faster detrapping rate of hot electrons, achieved through hole injection from the pdrain terminal. [ABSTRACT FROM AUTHOR]

In-memory computing is a promising non-von Neumann approach where certain computational tasks are performed within resistive memory units by exploiting their physical attributes. In this paper, we propose a new method for fast and robust compressed sensing (CS) of sparse signals with approximate message passing recovery using in-memory computing. The measurement matrix for CS is encoded in the conductance states of resistive memory devices organized in a crossbar array. In this way, the matrix-vector multiplications associated with both the compression and recovery tasks can be performed by the same crossbar array without intermediate data movements at potential ${O}{(}{1}{)}$ time complexity. For a signal of size ${N}$ , the proposed method achieves a potential ${O}{(}{N}{)}$ -fold recovery complexity reduction compared with a standard software approach. We show the array-level robustness of the scheme through large-scale experimental demonstrations using more than 256k phase-change memory devices. [ABSTRACT FROM AUTHOR]

This paper provides insight into the transport mechanisms of the collector current in SiGe HBTs operating at cryogenic temperatures and compares three technology generations of devices. Based on the experimental data, a method to differentiate direct tunneling from quasi-ballistic transport is proposed. Measurements indicate that direct tunneling becomes more significant at cryogenic temperatures. The effects of technology scaling on the direct tunneling were investigated using TCAD. Direct tunneling was found to be sensitive to the base width and the Ge profile. It is predicted that without an increase in the Ge content, direct tunneling may dominate over quasi-ballistic transport at the limits of technology scaling. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices. [ABSTRACT FROM AUTHOR]

This paper presents a new theoretical equivalent model (TEM) for organic light-emitting diodes (OLEDs). The parameters of TEM are identified using a simple characterization procedure based on auxiliary circuits and low-cost equipment. From this TEM, a method for intrinsic capacitance identification is proposed. This model is useful to simulate and analyze OLED devices considering dynamic and steady-state operation conditions. In addition, it provides guidelines for manufacturers and lighting designers to enhance the device performance and to design dedicated OLED drivers. In order to validate the proposal of this paper, four commercial OLEDs are tested, and the comparison between the theoretical and the experimental results is satisfactory. [ABSTRACT FROM PUBLISHER]

In this paper, we investigated the performance of SrTiO3 (STO) resistive random-access memory (RRAM) as a candidate to realize short-term synaptic elements in neuromorphic circuits. Ionic defect movement within oxides is postulated to play a significant role in resistive state reconfiguration of these devices. This relatively small movement in oxides was sensed by developing a novel measurement technique using differential voltammetry. Using this technique, the widely hypothesized belief of drift and diffusion of ionic defects in oxides was systematically studied and linked to the state reconfiguration in STO RRAM. Next, the devices’ state retention was examined and a consistent decay of the resistive state was observed. The decay rate was found to be a function of the conditioning voltage, allowing us to control the state decay via operational voltages. We then developed a test battery that quantified how these devices operate within a spike-rate encoded learning paradigm. By utilizing a carefully tuned test battery, we were able to quantify the magnitude of potentiation and depression due to varying spike amplitudes and spike rates. These tests provide a systematic methodology to capture the constantly changing resistive state of short-term synaptic elements. [ABSTRACT FROM AUTHOR]

Sub-bandgap (SBG) impact ionization (II) enables steep subthreshold slope that enable devices to overcome the thermal limit of 60 mV/decade. This phenomenon at low voltage enables various applications in logic, memory, and neuromorphic engineering. Recently, we have demonstrated sub-0.2-V II in n-i-p-i-n diode experimentally primarily based on steady-state analysis. In this paper, we present the detailed experimental transient behavior of SBG-II in n-i-p-i-n. The SBG-II generated holes are stored in the p-well. First, we extract the leakage mechanism from the p-well to show two mechanisms: 1) recombination–generation and 2) over the barrier (OTB), where OTB dominates when barrier height ${\phi }_{b}<\textsf {0.59}~\textsf {eV}$. Second, we analytically extract the SBG-II current (${I}_{\textsf {II}}$) at 300 K from the experimental results. The drain current (${I}_{D}$), electric field (${E}{-}\textsf {field}$), and ${I}_{\textsf {II}}$ are plotted in time. We observe that ${I}_{\textsf {II}}$ increase as ${E}{-}\textsf {field}$ reduces which indicates that ${E}$ -field does not primarily contribute to ${I}_{\textsf {II}}$. Furthermore, ${I}_{D}$ shows two distinct behaviors: 1) ${I}_{\textit {II}} ({I}_{D}$) is constant at the beginning and 2) eventually “universal” ${I}_{\textsf {II}} ({I}_{D}$) is linear, i.e., ${I}_{\textsf {II}}={k}\times {I}_{D}$ where ${k} = \textsf {1}\textsf {0}^{-\textsf {3}}$ ; we also show that the electrons primarily contributing to ${I}_{D}$ are directly incapable of II due to insufficient energy ($< {E}_{g}$). Fischetti’s model showed that SBG-II is primarily caused by “hot” electrons that accept energy in an Auger-like process from “cold” drain electrons to enable SBG-II. We speculate that if ${I}_{D}$ electrons “heat-up” the cold drain electrons, which would further energize the hot electrons to produce the observed ${I}_{\textsf {II}}{(}{I}_{D}$) universal dependence. [ABSTRACT FROM AUTHOR]

In this paper, fast trap behaviors in Ge pMOSFETs with Al2O3/GeOx/Ge gate-stack are evaluated and quantitatively characterized using a novel sub-1-ns ultrafast measurement (UFM) system. By changing the operation temperature and the rising time of the applied gate voltage (${V}_{\text {g}}$), it is found that the fast trap filling process could be observed within the first 10 ns after the gate voltage was applied, and the process would be more clearly characterized at a raised operation temperature. In addition, the trap density distribution and the time constant of the fast traps inside the valence band edge are experimentally extracted based on the UFMs. It is found that the trap densities inside the valence band edge are within the range of 1013 to 1014 cm $^{-2}\cdot \text {eV}^{-1}$ , which are consistent with the reported values from the Hall measurements. It is experimentally confirmed that the time constants of the fast traps in Ge pMOSFETs with Al2O3/GeOx/Ge gate-stack are about 10 ns, and deeper energy level corresponds to smaller time constant. [ABSTRACT FROM AUTHOR]

This paper investigates AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on epistructures with carbon (C)-doped buffers. Metalorganic chemical vapor deposition is used to grow two C-doped structures with different doping profiles, using growth parameters to change the C incorporation. The C concentration is low enough to result in n-type GaN. Reference devices are also fabricated on a structure using iron (Fe) as dopant, to exclude any process related variations and provide a relevant benchmark. All devices exhibit similar dc performance. However, pulsed ${I}$ – ${V}$ measurements show extensive dispersion in the C-doped devices, with values of dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}~3$ –4 times larger than in the dc case. Due to the extensive trapping, the devices with C-doped buffers can only supply about half the output power of the Fe-doped sample, 2.5 W/mm compared to 4.8 W/mm at 10 GHz. In drain current transient measurements, the trap filling time is varied, finding large prevalence of trapping at dislocations for the C-doped samples. Clusters of C around the dislocations are suggested to be the main cause for the increased dispersion. [ABSTRACT FROM AUTHOR]

The temperature dependence of the Schottky voltage under a forward constant current was used as a means to measure the transient temperature characteristics of gallium nitride (GaN) high-electron-mobility transistors (HEMTs). However, the degradation of the Schottky diode leads to error in the calculated temperature measurement results, especially at a high forward Schottky current. In this paper, we characterized the degradation of GaN HEMT Schottky diodes under forward bias using pulsed current–voltage measurements. The forward Schottky voltage behavior at constant currents of 0.2, 0.35, 0.5, 1, 1.5, and 2 mA was monitored. In particular, the vertical temperature distribution was corrected experimentally based on the transient voltage measurements. The success of this correction indicates that the said artifacts can be removed using the transient voltage measurements. This method increases the accuracy of temperature measurements when the temperature dependence of the Schottky voltage is used to characterize the behavior of GaN HEMTs. [ABSTRACT FROM AUTHOR]

This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic R {\mathrm{\scriptscriptstyle ON}} increase when they are submitted to soft switching up to V{\text {DS}}= 600 V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- R \mathrm{\scriptscriptstyle ON}) . The increase in dynamic R \mathrm{\scriptscriptstyle ON} induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in R \mathrm{\scriptscriptstyle ON} is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic R \mathrm{\scriptscriptstyle ON} becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice. [ABSTRACT FROM PUBLISHER]

The tunnel-FET (TFET) is a promising candidate for future low-power logic applications, because it enables a sub-60-mV/decadesubthresholdswing. However, themost experimental TFETs are plagued by unwanted trap-assisted tunneling (TAT) and Shockley–Read–Hall (SRH) carrier generation, which degrade the swing and increase the leakage floor, hence forming a major roadblock for TFET adoption. This degradation is attributed to bulk traps, semiconductor/oxideinterface traps, and/or heterojunction interface traps, but it is still unclear which of the three trap types are dominant. In this paper, we focus on TAT and SRH caused by bulk traps. We calibrate SRH and TAT models with the help of In0.53Ga0.47As p+/n+ and p+/i/n+ diodes grown on lattice matched substrates by molecular beam epitaxy (MBE). We then perform calibrated simulations of an In0.53Ga0.47As TFET, which show bulk SRH and TAT are sufficiently low compared with the target OFF-state current and, hence, not a significant issue. Therefore, it is likely that high SRH and TAT commonly observed in experimental homojunction InGaAs TFETs, MBE-grown on lattice matched substrates, are not caused by bulk semiconductor defects, but by semiconductor/oxide interface defects. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance. [ABSTRACT FROM AUTHOR]

Aluminium gallium nitride (AlGaN)/GaN high-electron mobility transistor performance is to a large extent affected by the buffer design, which, in this paper, is varied using different levels of carbon incorporation. Three epitaxial structures have been fabricated: 1) two with uniform carbon doping profile but different carbon concentration and 2) one with a stepped doping profile. The epitaxial structures have been grown on 4H-SiC using hot-wall metal–organic chemical vapor deposition with residual carbon doping. The leakage currents in OFF-state at 10 V drain voltage were in the same order of magnitude ( 10^-4 A/mm) for the high-doped and stepped-doped buffer. The high-doped material had a current collapse (CC) of 78.8% compared with 16.1% for the stepped-doped material under dynamic $I$ – $V$ conditions. The low-doped material had low CC (5.2%) but poor buffer isolation. Trap characterization revealed that the high-doped material had two trap levels at 0.15 and 0.59 eV, and the low-doped material had one trap level at 0.59 eV. [ABSTRACT FROM PUBLISHER]

Devices based on nanostructures hold great potential to improve the performance of present light emitter technologies. In this paper, we examine a buried multiquantum well III-nitride diffusion injected light-emitting diode (DILED), where the active region is located outside the p-n junction and current injection to the active region takes place through bipolar diffusion. We study the current–voltage behavior and light emission characteristics of the DILED as a function of temperature experimentally and theoretically. We show that in contrast to conventional LEDs, the light output efficiency of the DILED increases when temperature is increased from 0 °C to 100 °C. This anomalous temperature behavior is shown to be linked to the strong temperature dependency of ionized acceptor density in the p-doped region, which increases the hole diffusion current into the active region. This highlights the fundamental difference in the operating principle of the DILED compared with conventional LEDs. In addition to optical and electrical characterization of a DILED, we also study the relation of the observed yellow-band luminescence to Shockley–Read–Hall recombination, compare the measurements to charge carrier transport simulations, and present an equivalent circuit model of the DILED structure for additional insight into the new current injection scheme. [ABSTRACT FROM AUTHOR]

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%. [ABSTRACT FROM AUTHOR]

In this paper, alternative operational mode (AOM) of Si-based blocked impurity band (BIB) detectors is thoroughly investigated. The basic structure of the detector evolves from the prototype of the ion-implanted BIB detector, which is potentially compatible with CMOS processes. Benefiting from lower dark current, the detectivity of ion-implanted devices studied in this work is comparable with the Si BIB detectors ever reported. For ion implantation devices, a peak blackbody detectivity of ${5} \times {10}^{{12}}$ cm $\cdot $ Hz1/2/W (background temperature T = 40 K) occurs at 2 V under AOM. These merits make the ion-implanted device a powerful candidate for a wide range of applications from infrared to terahertz band. By analyzing the carrier distribution and the band structure in different functional regions of the device at the measured temperature, depletion junction formed in the region of active layer near active layer/cathode interface side is deduced when the device is operated under AOM. The theory is successfully used to interpret experimental data, including the detectivity comparable to the epitaxial device, significantly reduced dark current. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, ZnO nanorod humidity sensors with dye-sensitized solar cells (DSCs) were prepared on indium tin oxide conductive glass. The average diameter and length of the ZnO nanorods were ~100 nm and $\sim 1.5~\mu \text{m}$ , respectively. After ZnO nanorods were grown, TiO2 film was coated by TiO2 with a nanoparticle size of approximately 26 nm through the doctor blade method. The sensitizer N3 was used for charge transfer on the DSCs. The solar photovoltaic conversion efficiency of the DSCs was approximately 4.7%. Humidity sensors were used for measurement under ultraviolet (UV) light at 365 nm. During UV illumination, the current increased under low humidity and gradually decreased under high humidity. The integrated device exhibited similar stable and sensitive performance as the traditional ZnO humidity sensor. Experimental results revealed that DSCs could be integrated with ZnO nanorod humidity sensors to create a self-powered integrated device that has potential Internet of Things applications. [ABSTRACT FROM AUTHOR]

Diodes in forward direction exhibit excellent ESD ruggedness and are thus widely used in both discrete and on-chip electro-static discharge (ESD) protection devices. Due to the conductivity modulation under an ESD stress, a transient voltage overshoot is observed at the beginning of a fast discharge event. Since the voltage overshoot can be harmful, understanding the origin of the overshoot is crucial to design optimized protection diodes. In this paper, it will be shown that existing models can result in much underestimated overshoot voltage, especially for diodes with a large lowly doped region. This can be attributed to the negligence of transient charge distribution in the lowly doped region. A new model that takes this effect into account as well as impact-ionization is presented. [ABSTRACT FROM AUTHOR]

Nanowire transistors are typically fabricated as geometrically symmetrical devices, with metal/semiconductor source and drain contacts rather than a graduated doping profile. While the source and drain contacts are nominally identical, contact asymmetry can arise when the gate contact is not centered over the nanowire, leaving uneven access regions with no gate coverage on one or both sides of the channel. Measuring the characteristics of devices with symmetric and asymmetric contact geometries allows contact effects to be studied. In this paper, indium arsenide nanowire transistors were fabricated with symmetric and asymmetric gate coverage. It is shown that devices with highly asymmetric gate coverage can exhibit a factor of 10 change in current and a shift in threshold of up to 0.5 V upon reversing the source–drain orientation. Devices with highly asymmetric properties show nearly identical channel-generated noise yet a significant difference in contact-generated noise levels when the contact orientation is reversed. Fully symmetric devices show higher current levels, lower threshold voltages, and lower contact-generated noise than asymmetric devices with either source or drain gated, but channel-generated noise levels are similar. [ABSTRACT FROM PUBLISHER]