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This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications. [ABSTRACT FROM AUTHOR]

Selector-less resistive random-access memory (RRAM) devices require high nonlinearity (NL) in low-resistance state current ( ${I}_{\textsf {LRS}}$ ). In this paper, we investigate the effect of composition (here, Ca%)-dependent material properties, viz., ion migration barrier, and thermal conductivity, on memory performance of recently demonstrated Pr1–xCaxMnO3-based selector-less RRAM with high NL. First, the NL increases as “ $\mathit {x}$ ” decreases. This is attributed to higher self-heating in $\textsf {PCMO}{(}\mathit {x}{)}$ films as composition-dependent thermal conductivity ( $\kappa $ ) decreases as “ $\mathit {x}$ ” is decreased. This enables selector-less operation. Second, larger memory window is observed as “ $\mathit {x}$ ” increases due to decrease in the voltage required for onset of RESET process (i.e., $V_{\textsf {MIN, RESET}}$ ) as “ $\mathit {x}$ ” is increased. Lower $V_{\textsf {MIN, RESET}}$ at higher “ $\mathit {x}$ ” is due to higher oxygen-ion conductivity attributed to lower migration barrier ( ${E}_{m}$ ). Third, retention is measured at different temperatures to extract composition-dependent ${E}_{m}$. The poor memory retention performance for $\mathit {x}= 1$ is consistent with lower ${E}_{m}$ estimated. Finally, enhanced endurance is observed for lower ${E}_{m}$ due to low-energy requirement for switching. Based on these observations, an interrelation between ${E}_{m}$ , retention, and endurance is established. Therefore, an interplay of composition-dependent thermal conductivity and oxygen-ion migration barrier enables tunable memory characteristics in Pr1–xCaxMnO3-based RRAM. [ABSTRACT FROM AUTHOR]

The understanding of failure behavior is one of the basic requirements for further development of nonvolatile resistive random access memory (RRAM) devices. In this paper, we show a detailed analysis of a temperature-dependent low-resistance state (LRS) retention failure behavior of RRAM based on TiOx/Al2O3 bilayer structure. The device is capable of showing good resistive switching properties with stable operating parameters. The LRS current conduction process is mostly dominated by the Fowler-Nordheim tunneling. Retention behavior has been studied with a wide range of temperatures from room temperature to 200 °C with different compliances. The experimental results of TiOx/Al2O3 bilayer resistive switching memory are further supported theoretically by the Meyer-Neldel rule, which is fit well to the retention failure time. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a tunable Schottky diode based on amorphous indium–gallium–zinc–oxide (a-IGZO) film with high performance for rectifying circuit and bipolar one diode-one resistor (1D1R) crossbar applications. By modulating the oxygen content in the a-IGZO film, the device shows adjustable behavior. Under the high oxygen content condition, the device displays outstanding diode features with a large rectification ratio up to 108 at ±1 V and a high forward current density of 100 A/cm2 at ±1 V when used Cu as the top electrode. The thermionic emission model is proposed to explain the Schottky diode behavior. And by utilizing the superior rectifying performance, we successfully demonstrate the dynamic rectifying application. In addition, we combine the optimized Schottky diode device with the bipolar-type resistive random access memory (RRAM) device to investigate the Schottky diode device in 1D1R crossbar application. As a result of its tunable nature and low processing temperature, the a-IGZO Schottky diode is a promising element for rectifying circuit and bipolar 1D1R crossbar applications. [ABSTRACT FROM AUTHOR]

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the limiting factors for building large-scale V-RRAM arrays. The previous approach to evaluate the write/read margin of V-RRAM was based on the exhaustive SPICE simulations, which prohibits the design exploration to MB-level as it takes huge amount of computation resources. In this paper, a quasi-analytical model is proposed, which aims to reduce the simulation time and the required memory usage. Through the validation with the SPICE simulation results, the proposed model shows a similar accuracy. Based on the proposed quasi-analytical model, the worst case data pattern of 3-D V-RRAM with large array size up to 4 MB is analyzed. The results show that it is more efficient to increase the number of stack layers than expanding the horizontal array size to achieve large subarray size. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

In this paper, the presence of filamentary current instabilities in the high resistance state of Ni/HfO2-based RRAM devices and their associated current fluctuations mechanisms are explored. After systematic measurements, the advanced weighted time-lag plot method is employed to accurately identify the contribution of multiple electrically active defects and to minimize the negative effect of the background noise. Special attention is given to the physical analysis of multilevel random telegraph noise (RTN) signals caused by both independent and interactive defects located in the vicinity of the conductive filament (CF), which may alter the tunneling path and induce large stochastic current fluctuations. In addition, irreversible current changes, owing to trap density variations inside or near the CF, are also identified. Finally, the voltage dependence of the RTN phenomena and the occurrence of stress-induced complex fluctuations is evaluated. [ABSTRACT FROM PUBLISHER]

In this paper, we demonstrate three key features of oxide-based nano-oscillators: 1) the observation of threshold switching and filamentary oscillations in TaOx; 2) the highest frequency achieved by oxide-based oscillators; and 3) a study with linear (resistor) and nonlinear (transistor) ballasts to clearly understand the role of filament dynamics in scaling. These oscillators show frequency tunability over the range of 20 kHz–250 MHz, with 250 MHz being the highest reported frequency for this class of oscillators. Different types of ballasts show frequency tunability using two distinct methods: 1) by tuning the channel resistance of the transistor and 2) by increasing the rail voltage across the ballast–device pair. This sheds new light on the oscillator dynamics for dense oscillator arrays aimed at oscillatory neural networks and other applications. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

Metal/NiO/Pt films with various electrodes were fabricated to investigate the effects of standard free energy (SFE) on NiO resistive switching devices. By selecting Ti, Ta, Ag, Cu, and Co as the top electrodes (TEs), we found that the switching voltage was inversely proportional to the SFE. The reason for this is attributed to the different thicknesses of the oxidized interface between TE and NiO. Since the thickness of the oxidized interface depends on the SFE, this paper provides an effective way to control and adjust the switching voltage. [ABSTRACT FROM PUBLISHER]

This paper investigates the characteristics of applying indium–tin oxide (ITO) with and without nitride gas (N2) as the insulator in resistive random access memory (RRAM). After cosputtering an ITO target with N2 as the insulator and capping the same ITO material as the top electrode, the device exhibits rectifier and resistance switching characteristics before and after the forming process, respectively. The Schottky diodelike rectifier mechanism was also verified by various temperature measurements. Furthermore, robust resistance switching at a positive forming voltage, smaller than that required during negative bias forming, can be achieved. Both positive and negative forming processes are examined with current fitting results, which show different dominant mechanisms when using positive or negative biases. All these mechanisms have also been verified by temperature effect experiments, which confirmed the dominant conduction mechanisms. This, in combination with the fact that the positive forming voltage itself is smaller than the negative forming voltage, and decreases with device scale down, provides two highly beneficial results. This good performance achieved by using ITO with N2 suggests significant progress of RRAM and remarkable potential applications. [ABSTRACT FROM PUBLISHER]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

In this paper, nonpolar resistive switching behavior is reported for the first time in a SZO-based memory device. The electrode materials used which have different conductivities affect the resistive switching properties of the device. The AI/V:SZO-LNO/Pt device shows nonpolar switching behavior, whereas the AI/V:SZO/LNO device has bipolar switching property. The resistance ratios of these two devices are quite distinct owing to the difference between the resistance of low resistance states. The AI/V:SZO-LNO/Pt device with lower resistive switching voltages (±7 V turn on and ±2 V turn off) and higher resistance ratio (107) is more suitable for practical applications compared to the AI/V:SZO/LNO device. The switching speed of the AI/V:SZO-LNO/Pt device is 10 ns, which is the fastest speed that has ever been reported. The conduction mechanisms, nondestructive readout property, retention time, and endurance of this device are also reported in this paper. [ABSTRACT FROM AUTHOR]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for metal–oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed $I$ – $V$ characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the model’s applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level. [ABSTRACT FROM PUBLISHER]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic andmemory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory. [ABSTRACT FROM AUTHOR]

Enlargement of memory window through forming compliance current was demonstrated in Gd:SiO2 resistive random access memory (RRAM) with a gadolinium (Gd) electrode. Lower forming compliance current for Gd:SiO2 RRAM with a Gd electrode results in larger memory window as compared with the RRAM with a Pt electrode. Through analyses on the current conduction mechanism, we demonstrate that a lower forming compliance current leads to a thinner conductive filament forming and less oxygen ions penetrating into Gd electrode, which caused higher on current and lower off current. Furthermore, a possible resistive switching model was proposed to explain the effect of Gd electrode on RRAM device. [ABSTRACT FROM AUTHOR]

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance. [ABSTRACT FROM AUTHOR]

A versatile multiphysics simulation packet for investigating different resistive random acces memories (RRAMs) is developed in this paper. Heat transfer, electrical conduction, and ion migration in such heterogeneous structure are all taken into consideration. Three fully coupled partial differential equations are solved using our self-developed finite-difference algorithm, where Scharfetter–Gummel method is adopted to simulate ion migration with fast convergence achieved. This packet is validated in comparison with the commercial software based on the finite-element method. With its implementation, complete and clear pictures for crosstalk effect in vertically integrated RRAM are captured and compared, where the effects of key physical and geometrical factors are characterized and understood. Some useful suggestions to mitigate its unfavorable influences are given. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations. [ABSTRACT FROM AUTHOR]

This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector–one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonnegligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed. [ABSTRACT FROM AUTHOR]

In this paper, the resistive switching behavior of a single-component-polymer resistive memory device based on polychloro-para-xylylene (parylene-C) is comprehensively studied. With the excellent chemical stability and high process compatibility of parylene-C, an 8 \times 8 crossbar array with a sandwiched structure of parylene-C and active electrodes is fabricated, which can be integrated in the CMOS back-end process and shows great potentials for future transparent, low-cost, flexible, and high-density nonvolatile memory applications. This organic memory device exhibits excellent performance with a \10^7 on/ off current ratio, nanosecond set/reset speed, and low switching voltages, as well as good retention and cycling endurance behaviors. The switching mechanism is systematically investigated with the comparison between active electrodes (Al, Cu, or Ag) and an inert electrode (Pt), as well as the dependence on temperature and device area. [ABSTRACT FROM AUTHOR]

This paper reports the effects of rapid thermal annealing (RTA) on resistive switching (RS) characteristics and mechanisms of \SrZrO3 (SZO)-based memory devices. SZO thin films were deposited on \LaNiO3 (LNO) (\100)/\Pt/Ti/SiO2/\Si using radio-frequency magnetron sputtering and were followed by an RTA process in \N2, Ar, and \O2 ambients, respectively, at various temperatures for improving RS performance. Experimental results indicate that an SZO device annealed in \O2 at 600 ^\circ\C (\O2-600) exhibits stable RS properties and has a high device yield (\sim 90%), a reliable retention characteristic (up to \1 \times \10^6\ \s at 100 ^\circ\C), and steady nondestructive readout properties (over \1.4 \times \10^4\ \s at 100 ^\circ\C). However, by increasing RTA temperature to more than 700 ^\circ\C, random formation of LNO (110) precipitates on the bottom surface of SZO grains might shorten the effective thickness of the SZO thin films. Furthermore, a strong electric field possibly occurs at the region between Al top electrodes and low-resistivity LNO precipitates. It is speculated that an RS phenomenon, which occurs within SZO grains instead of on grain boundaries, easily leads to RS failure, further resulting in severe degradation of device yield in the \O2-700 and \O2-800 devices. When compared with other devices, \O2-600 SZO memory devices exhibit highly reliable RS characteristics. [ABSTRACT FROM AUTHOR]

The conduction mechanism and resistive switching properties in a resistive-random-access-memory device composed of Al(top)/TiOx/TiO2/Al(bottom) are investigated in this paper. The active-top-electrode (TE) material aluminum interacted with the TiO2 layer and induced an oxygen-deficient TiOx layer near the TE. The naturally formed oxygen-deficient TiOx layer was confirmed by a transmission-electron-microscope energy-dispersive X-ray spectrometry analysis. The oxygen-deficient TiOx region acted as a trap for electrons and contributed to the resistive switching. The proposed mechanism and measured data are verified through simulation of a two-variable resistor model. [ABSTRACT FROM AUTHOR]

The unidirectional bipolar resistance switching in GaN/InGaN-based light-emitting diode (LED) was discovered to explore optically readable resistive random access memory (RRAM) device. The device displays stable resistance window in both endurance and retention tests, showing good nonvolatility for memory application. The light-emitting state of this device can also be tuned by the resistance switching. Such phenomenon is illustrated as the switching between conventional light-emitting rectifying behavior and nonlight-emitting metal-like ohmic behavior. Large amount of structural and point defects in the epitaxial wafer were considered as the main contributor to the resistance switching in LED device. [ABSTRACT FROM AUTHOR]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

Research on memory devices is a highly active field, and many new technologies are being constantly developed. However, characterizing them and understanding how to bias for optimal performance are becoming an increasingly tight bottleneck. Here, we propose a novel technique for extracting biasing parameters, conducive to desirable switching behavior in a highly automated manner, thereby shortening the process development cycles. The principle of operation is based on: 1) applying variable amplitude, pulse-mode stimulation on a test device in order to induce switching multiple times; 2) collecting the data on how pulsing parameters affect the device’s resistive state; and 3) choosing the most suitable biasing parameters for the application at hand. The utility of the proposed technique is validated on TiOx-based prototypes, where we demonstrate the successful extraction of biasing parameters that allow the operation of our devices both as multistate and binary resistive switches. [ABSTRACT FROM AUTHOR]

We report a 3-D-stackable 1S1R passive cross-point resistive random access memory (RRAM). The sneak (leakage) current challenge in the cross-point RRAM integration has been overcome utilizing a field-assisted superlinear threshold selector. The selector offers high selectivity of >10^7 , sharp switching slope of < 5 mV/decade, ability to tune the threshold voltage, stable operation at 125 °C, and endurance of >10^{11} . Furthermore, we demonstrate 1S1R integration in which the selector-subthreshold current is <10 pA while offering >10^2 memory ON/OFF ratio and >10^6 selectivity during cycling. Combined with self-current-controlled RRAM, the 1S1R enables high-density and high-performance memory applications. [ABSTRACT FROM AUTHOR]

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/ $n$ architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

Endurance reliability at the array level of resistive random access memories (RRAMs) is addressed. Both oxide based RAM and conductive bridge RAM stacks are extensively characterized, presenting various measurements over resistive layers, memory stacks, and programming conditions. These measurement results allow to extract the maximum number of cycles before breakdown $\text {N}_{c\,\text {max}}$. It is found that this quantity follows a log-normal law. According to this first significant result, the impact of SET and RESET conditions on $\text {N}_{c\,\text {max}}$ statistics is studied. Using tailored ramp voltage stress (RVS) measurements, the minimum RRAM switching voltage is extracted along the endurance cycles and then correlated with the memory degradation. To explain and better understand all these experimental results, a stochastic model based on defect generation in a constriction zone of the resistive layer during cycling is proposed. After exploration of the size, geometry, and shape of such constriction zone, as well as different probability laws governing breakdown, modeled $\text {N}_{c\,\text {max}}$ distributions fitting the experimental ones are successfully generated and deeper explanations about the origin of the maximum number of cycles variability are inferred. [ABSTRACT FROM AUTHOR]

A bipolar, highly nonlinear n-p-n selector is coupled in series with resistive switching memory device to suppress the sneak path current. The memory characteristics are measured for the crossbar array fabricated on a flexible polyethylene terephthalate substrate. Dominant conduction mechanism is the Zener tunneling to obtain the high nonlinearity in the selector device. This phenomenon validates the ${I}$ – ${V}$ characteristics which are temperature dependent, which leads to decrease in the turn-on voltage of the device as the temperature increases. The proposed one bipolar selector-one resistor device demonstrates better memory characteristics with the high nonlinearity ($\sim 10^{\textsf {3}}$), observable memory window of about one order, excellent ac endurance ($10^{\textsf {7}}$) cycles, fast switching speed (60 ns), and stable retention ($10^{\textsf {4}}$ s) at 100 °C. The results show the substantial potential of the proposed one selector-one resistor structure in suppressing the leakage current, making it attractive for future high-density flexible crossbar memory array. [ABSTRACT FROM AUTHOR]

Physics-based compact models for redox-based resistive switching memory (ReRAM) devices are used to increase the physical understanding of the complex switching process as well as to allow for accurate circuit simulations. This includes that models have to cover devices showing bipolar switching (BS) and complementary switching (CS). In contrast to BS devices, which store the information in (at least) one high and one low resistance state, CS devices use (at least) two high resistance states. Applications of CS devices range from passive crossbar arrays to novel logic-in-memory concepts. The coexistence of CS and BS modes in one device has been shown experimentally. Here, a physics-based compact model describing BS and CS consistently is presented. Besides modeling CS devices, the model improves the description of BS as it allows to reproduce and explain anomalies in the BS RESET process. The model includes ion drift and diffusion along the filament. The influence of different parameters on the drift–diffusion balance is discussed. [ABSTRACT FROM AUTHOR]

Introducing a threshold switching selector in a resistive random access memory (RRAM) is essential for implementing a crossbar array that accurately accelerates neuromorphic computations. But, at an expense, a read voltage (${V}_{\text {read}}$) to be used for inference tasks is inevitably boosted. Therefore, this brief shows the effect of the enlarged ${V}_{\text {read}}$ on the stability of conductance states of the RRAM relevant to the inference robustness. The multiple conductance states of the analog RRAM achieved by a SPICE simulation are stable under consecutive 106 cycles of nominal ${V}_{\text {read}}$. However, each state of the one selector and one RRAM begins to be disturbed at ~104 cycles due to the boosted ${V}_{\text {read}}$. More importantly, when a certain state exceeds to the next state due to the accumulated ${V}_{\text {read}}$ stress, a classification accuracy of the neural network is significantly degraded. We, thus, introduce a two-step read scheme that separates the roles of turning on the selector and reading the states. As the selector is turned on rapidly with an additional large pulse, the following ${V}_{\text {read}}$ can be lowered. As a result, the read disturbance is minimized, and the optimized two-step pulse scheme allows 106 MNIST images to be recognized with >95% accuracy in the neural network. [ABSTRACT FROM AUTHOR]

The effects of vanadium doping on resistive switching (RS) characteristics and mechanisms of RF-sputtered SrZrO3 (SZO)-based thin films are investigated in this paper. The physical and electrical properties of SZO-based thin films are modulated by vanadium doping due to the Zr4+ ion replaced by V5+, further affecting the RS parameters of SZO-based thin films. The conduction mechanisms of SZO-based thin films are dominated by ohmic conduction (hoping conduction) and Frenkel--Poole emission for the low resistance state (LRS) and the high resistance state (HRS), respectively. The turn-on process might be attributed to the formation of conducting filaments consisting of oxygen vacancies with the effective barrier height (φB,eff) in the range of 0.10-0.13 eV, whereas the turn-off process might result from thermally assisted oxidation of oxygen vacancies by the Joule heating effect. Furthermore, the introduction of the high valence cation (V5+) in a Zr4+ site of SZO crystalline structure can suppress the formation of oxygen vacancies due to the charge neutrality restriction. Such suppression leads to the changes in the forming voltage, turn-on voltage, HRS resistance, dielectric constant, and φB,eff with vanadium doping concentration up to 0.2 mol%, which is within the solid solubility limit based on our measured lattice constants and Vegard's law. [ABSTRACT FROM AUTHOR]

To combat the large variability problem in resistive random access memory, current compliance elements are commonly used to limit the in-rush current during the forming operation. Regardless of the compliance element (1R-1R or 1T-1R), some degree of current overshoot is unavoidable. The peak value of the overshoot current is often used as a predictive metric of the filament characteristics and is linked to the parasitic capacitance of the test structure. The reported detrimental effects of higher parasitic capacitance seem to support this concept. However, this understanding is inconsistent with the recent successes of compliance-free ultrashort pulse forming which guarantees a maximum peak overshoot current. We use detailed circuit analysis and experimental measurements of 1R-1R and 1T-1R structures to show that the peak overshoot is independent of the parasitic capacitance while the overshoot duration is strongly dependent on the parasitic capacitance. Forming control can be achieved, in ultrashort pulse forming, since the overshoot duration is always less than the applied pulse duration. The demonstrated success of ultrashort pulse forming becomes easier to reconcile after identifying the importance of overshoot duration. [ABSTRACT FROM AUTHOR]

We study the heat transport in filamentary resistive random access memory nanosized devices by comparing the accurate results of COMSOL Multiphysics modeling with simplified analytical models for two complementary mechanisms: one neglecting the radial heat transfer from the filament to the insulating host, while the other describing the radial transport through the dielectric in the absence of the filament heat transfer. For the former, we find that the earlier assumed simplification of the electrodes being ideal heat conductors is insufficient; a more adequate approximation is derived where the heat transport is determined by the adjacent proximities of the filament tips in the electrodes. We find that both complementary mechanisms overestimate the maximum temperature yet offering acceptable results. However, the two in parallel provide a better analytical approximation. In addition, we show that the Wiedemann–Franz–Lorenz law helps the analysis when the Lorenz parameter is chosen from the actual data. We present an approximate relation between device SET voltage and SET temperature possessing a high degree of universality and predicting that filament materials with low Lorenz numbers can be good candidates for the future low set voltage devices. [ABSTRACT FROM PUBLISHER]

The impact of the dielectric thickness, forming polarity, and current compliance on the self-rectifying current–voltage ( I – V ) characteristics of Ni/HfO2/n+-Si resistive random access memory (RRAM) devices was investigated. The obtained results indicate that these three aspects not only play a role in the postforming currents but also affect the switching properties of the devices. In the case of 5-nm-thick oxide devices, a self-rectifying ratio of about three orders or magnitude is observed after substrate injection forming (SIF) with current compliance below 500 $\mu$ A. However, similar devices subjected to gate injection forming (GIF) do not exhibit such rectifying feature. This distinctive behavior for SIF is ascribed to the formation of a Schottky-like contact in between the Ni-based conducting filament and the semiconductor electrode. For 20-nm-thick oxide devices, the forming voltage under GIF and the subsequent dielectric degradation are higher than for thinner oxide layers, resulting in a less resistive state, and a negligible role of the referred Schottky barrier. The effect of the temperature on the diffusion of the Ni ions that form the conducting path is also discussed. [ABSTRACT FROM PUBLISHER]

Filamentary conduction paths through insulating solid electrolytes is a widely accepted theory describing the conductionphenomenon in resistive random access memories (RRAMs). In this work, the relationship between filamentary conduction and multilevel resistive states obtained as a result of V\text {STOP} during the RESET process has been analyzed in detail to understand the underlying physics of resistive switching phenomenon. Subsequently, a multifilamentary conduction mechanism has been proposed and a “3-D multifilamentary rupturemodel” has been developed in a transition metal oxide-based RRAM. Four different resistance states have been achieved by using three conduction filaments and their subsequent rupture, thus realizing the multiple resistance levels. By varying V\text {STOP} , it has also been verified that the states thus obtained were because of the direct consequence of the conduction filaments. [ABSTRACT FROM PUBLISHER]

A new two-transistor logic resistive random-access memory (RRAM) cell with a 16-nm standard FinFET CMOS logic platform that is fully compatible with the CMOS process is proposed and demonstrated in a 1-kb FinFET dielectric RRAM (FIND RRAM) array. The new 16-nm FIND RRAM comprises two logic standard FinFET transistors with a HfO2-based composite resistive gate dielectric film as the storage node in a cell. The set and reset characteristics of the FIND RRAM are largely improved by the locally enhanced field at fin corners, which results in low set voltage and low reset current in array operations. Due to adoption of a FinFET CMOS logic process without any additional masks or processing steps, FIND RRAM can be scaled aggressively with a cell size of 288~\text nm \times 265 nm. Low-voltage operation, excellent reliability, and stable low-resistance state/high-resistance state window are realized with the set and reset procedures based on the incremental step pulse programming algorithm, making FIND RRAM a promising embedded nonvolatile memory in the FinFET era. [ABSTRACT FROM AUTHOR]