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In this paper, a multiple-ring-modulated junction termination extension (MRM-JTE) technology for large-area silicon carbide PiN rectifier rated at 4500 V is proposed and experimentally investigated using a standard two-zone JTE (TZ-JTE) process without extra process steps or masks. Multiple modulation rings embedded inside JTE region, which is similar to varied lateral doping technology widely used in silicon devices, form a gradual decrease of effective charges in the termination region. MRM combines the advantages of two termination techniques, namely, ring-assisted JTE and space-modulated JTE, to enlarge the optimum JTE-dose window with high reverse blocking voltage in comparison with conventional TZ-JTE. A breakdown voltage of 4940 V at a leakage current of 1 μA is achieved from fabricated MRM-JTE rectifiers with a 36-μm-thick N- epilayer doped to 1.8 × 1015 cm-3, which is 92% of the ideal parallel-plane value. A forward current of 50 A has been measured at a forward voltage drop of 3.9 V for devices with an active anode area of 9.2 mm2, corresponding to low differential on-resistance of 1.8 mQ · cm2. The simulation and experimental results show that the proposed device exhibits approximately 2 times JTE dose tolerance window improvement with respect to the breakdown voltage of 4500 V. [ABSTRACT FROM AUTHOR]

A closed-form charge control model (CCM) for threshold voltage (Vth) of single-heterojunction (AlGaN/GaN) devices is developed. The CCM reveals the mechanisms of how the space charges across the barrier of a heterojunction deplete or enhance 2-D electron gas. The Vth of both depletion- and enhancement-mode heterostructure field-effect transistors may be calculated through this model. Considering the strained and relaxed states, and surface states, the calculated results for Vth are in good agreement with simulation results. The generalized form for CCM may have wide applications for theoretical-based design for Vth of AlGaN/GaN devices. [ABSTRACT FROM AUTHOR]

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field E1 to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon εT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/µm at tS = 0.1 µm. Expressions for E1 and VB,V are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an E1 value of 300 V/µm has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF. [ABSTRACT FROM AUTHOR]

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias Vbg, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). Vbg only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 V/ µm for the buried oxide in the conventional SOI to 457 V//µm at Vbg = 0 V, leading to a high BV in CBL SOI. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO. [ABSTRACT FROM AUTHOR]

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin—film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBT1) or electron injection (EI) is observed under — Vg or — Vd only stress, respectively, no typical hot carrier (HC) degradation can be identified under high —Vd stress combined with either low or high —Vg stress. Instead, mixed NBTI and EI degradation is observed under combined low — Vg, and — Vd stresses; and combined degradation of NBTI and HC occurs under high —Vd and moderate —Vg stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs' degradation. [ABSTRACT FROM AUTHOR]

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of EI > 700 V/μm is obtained by the simulation on a 2-μm-thick SOI layer over 2-μm-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices. [ABSTRACT FROM AUTHOR]

We studied electrical characteristics of p-channel polycrystalline silicon thin-film transistors (TFT) fabricated by solution-based metal-induced crystallization (SMIC). In particular, the effect of annealing conditions was systematically investigated. The current-voltage characteristics show that the performance of TFTs was dominated by the SMIC process rather than the annealing temperature up to 630 °C. All the devices exhibited good uniformity after annealing. The effects of gate stress and self-heating stress were also studied. The device performance was not affected by both stresses for all devices, p-channel SMIC poly-Si TFT has high performance, good uniformity, and satisfactory reliability with a process temperature < 600 °C. [ABSTRACT FROM AUTHOR]