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Many methods have been proposed for the experimental determination of the collector resistance in bipolar junction transistors and HBTs. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs with a large variety of device sizes fabricated in different technologies and generations, including high-speed and high-voltage transistors. First, the accuracy of those methods, which are based on an extraction from single-transistor characteristics, is evaluated from simulated data using a sophisticated compact model and, where applicable, also device simulation. This approach allows the origin of observed inaccuracies or failures of certain methods to be identified. Second, the test structure-based methods are reviewed, and third, all methods were applied to experimental data. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, a device size, and an operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM AUTHOR]

In this paper, we propose a physics-based compact model of the pinned photodiode (PPD) combined with the transfer gate. A set of analytical expressions is derived for the 2-D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation, and the full-depletion approximation to obtain the charge transfer current. The proposed physics-based model is fully validated with technology computer-aided design simulations, i.e., stationary and optoelectrical simulations. The development of such a compact model for PPD represents an essential step toward the design, simulation, and optimization of PPD-based pixels in CMOS image sensors. [ABSTRACT FROM AUTHOR]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters. [ABSTRACT FROM AUTHOR]

Zinc oxide thin-film transistors (TFTs) with different device geometries and source/drain (S/D) contact metallizations are investigated. To facilitate the analysis, the channel and contact regions in top-gated staggered and drain-offset TFTs employing various permutations of ruthenium (Ru) and gold (Au) bottom electrodes are quantified with a TFT device model. The staggered TFT structure employs identical geometric overlaps between the gate-and-S/D electrodes; whereas the drain-offset TFT structure replaces the gate-to-drain overlap with a geometric gap in the channel. First, the experimental TFT current–voltage (${I}$ – ${V}$) characteristics are disentangled into the intrinsic channel and contact components by the transmission line method. The contact and channel behaviors are then individually modeled using a universal transistor compact model. From evaluating the model parameters, the diverse device characteristics observed in this paper are attributed to the Au electrode’s electron doping effect altering the properties of both the TFT’s contact and channel regions. [ABSTRACT FROM AUTHOR]

The base series resistance is a very important parameter for bipolar transistors. In this paper, methods for its determination from tetrode structures are analyzed and quantitatively evaluated in terms of their accuracy and suitability for advanced SiGe HBTs. The accuracy of the methods is evaluated based on 2-D device simulation, thus allowing to clearly detect and explain the causes for observed inaccuracies or failures of a method. The methods are then applied to experimental data. It is shown that one of the methods yields reliable and accurate results over a wide bias range, while the other two are limited either in accuracy or to VCE = 0 V. [ABSTRACT FROM AUTHOR]

For the experimental determination of the emitter resistance of bipolar junction transistors and HBTs, many methods exist in the literature, which yield quite different results though. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations, including different device types (i.e., high-speed and high-voltage transistors). First, the accuracy of the methods is evaluated based on simulated data using a compact model. Explanations for causes of observed inaccuracy or failure are given and discussed. Second, suitable methods are applied to experimental data. In both cases, the results are compared for a large variety of device sizes. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, device size, and operating range; as well as its requirements in terms of equipment and extraction effort. A guideline for extracting the emitter resistance is also given. [ABSTRACT FROM AUTHOR]

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation. [ABSTRACT FROM PUBLISHER]

This paper presents a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based and does not introduce any empirical parameter. The central concept is based on the linear approximation of the channel charge density with respect to the surface potential, leading to explicit and continuous expressions for charges and current in all the regions of operation, including subthreshold. In addition, an effective circuit design methodology based on the pinchoff surface potential, the pinchoff voltage and the key concept of inversion coefficient (IC) is proposed, likewise for silicon MOSFET circuits. [ABSTRACT FROM AUTHOR]

This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter. [ABSTRACT FROM AUTHOR]

This paper describes a robust, modular, and physics-based circuit framework to model the conventional and emerging magnetic tunnel junction (MTJ) devices. Magnetization dynamics are described by the stochastic Landau–Lifshitz–Gilbert (sLLG) equation whose results are rigorously benchmarked with a Fokker–Planck equation description of the magnet dynamics. We then show how sLLG is coupled to the transport equations of MTJ-based devices in a unified circuit platform. Step by step, we illustrate how the physics-based MTJ model can be extended to include different spintronics phenomena, including spin-transfer torque, voltage-controlled magnetic anisotropy (VCMA), and spin–orbit torque phenomena by the experimentally benchmarked examples. To demonstrate how our approach can be used in the exploration of novel MTJ-based devices, we present a recently proposed MEMS resonator-driven spin-torque nano-oscillator (STNO) that can reduce the phase noise of STNOs. We briefly elaborate on the use of our framework beyond conventional devices. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices. [ABSTRACT FROM AUTHOR]

This paper proposes a novel type of compact circuit model for silicon germanium (SiGe) heterojunction phototransistor (HPT) that is justified from the distributed nature of both its electrical and optical behaviors. The proposed model is based on a modified Ebers–Model structure and contains 28 different parameters. It is independent of the nature of the base bias (current or voltage), as opposed to existing models. The method to identify that the architecture of the model is original as it makes use of a drift–diffusion numerical simulation of a SiGe HPT adjusted to experimental data. A good fit of the model both in amplitude and phase is obtained through the nine optomicrowave S-parameters. [ABSTRACT FROM PUBLISHER]

Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages. [ABSTRACT FROM AUTHOR]

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses 3n$ extra nodes in Verilog-A implementation whereas it is 2n^{2}-n for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit. [ABSTRACT FROM AUTHOR]

As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs. [ABSTRACT FROM AUTHOR]

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate. [ABSTRACT FROM AUTHOR]

Symmetric double-gate ferroelectric FETs (SDG-FeFETs) have better short-channel electrical behavior and hold promise in reducing the subthreshold swing below the classical Boltzmann’s limit. Surface potential and drain current models for SDG-FeFETs have already been published in the literature. In this paper, we derive the quasi-static terminal-charge models for these devices, which can be seamlessly integrated into standard circuit simulators using the Verilog-A interface. The terminal-charge models proposed are shown to match very well with exact numerical integration of Ward–Dutton terminal-charge integrals, for all bias conditions. Core compact model for the SDG-FeFET is implemented in a SPICE circuit simulator, and the simulation of different circuits built using SDG-FeFET transistors shows improvement in their switching behavior. [ABSTRACT FROM PUBLISHER]

Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results. [ABSTRACT FROM AUTHOR]

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potential by using PSP metal-oxide-semiconductor description. Cell-to-cell coupling, Fowler–Nordheim tunneling, and new leakage current formulas have been implemented on Verilog-A compact model. The channel potential calculation of the PSP model enables accurate modeling of channel coupling and leakage currents which are associated with the boosted channel. In addition, the model parameter extraction procedure through 3-D technology computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of sub-20-nm nand cells. [ABSTRACT FROM AUTHOR]

A comprehensive study and comparison of IV and III–V Schottky barrier (SB) double-gate MOSFETs using a universal analytical model and Synopsys TCAD Sentaurus is presented. Various impacts on the device performance have been identified, e.g., the SB height, the bandgap, the material-dependent carrier masses, and density-of-states affecting the ambipolar behavior and ON-current. The performance is analyzed with respect to the most important physical parameters and their impact on the device figure of merit. Ambipolar behavior is an important factor and must be carefully considered in the device design to aim a high I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} ratio and comparable subthreshold slope to conventional MOSFET devices to benefit from the SB. This paper shows that the above listed parameters determine the bottleneck on the device performance. [ABSTRACT FROM PUBLISHER]

Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. [ABSTRACT FROM PUBLISHER]

An equivalent circuit model of monolithic 3-D inverter (M3INV) considering the electrical coupling between the stacked metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. We conduct the parameter extraction with technology computer-aided design (TCAD) simulations, where LETI-UTSOI model in HSPICE is used for the bottom PFET and the top NFETs. Their parameters are extracted by fitting their current–voltage (for dc analysis) and capacitance–voltage (for transient ac analysis) characteristics. The parameters extracted from the LETI-UTSOI model contain the electrical coupling at the gate of the bottom MOSFET. In order to extract external capacitances such as monolithic intertier via (MIV)-to-MIV and MIV-to-contact in M3INV, we use two structures, the first that contains MIVs and metal lines and the second that does not. We observe that the dc and transient characteristics of M3INVs built using our extracted parameters match the TCAD mixed-mode circuit simulation results considerably well. Finally, we build and analyze ring oscillators using our M3INV to demonstrate the coupling impact on power and performance. [ABSTRACT FROM AUTHOR]

The carrier transport in advanced SiGe heterojunction bipolar transistor (HBT) process technologies exhibits bandgap-related transport effects that not only impact the transconductance and output conductance characteristics, but are also difficult to describe accurately by compact models. This paper addresses the modeling of bandgap-related effects in the collector current by formulating an improved version of a generalized integral charge-control relation (GICCR). As a result, the experimentally observed degradation of the transconductance at low and medium current injection, which is a strong function of the Ge grading, as well as the output conductance are described by simple bias- and temperature-dependent formulations of the GICCR weight factors. The derived formulations fit seamlessly into the compact model HICUM/L2. The extended model shows excellent agreement over a wide bias and temperature range with the experimental data of a large variety of SiGe HBTs from technologies of different manufacturers, including production and most advanced lab processes. [ABSTRACT FROM AUTHOR]

The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (t^n). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and dynamic voltage scaling (DVS) in real circuit operation. To overcome these barriers, this paper: 1) practically explains the aging statistics due to randomness in number of traps with the log(t) model, accurately predicting the mean and variance shift; 2) proposes cycle-to-cycle model (from the first principles of trapping) to handle aging under multiple supply voltages, predicting the nonmonotonic behavior under DVS; 3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles; and 4) comprehensively validates the new set of aging models with 65-nm statistical silicon data. Compared with previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard banding during the design stage. [ABSTRACT FROM PUBLISHER]

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface. [ABSTRACT FROM PUBLISHER]

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal–oxide–semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends. [ABSTRACT FROM AUTHOR]

Previous techniques used for solving the 1-D Poisson equation (PE) rigorously for long-channel asymmetric and independent double-gate (IDG) transistors result in potential models that involve multiple intercoupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This paper reports a different rigorous technique for solving the same PE by which one can obtain the potential profile of a generalized IDG transistor that involves a single implicit equation. The proposed Poisson solution is shown to be computationallymore efficient for circuit simulation than the previous solutions. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of band-to-band tunneling (BTBT) mechanisms into the compact model of a conventional carbon nanotube transistor FET featuring a MOSFET-like operation. Appropriate equations enable the calculation of the BTBT current as well as the charge pileup in the channel. To ensure the model accuracy and validate the equation set, the compact model simulation results are methodically compared with nonequilibrium Green function ones. Afterward, the investigations on the BTBT effects with respect to the figures of merits of the transistor and circuit have led to draw the conclusion that their impact is of utmost importance for large-signal analog and digital circuit designs. Neglecting the BTBT phenomena lead to an underestimation of more than 50% of the gate inverter delay and to an underestimation of power consumption of 30%. Finally, tradeoff recommendations between chirality and operating bias voltage are presented. [ABSTRACT FROM AUTHOR]

This paper describes the development of a SPICE equivalent-circuit model of the silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection applications. The framework developed includes the equivalent circuit, models for the various components imbedded in the SCR, and model parameters' extraction. The new model is implemented into the industry standard Cadence SPICE and is verified against transmission line pulsing measured data. [ABSTRACT FROM AUTHOR]

In this paper, a new method of statistical compact model parameter extraction is proposed and described in detail. The method is characterized in that the target of fitting is not the individual transistor, but statistically analyzed results (more specifically, principal components) of measured data. Variations of transistor characteristics can be translated into equivalent variations of compact model parameters by only one fitting step without repeating the parameter extraction procedure multiple times. Since the fitting is based on the response of a compact model to parameters, detailed information of the model is not necessary. The method has been applied to modeling the variations of metal-oxide-semiconductor field-effect transistor current versus voltage characteristics, and its validity has been confirmed. [ABSTRACT FROM AUTHOR]

In this paper, a small-signal MOSFET model is described, which takes the local effects of both velocity saturation and transverse mobility reduction into account. The model is based on the PSP model and is valid for both quasi-static and non- quasi-static (NQS) operations. Recently, it has been found that, in the presence of velocity saturation, the low-frequency capacitances cannot be determined from the Ward-Dutton charge-partitioning scheme.1 By use of the small-signal model developed in this paper, it is demonstrated that, in the presence of velocity saturation, no terminal drain and source charges exist, from which the capacitances can be derived. The small-signal model enables the determination of the correct capacitive behavior in the presence of velocity saturation. Furthermore, it is demonstrated how the small-signal model can be used to determine the number of collocation points needed in the large-signal PSP model. Finally, inclusion of the local variation of mobility reduction due to the vertical electrical fields provides insight into the approach commonly applied in compact modeling, where these fields are replaced by global ones depending on the terminal voltages only. [ABSTRACT FROM AUTHOR]

The Ward-Dutton (WD) partitioning scheme [IEEE Trans. Electron Devices, vol. ED-27, p. 1571, Aug. 1980] is used extensively to develop transient and high-frequency advanced compact models for MOSFET devices. Recently, it has been shown that WD partitioning fails for field-dependent mobility [IEEE Electron Device Lett., vol. 27, p. 674, Aug. 2006] or for laterally asymmetrical doping [IEDM Tech. Dig., p. 751, Dec. 2004], [IEEE Trans. Electron Devices, vol. 53, p. 270, Feb. 2006]. This paper is aimed at presenting a generalization of the partitioning concept. We show that, although it is not possible to guaranty a partitioning scheme for general operation of the MOSFET, it is possible to show the existence of a partitioning scheme for small-signal operation of the device accounting for both field-dependent mobility and lateral asymmetry. Application of this new concept in capacitance evaluation of lateral asymmetric MOSFET considerably simplifies the existing capacitance-evaluation methodology and accounts for any arbitrary field-dependent mobility. It also gives a mean to physically understand the unusual behavior of Cdg in lateral asymmetric MOSFET. We also show how failure of the WD partitioning can affect the present compact-modeling methodologies. [ABSTRACT FROM AUTHOR]

This paper presents a carrier-based approach to develop a compact model for long-channel undoped symmetric double-gate MOSFETs. The formulation starts from a solution of the Poisson's equation that is coupled to the Pao-Sah current formulation to obtain an analytic drain-current model in terms of the carrier concentration. The model provides an analytical expression to describe the dependence of the surface potential, silicon-film centric potential, inversion charge, and the current on the silicon-body thickness and the gate-oxide thickness. The model calculation is verified by comparing results to the 2-D numerical simulations, and good agreement is observed. [ABSTRACT FROM AUTHOR]

A physics-based analytic solution to the surface potential from the accumulation to the strong-inversion region has been derived from the complete MOSFET surface potential equation in this paper without any need for smooth functions or simplification by dropping some second-order related terms, its high accuracy in predicting the surface potential and the transcapacitance under various bias conditions has also been verified by a comparison with the numerical results. The explicit surface-potential solution not only leads to a more clear understanding of MOSFET device physics but also provides a better platform to develop the advanced surface potential-based model for the circuit simulation. [ABSTRACT FROM AUTHOR]

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure—FinFET. [ABSTRACT FROM AUTHOR]

In this paper, we extend our derivation of an analytical model for nanoscale MOSFETs, focusing on the effects of Fermi-Dirac statistics on vertical electrostatics and on carrier transport. We derive a relation between mobility and mean-free path valid under degenerate statistics, and investigate the cases of rectangular and triangular quantum confinement under Fermi-Dirac statistics in the transition from DD to B transport. We derive a simple, physics-based and continuous analytical model that describes double-gate MOSFETs, fully depleted silicon-on-insulator MOSFETs, and bulk MOSFETs in the electric quantum limit in the whole range of transport regimes comprised between DD (device length much larger than mean-free path) and B (device length much mailer than mean-free path). [ABSTRACT FROM AUTHOR]

A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical calculation of interface potentials, valid for all regimes of independent double-gate device operation, is detailed. This analytical computation, which is the heart of Leti-UTSOI2, provides explicit expressions for all quantities required to build dc and ac core models. [ABSTRACT FROM AUTHOR]

A compact model for the current–voltage characteristics of organic thin-film transistors (OTFTs), which includes the effects of the contact regions, is proposed. Different physical and morphological aspects of contacts with organic or other emerging materials such as graphene, semiconducting dichalcogenides such as MoS2, or NW devices are described. The electrical behavior of the contacts is studied in OTFTs, and circuit models that describe them are reviewed. Two trends are observed in the current–voltage curves of the contacts of different OTFTs: linear and nonlinear, and different models are used to explain them. A unified model for the contact region that reproduces both trends and gathers the different physical and structural features of the contacts is developed. It is described by a single parameter and introduced in a generic analytical model for TFTs. The variability in OTFT structures, materials, and fabrication approaches gives rise to a strong variability in the values of the parameters of the model. In this regard, a characterization technique to determine the value of the parameters of the model from experimental data is also developed. Different physical tests are proposed to validate the results of the technique. The procedure is applied to recent experimental data for different pentacene-based transistors. The good agreement between the experimental data and our analytical results provides a way to relate the parameters of the model with the physical or geometrical origin of the contact effects in OTFTs. [ABSTRACT FROM PUBLISHER]

A novel compact lateral double-diffused MOSFET (LDMOS) transistor model is presented in this paper. In contrast to other LDMOS models, the drift region part of this model is developed according to a surface-potential-based description of the drift region underneath the gate oxide. The model gives a complete description for all operation regimes while keeping a relatively simplified analytical expression of the current. A nodal charge model is also included for the time-dependent behavior of devices. The proposed complete LDMOS model is validated by comparison with numerical device simulations and measured data of the actual LDMOS devices. The comparison results demonstrate that the new model gives accurate descriptions for both dc and ac characteristics of LDMOS transistors. [ABSTRACT FROM AUTHOR]

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence. [ABSTRACT FROM PUBLISHER]

Surface-potential-based compact charge models for symmetric double-gate metal–oxide–semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design. [ABSTRACT FROM AUTHOR]

We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations. [ABSTRACT FROM AUTHOR]

This paper presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results ( I–V characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented. [ABSTRACT FROM AUTHOR]

Suspended gate field-effect transistors (SG-FETs) with switching gates are interesting as digital logic switches because of their high Ion/Ioff current ratio and their infinite sub-threshold slope. However, the limits of scalability of the SG-FETs are still unclear. This paper investigates two effects that could limit scaling: the dielectric charging and the dielectric roughness. To do so, a surface-potential-based model for suspended gate transistors with a mechanically switching gate is presented and validated using experimental data. Devices fabricated in a standard complimentary metal-oxide-semiconductor process are used for the model assessment. The model reproduces the effect of a fixed charge and the effect of a nonideal contact of the gate after pull-in. We show that, at the device dimensions required to follow the International Technology Roadmap for Semiconductors, these effects will be critical. [ABSTRACT FROM AUTHOR]