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This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed. [ABSTRACT FROM AUTHOR]

A novel vertical architecture for all-printed organic electrochemical transistors, based on poly(3, 4-ethylenedioxythiophene):poly(styrene sulfonate), realized on flexible substrates, is reported. The transistors are manufactured along both faces of plastic or paper substrates and via connections are realized using laser ablation or simple punch through using a pin. Successful modulation of the electric current that flows between the two sides of the substrate is achieved using electrolyte-gating and electrochemical modulation of the electronic charge transport of the bulk of the transistor channel. In addition to this, the transistors are exhibiting fast switching and high ON/OFF current ratios. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

Many methods have been proposed for the experimental determination of the collector resistance in bipolar junction transistors and HBTs. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs with a large variety of device sizes fabricated in different technologies and generations, including high-speed and high-voltage transistors. First, the accuracy of those methods, which are based on an extraction from single-transistor characteristics, is evaluated from simulated data using a sophisticated compact model and, where applicable, also device simulation. This approach allows the origin of observed inaccuracies or failures of certain methods to be identified. Second, the test structure-based methods are reviewed, and third, all methods were applied to experimental data. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, a device size, and an operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM AUTHOR]

A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events over the static one. Moreover, the superior transient-noise immunity of the proposed clamp over traditional transient ones is essentially revealed in this paper. The proposed clamp is successfully verified in a 65-nm bulk CMOS process. In addition, the design flexibility of the proposed clamp for other processes is also deeply discussed in this paper. [ABSTRACT FROM PUBLISHER]

This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current–gate voltage (${I}_{\text {D}}$ – ${V}_{\text {G}}$) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state $\to $ on-state and the ON-state $\to $ OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the ${I}_{\text {D}}$ – ${V}_{\text {G}}$ curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole–Frenkel region. At the Poole–Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau–Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ~ $10\times $ with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper. [ABSTRACT FROM AUTHOR]

In order to better predict the high-frequency switching operation of transistors in power converters, parasitic elements of these devices such as resistances, inductances, and capacitances must be accurately evaluated. This paper reports on the characterization of a gallium nitride (GaN) packaged power transistor using S-parameters in order to extract the device parasitics. Because the transistor is packaged, a calibration technique is carried out using specific test fixtures designed on FR4 printed circuit board (PCB) in order to get the S-parameters in the transistor plane from the measurement. The proposed method is suitable for a wide range of power devices. In this paper, it is applied to an enhancement-mode GaN high electron mobility transistor (HEMT). The impact of junction temperature on drain and source resistances is also evaluated. According to characterization results, equation-based modeling is proposed for the nonlinear parameters. The extracted parasitic elements are compared with reference values given by the device manufacturer. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for compact modeling of aging and radiation effects for MOS transistors including process variation and environmental influences. This approach can be used in common design flows for analog integrated circuits. Moreover, the aging behavior of whole circuits can be analyzed without the need for abstractions or extrapolation. Only one common physically motivated transistor parameter is used in order to model radiation and degradation mechanisms. [ABSTRACT FROM AUTHOR]

This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold. The mosaic uncooled PIR sensors are composed of several TMOS subpixels, which are electrically connected, either in parallel or in series as well as a combination of both options. These mosaic sensors, which are manufactured by nanofabrication methods, exhibit enhanced performance and robust manufacturing on wafer level. The overall figures of merit of these sensors, which are modeled in this paper, indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things as well as mobile applications. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L\mathrm{ eff}= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f\mathrm {\mathrm {MAX}} , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation. [ABSTRACT FROM AUTHOR]

In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator. [ABSTRACT FROM AUTHOR]

This paper demonstrates the use of doublegate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping (Nd) ≤ 1018 cm-3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm-3). RT of ~2.5 s at 85 °C and ~4.5 s at 27 °C is achieved for gate length (Lg) of 400 nm with Nd = 1017 cm-3 which reduces to ~90ms at 85 °C for Lg = 25 nm. This paper discusses the storage volume (Lg x film thickness for a fixed volume with width of 1 µm) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrödinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

A bond-pad charging protection design for charging-free reference transistor test structures was examined. This paper concludes that truly charging-free reference transistors cannot be realized with the one conventional bond-pad charging protection design of protecting transistor gates only. This, however, can be achieved by simultaneously protecting all terminals of the reference transistors. The simulations, in this paper, reconfirm the earlier important experimental conclusion that placing protection device(s) at transistor gates may inflict severe damage to transistor gate oxides instead of protecting them. The implication of the above suggests that attention may be required in a circuit layout design stage for those transistors which gates begin to connect, at high metal layers, to highly efficient leakage paths, such as protection devices, n-type source/drain diffusion regions, and VSS bus lines, which tend to pull transistor gates to low potentials during a backend integrated-circuit manufacturing process. This paper proposes an optimum bond-pad charging protection design for the truly charging-free reference transistor test structures by considering a minimum usage in a layout space and minimum gate oxide stress in the fuse zap-off process. [ABSTRACT FROM AUTHOR]

Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n+ buried layer (PNBL). The power capability of a transistor can be evaluated by ${P}_{\text {max}}/A$ , which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. ${P}_{\text {max}}$ is dependent on the snapback voltage (${V}_{\text {sb,QS}}$), OFF-state breakdown voltage (${V}_{\text {bd}, \mathrm{\scriptscriptstyle OFF}}$), and maximum current (${I}_{\text {max}}$) in the quasi-saturation regime of an LDMOS transistor. Increase of ${P}_{\text {max}}/A$ by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on ${V}_{\text {sb,QS}}$ and ${P}_{\text {max}}/A$ are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented. [ABSTRACT FROM AUTHOR]

A general equivalent circuit model for the metal/organic semiconductor (OSC)/liquid/metal system is presented. Each circuital element, representative of a physically observable phenomenon associated with the device working principle, is analyzed and discussed. Two case studies of electrochemical impedance spectroscopy of devices featuring NaCl (concentration of 0.1 M) and MilliQ water as liquid are reported, showing that both cases can be considered as a particular case of the general model presented in this paper. Experimental verification of the two practical cases is achieved by performing measurements onto electrodes coated by either an n-type or a p-type OSC deposited by sublimation or drop casting, respectively. The good agreement with the experimental data makes our model a useful tool for the characterization and failure analysis of electronic devices, such as water-gated transistors, electrophysiological interfaces, fuel cells, and others electrochemical systems. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

The application of capacitive deep trench isolation (CDTI) as a shared vertical transfer gate (VTG) in a back-side-illuminated CMOS image sensor pixel is investigated using 3-D device-level simulations. The parasitic capacitance existence between CDTI and deeply buried pinned photodiode (BPD), and also between CDTI and floating diffusion (FD) region, makes the charge transfer process more difficult. In order to design a lag-free pixel and obtain complete charge transfer from BPD to FD, various considerations regarding the device-level design should be taken into account which is discussed in this paper. A CDTI neighboring two pixels can be functionalized as a shared VTG. Using CDTI as shared VTG facilitates pixel miniaturization and can result in more circuit integration at the pixel surface. This paper proposes a ${2}\,\,\mu \text{m} \times {2}\,\,\mu \text{m}$ pixel with CDTI as shared VTG, an equilibrium full-well capacity of 4605 e−, and a complete charge transfer from BPD to FD. [ABSTRACT FROM AUTHOR]

In our earlier work, we presented a percolation theory-based analytical model to estimate FinFET’s VT distribution due to fin edge roughness. The earlier models in the literature were based on minimum fin width, the limitations of which were discussed in detail. In this paper, we advance the percolation theory-based model to capture the variability in all key-device parameters, viz. I \mathrm{\scriptscriptstyle ON} , I \mathrm{\scriptscriptstyle OFF} , subthreshold slope, and VT . The entire distribution of these parameters obtained by the model is presented and compared against stochastic TCAD to demonstrate excellent match. The model reduces rms error in $\mu $ of various parameters by 5%–60%, and 20%–50% in $\sigma $ with respect to the minimum fin width-based models present in the literature. [ABSTRACT FROM PUBLISHER]

This paper reports ultralow contact resistivities ( \rho c) achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; \rho c achieved was \sim 2.9\times 10^-9~\Omega \cdot cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; \rho c achieved was \sim 1.7\times 10^-9~\Omega \cdot cm2. When \rho c reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates. [ABSTRACT FROM PUBLISHER]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 °C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 °C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 °C are 0.79 and 1.01 LSB, respectively, while at 500 °C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 °C and 500 °C, respectively. [ABSTRACT FROM AUTHOR]

This paper reveals an early quasi-saturation (QS) effect attributed to the geometrical parameters in shallow trench isolation-type drain-extended MOS (STI-DeMOS) transistors in advanced CMOS technologies. The quasi-saturation effect leads to serious gm reduction in STI-DeMOS. This paper investigates the nonlinear resistive behavior of the drain-extended region and its impact on the particular behavior of the STI-DeMOS transistor. In difference to vertical DMOS or lateral DMOS structures, STI-DeMOS exhibits three distinct regions of the drain extension. A complete understanding of the physics in these regions and their impact on the QS behavior are developed in this paper. An optimization strategy is shown for an improved gm device in a state-of-the-art 28-nm CMOS technology node. [ABSTRACT FROM AUTHOR]

This paper presents functional high-temperature analog circuits in silicon carbide bipolar technology. The circuits will collectively form the analog signal conditioning block for a wireless telemetry system in an extreme environment (above 400°C). The signal conditioning block is composed of a low dc gain operational amplifier, a negative voltage charge pump (CP), an RC oscillator, and a voltage regulator. The circuits are tested up to 450°C. The measured open-loop gain for the amplifier at 450°C is 30 dB. The regulator provides approximately 9-V output at 450°C for a fixed load current of up to 18 mA and an applied reference of 4.5 V. The negative voltage CP requires an oscillating signal at its input, which is provided by the RC cross-coupled oscillator. The CP provides about −5 V at 450°C. [ABSTRACT FROM AUTHOR]

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters. [ABSTRACT FROM AUTHOR]

This paper presents the study of the chopper-stabilized magnetic field effect transistor (CHOPFET), a high-resolution silicon magnetic transducer. After a full description of its structure and operating principle, a 3-D multiphysics model is proposed. This model combines the electrical model of conventional silicon electronic devices (i.e., transistors) and the magnetic model in order to obtain accurate transduction effect prediction. Experimental results collected from a set of CHOPFET transducers fabricated in AMS $0.35~\mu \text{m}$ standard CMOS technology effortlessly match the simulations performed on the same process. Analysis and discussions reveal one key result: when the CHOPFET is appropriately biased, its channel current, ${I}_{\text {DS}}$ , can be lowered without magnetic sensitivity loss, i.e., the CHOPFET can achieve high-resolution performance even when operated in a low-power mode. [ABSTRACT FROM AUTHOR]

This paper reports the process integration and fabrication characteristics of a vertical thin poly-Si channel (VTPC) transfer gate (TG) pixel, which is one of the candidates for future 3-D CMOS image sensor (CIS) applications. The proposed process integration can effectively suppress grain boundary formation at the interface between the photodiode and the poly-Si channel by solid phase epitaxial growth (SPEG) mechanism. Furthermore, dopant diffusion characteristics for source–drain junction formation in poly-Si substrates are investigated using secondary ion mass spectroscopy (SIMS) depth profiles under various process conditions. In addition, combining SIMS results with ${I}_{d}$ – ${V}_{g}$ curve and scanning spreading resistance microscopy measurements, we explained the discrepancy in diffusion characteristics between the bulk and the thin-film poly-Si. Finally, by using optimized SPEG conditions and adopting the proposed VTPC-TG pixel structures in a commercial 5-Mpixel CIS image sensor product, we successfully verified the improvement in image quality. [ABSTRACT FROM AUTHOR]

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure. [ABSTRACT FROM AUTHOR]

The base series resistance is a very important parameter for bipolar transistors. In this paper, methods for its determination from tetrode structures are analyzed and quantitatively evaluated in terms of their accuracy and suitability for advanced SiGe HBTs. The accuracy of the methods is evaluated based on 2-D device simulation, thus allowing to clearly detect and explain the causes for observed inaccuracies or failures of a method. The methods are then applied to experimental data. It is shown that one of the methods yields reliable and accurate results over a wide bias range, while the other two are limited either in accuracy or to VCE = 0 V. [ABSTRACT FROM AUTHOR]

In this paper, we propose and simulate a new structure of a line tunnel FET employing gate over source--channel overlap pockets (GO-SCOPs). The SCOPs create vertical tunneling path within the source and the channel extension that lead to a faster thinning of the lateral tunneling barrier between the source and channel regions. As a result, an inverted C-shaped tunnel junction is formed providing both lateral tunneling and vertical tunneling. A calibrated 2-D simulation study shows that an ON-current improvement by one order is achieved in comparison with the gate over source only (GoSo) tunnel field-effect transistors with pockets. Further, the OFF-state leakage and average subthreshold swing are reduced by 44% and 21%, respectively, with an improved parasitic capacitance. This has improved the cutoff frequency from 8.3 MHz in GoSo with pockets structure to 1.19 GHz in the proposed GO-SCOP structure. Furthermore, by employing Ge SCOPs, the ON current is boosted by 4 orders of magnitude, maintaining leakage at ~0.25 fA/µm, giving ION/ IOFF > 109, and a much improved average subthreshold swing of ~48 mV/dec at VGS = 2 V, VDS = 0.5 V. [ABSTRACT FROM AUTHOR]

Although oxide thin-film transistors (TFTs) have drawn great interests in flexible displays, a key obstacle is the requirement of high-temperature annealing to realized mobility >10 cm²/V · s. In this paper, a fully room-temperature strategy, involving the deposition of ~10 nm In-Ga-Zn-O (IGZO) channel layer and ~4 nmAl2O3 passivation layer, is introduced. The as-prepared flexible TFT on polymide substrate exhibits a saturation mobility of 15.3 cm²/V · s, Vth of 3.08 V, and on/off current ratio of 2.3 x 107. Thickness-dependent analysis indicates that the interface between Al2O3 and IGZO is composed of negative O-rich layer, which impel the energy band bending inside the IGZO layers and release of electrons from traps. This paper opens up a route to achieve fully room-temperature fabrication of high-performance flexible TFT. [ABSTRACT FROM AUTHOR]

This paper utilizes electrical analyses and a study of physical mechanisms to investigate metal gate structure-dependent performance in amorphous InGaZnO (a-IGZO) thin-film transistors. The effects of different shielding areas between the IGZO layer and metal gate are investigated. In devices with shorter metal gate lengths, an abnormal rise in capacitanceat the off-state in capacitance--voltage ( C-V) characteristic curves can be observed. This can be attributed to the stronger electric field induced by the edge of themetal gate under bias sweepwhen themetal gate length is shorter than the IGZO layer length. Light illumination measurements indicate a negative shift in threshold voltage and an increase in subthreshold-leakage current regardless of relative metal gate length. Moreover, negative threshold voltage shift becomes more severe with a more obvious hump in C-V characteristic curves under backlight illumination of a shorter width device, a phenomenon which has been verified by simulation. [ABSTRACT FROM AUTHOR]

This paper presents an optimized normally off GaN-based metal--insulator--semiconductor field-effect transistor (MISFET) with an electrode-connectedp-i-n diode inserted in the buffer layer, i.e., EC-PINMISFET, and in which the substrate is removed for the suppression of the vertical leakage current. We provide the simulation results of the proposed MISFET. The EC-PIN MISFET with Lgd = 6 µm presents an excellent breakdown voltage of 1400 V, which attributes to the improvement of electric field distribution in the gate--drain region and the suppression of leakage current by EC-PIN. In addition, the specific on resistance of 0.64 mΩ·cm² and Baliga's figure of merit of 3.08 GW·cm-2 are achieved in the optimized EC-PIN MISFET, indicating a good tradeoff between the specific on resistance and breakdown voltage. [ABSTRACT FROM AUTHOR]

This paper addresses a wearable piezoelectric energy harvester that combines a PVDF piezoelectric charge generator with an a-Si:H dual-gate thin-film transistor as a rectifier. An analytical model and equivalent circuit elaborate their working principle and device physics. A preliminary experimental study proves the device concept and demonstrates that such a harvester is capable of generating microwatt-range power with a simple 90° finger bending action. Coupled with low-cost and largearea fabrication processes, a pixelated energy-harvesting array can be potentially achievable, making it a promising alternative to energy sources for wearable electronics. [ABSTRACT FROM AUTHOR]

Transconductance efficiency ( gm/{I}D ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of gm/{I}D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the gm/{I}D -based design methodologies usage in DG FDSOI transistors sizing. [ABSTRACT FROM AUTHOR]

Transport properties of realistic phosphorene nanoribbons (PNRs) with edge defects are studied by using statistical atomistic quantum transport simulations. Regarding the impact of nanoribbon width downscaling and increasing of edge defect percentage, we show that PNRs exhibit qualitatively similar behavior of the ON- and OFF-state conductance, and of the ON–OFF conductance ratio as graphene nanoribbons (GNRs). However, we demonstrate that PNRs are superior to GNRs in terms of the absolute values of the conductance parameters, and that PNRs are much more immune to edge defects than their graphene counterparts. This paper identifies PNRs as a more promising channel material than GNRs for the extremely scaled postsilicon transistor technology. [ABSTRACT FROM PUBLISHER]

The tunable negative differential resistance (NDR) characteristics of metal-insulator-semiconductor- insulator-metal (MISIM) tunnel diodes (TDs) structure with thin oxide were observed by biasing the substrate simultaneously with one of the TDs under designed voltage drops (AV). An inner circular electrode TD surrounded by a ring-shape electrode TD gate pattern was adopted. The NDR region can be adjusted by varying the AV between the inner TD and the body. Not only the peak-to-valley current ratio (PVCR) but also the voltage range where NDR occurs can be controlled. It is supposed that the injected electrons and the inversion charges increase and decrease with negative bias, respectively, for the MIS(p) TD and play an important role in this observation. Meanwhile, the asymmetry of inner gate and ring gate enhances the coupling efficiency at reverse bias region. In this paper, the PVCR can be tuned to more than two orders and the voltage of the NDR region can be shifted to larger than 1 V. The tunable NDR characteristic of MISIM provides a possible application of MIS TD. [ABSTRACT FROM AUTHOR]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SISP on the threshold voltage, the boundary conditions at the silicon–buried oxide interface have been modified accounting for the potential difference between substrate surface and substrate bulk. Model results are compared with the simulation results obtained using 3-D visual TCAD device simulator from Cogenda. [ABSTRACT FROM PUBLISHER]

This paper investigated the applicability of thermal annealing to be used for the color conversion of organic light-emitting diodes (OLEDs) made of a blend of light-emitting polyfluorenes. Blue-light-emitting polyfluorene poly(9,9-di-n-octylfluorenyl-2,7-diyl) (PFO) was used as the host material and green-light-emitting polyfluorene poly[(9,9-di-n-octylfluorenyl-2,7-diyl)-alt-(benzo[2,1,3]thiadiazol-4,8-diyl)] (F8BT) as the dopant material. Annealing treatment was conducted at the temperatures of 150 °C and 270 °C, before top contact deposition. Both nonannealed OLEDs and those annealed at 270 °C showed green color emission, implying that emission was taking place via the dopant material F8BT. Instead, the light emission color of the OLEDs annealed at 150 °C was shifted to white upon a rise of a blue spectral component. The origin of the blue light emission was attributed to PFO and indicated considerable phase separation between PFO and F8BT. This paper showed that thermal annealing can be applied to modify the light emission color of polyfluorene-blend OLEDs. [ABSTRACT FROM PUBLISHER]