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Ultrathin nitride/oxide (N/O) gate stacks with equivalent oxide thicknesses (EOT) of 1.6 nm, prepared by rapid thermal chemical vapor deposition (RTCVD) and two-step NH[subscript 3]/N[subscript 2] O post-deposition treatment, for dual-gate complementary metal-oxide semiconductor (CMOS), are investigated experimentally. And the electrical properties of the N/O stacks are optimized with bottom-oxide materials and post-deposition treatment.

Optimized indium halo structures and arsenic implantations are described, for high-performance sub-0.1 micromillimeter-channel-length complementary metal-oxide semiconductor field-effect transistors (CMOSFET). degradation of the performance because of interstitial Si resulting from In-halo implantation can be cut down using thermal annealing at medium temperatures for longer periods of time.

Differences are found between doping characteristics of BF[superscript +, subscript 2] implanted (100) and (111) silicon. High dose BF[superscript +, subscript 2] implants always produce higher sheet resistance in (111) silicon.

Maximum post-process annealing temperature for standard 0.35 mu m CMOS wafers having aluminium based interconnections and tungsten plugs, is studied.

A study was conducted to analyze the wet oxide thickness dependence of nitrogen concentration and the effects of nitrogen distribution profiles on charge trapping and TDDB behavior. Metal oxide semiconductor capacitors and transistors were prepared on p-type (100) orientation silicon substrates. Results indicated that improvements in the reliability of the gate oxide correlate with a nitrided wet oxide in N2O ambient.

A study was conducted to describe the combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in metal-oxide semiconductor field-effect transistors (MOSFETs). Up to 32x improvement in device lifetime was observed in complementary metal oxide semiconductor devices annealed in a 10% deuterium/90% nitrogen ambient. The greatest improvement was seen after silicide anneal, with subsequent thermal processing degrading the effect.

The post-metallization annealing effect on the quality of thermal SiO(sub 2) on p-type 4H- and 6H-SiC was systematically investigated. To this end, the total effective oxide charge and interface state density were measured using a simultaneous quasi-static high-low frequency capacitance-voltage technique. It was found that total effective oxide charge values close to the detection limit due to the uncertainty in SiC electron affinities and interface state density values below 1 x 10(super 11) cm(super -2)/eV deep in the band gap can be reproducibly derived for both p-type 4H- and 6H-SiC.

The results of electrical properties of in vacuo deposited Ti/TiN/Pt contact metallization on n-type 6H-SiC epilayer as function of impurity between 3.3 x 10 (super 17) negative cc and 1.9 x 10 (super 19) negative cc are reported. With the highly doped sample as exception, the as-deposited contacts are rectifying. Following the annealing of samples at 1000 degrees centigrade between 0.5 and 1 min in argon, only the lesser doped is left rectifying. Superior mechanical stability results from the non-occurence of adhesion problems related with metal deposition on pre-processed titanium.

The effects of rapid thermal annealing (RTA) on the performance and reliability of deposited gate oxides for thin film transistors (TFT) are studied. Temperatures between 700 to 950 degrees Centigrade and annealing ambients such as oxygen, nitrous oxide and argon are considered. Results show that RTA leads to increased charge to breakdown (Qbd) compared to furnace annealing. The nitrous oxide and argon ambients also yielded higher Qbd due to reduced interfacial stress. RTA also reduced trap density as well as temperature instability in TFTs.

Research shows that a rapid thermal postoxidation annealing (poa) technique which reheats thin gate oxides in pure nitrogen results in high charge-to-breakdown and low interface trap densities. However, the technique results in samples susceptible to radiation damage. Reduced radiation hardness caused by poa degradation can be reduced through a reoxidation process. The setting temperature profiles for the poa treatment are shown.

Poly-Si thin film transistors with high mobility bottom gates are fabricated on substrates made of hard glass by XeCl excimer laser annealing and ion doping techniques. The precursor film consisted of an amorphous SiH film, which is deposited by plasma enhanced chemical vapor deposition. The film is crystallized to the amorphous Si film by xenon chloride excimer laser annealing.

The annealing process after ion implantation using a simulation model for boron diffusion is studied. Applying several parameter values that includes intrinsic and extrinsic equilibrium diffusion conditions and nonequilibrium diffusion conditions after implantation. The time elapsed in boron-interstitial silicon pair influences the rate of boron diffusion during annealing following ion implantation.

The use of local interconnection technology to thwart leakage currents in the diode is studied. Chemical vapor deposition tungsten embedded on polysilicon is applied in local interconnection technology to fabricate metal oxide semiconductors 0.25 micrometers thick. This fabrication technique has low resistivity, discourages diffusion and separation of dopants which makes it a logical choice for a gate shunt and local interconnection material. High doping concentrations may lead to leakage currents in the diode.

The influence of post-nitridation anneals in oxygen and nitrogen on the electrical characteristics of gate oxides was investigated. The study focused on the charge trapping, ionizing radiation and current conduction mechanisms and tolerance to Fowler-Nordheim injection of the gate dielectrics. Metal oxide semiconductor field effect transistors whose gates are of reoxidized nitride oxide material were also studied.

The effects of rapid thermal annealing (RTA) and processing at low temperatures on the structures of high-electron-mobility transistors (HEMT) were studied. Planar doped structures, fabricated from metallic compounds such as gallium arsenide, indium gallium arsenide and aluminum gallium arsenide, were subjected to various laboratory tests. Results show that RTA temperatures above 700 degrees centigrade have adverse effects on the performance of HEMT structures.

The effects of ion implantation and rapid thermal annealing (RTA) on the performance of compound-semiconductor heterostructure devices were studied to eliminate the susceptibility of such devices to process-induced degradation. Two different heterostructure devices were subjected to ion implantation and RTA treatments and results were then analyzed. It was found that the treatments significantly improved the performance of the heterostructure devices.

The emitter and base impurity behaviors of bipolar transistors were evaluated using low-temperature furnace annealing and high-temperature rapid thermal annealing (RTA) methods to determine the requirements needed for developing efficient 0.5 micrometer bi-complementary metal oxide semiconductors. It was found that RTA can treat problems that affect the transistors' performance better than low-temperature furnace annealing. These problems include enhanced boron diffusion and abnormal arsenic activation in the transistor's emitter .

Rapid photothermal annealing was applied to Ta2O5 thin films deposited by thermal metalorganic chemical vapor deposition. The samples annealed with high-energy photons had lower leakage current, low trap density and lower thermal stress as compared to rapid thermal annealing. Results showed that rapid photothermal annealing has the potential of meeting the manufacturing needs of future generation of integrated circuits.

Rapid thermal contact annealing was found damaging to the threshold characteristics of thin-film transistors (TFT's) but, it can improve the maximum transconductance. It was also observed that at higher rapid thermal contact annealing temperature, more degradations on the characteristics of the TFT's will be observed. Low-temperature anneal in H2/N2 gas ambient was recommended for recovery of these degradations.