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Spintronic-based computing-in-memory (CiM) architecture has emerged as one of the efficient solutions to eliminate the latency/bandwidth bottleneck of conventional von-Neumann architecture. Voltage-controlled spin-orbit torque (SOT) memory offers ultralow power and high-speed operation among the various spintronic memories. In this article, advanced encryption standard (AES) system within CiM architecture using voltage-controlled SOT device has been presented. The entire encryption process is performed within the high-density spintronic-based memory array to achieve low power and high processing speed. The reconfigurable logic operations and random key generation for AES are achieved by using a single voltage-controlled SOT device within the memory array. The results show that the proposed architecture is 96%, 52.1%, and 14% more efficient in terms of energy consumption, throughput, and area, respectively, when compared with one of the most efficient SOT-based AES systems.

This article presents a multilevel design for spin–orbit torque (SOT)-assisted spin-transfer torque (STT)-based 4-bit magnetic random access memory (MRAM). Multilevel cell (MLC) design is an effective solution to increase the storage capacity of MRAM. The conventional SOT-MRAMs enable an energy-efficient, fast, and reliable write operation. However, unlike STT-MRAM, these cells take more area and require two access transistors per cell. This poses significant challenges in the use of SOT-MRAMs for high-density memory applications. To address these issues, we propose an MLC that can store 4 bits and requires only three access transistors. The effective area per bit of the proposed cell is nearly 58% lower than that of the conventional 1-bit SOT-MRAM cell. The combined effect of SOT and STT has been incorporated to design SOT-STT-based MLC that enables more energy-efficient and faster write operation than the regular MLCs. The results show that SOT–STT-based 4-bit MLC is 52.9% and 40% more efficient in terms of latency and energy consumption, respectively, when compared to 3-bit SOT-/STT-based MLC.

In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and M0 filling through S/D trenched regions in addition to the conventional scheme where metal (M0) epi on the S/D. The device ET performance is enhanced by increasing the device on-state current ( ${I_{ \mathrm{\scriptscriptstyle ON}}}$ ) by more than 10% with better device lattice heat removal from the hot-spot location of the NSHFET. This results in decreased device self-heating by lowering lattice hot-spot temperature ( ${T}_{L, max}$ ) and device effective thermal resistance ( ${R}_{th, eff}$ ) by more than 11% compared to conventional M0-epi-based NSHFET design. The junction temperature difference between the nanosheet channels is also lowered, which decreases the inter-sheet threshold voltage ( ${V}_{T}$ ) difference. The benchmarking study of the device designs reveals that M0-trench-based NSHFET gives the best performance from both electrical and thermal perspective for future sub-5-nm CMOS logic technologies.

In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied for U-shaped n-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventional n-channel FDSOI MOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less $1\sigma $ threshold voltage ( ${V}_{T}$ ) and ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low ${V}_{T}$ mismatch index ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ ) close to the literature reported. Due to combined variability sources, U-SOIFET shows less ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.

Artificial intelligence has been demonstrated for numerous applications including image recognition and processing, internet-of-things (IoT), and speech recognition. Recent neural network (NN) architectures escalating to perform these functionalities require deep-learning and deep NN (DNN) implementation. However, the present algorithm and circuit of DNN suffer from area and energy-efficiency. The usage of an energy-efficient and cost-effective binary NN (BNN) can mitigate the performance bottleneck. The basic component of BNN (the XNOR and accumulate module) is capable of replacing the conventional multiply-and-accumulate (MAC) operation. Among various emerging nonvolatile memories (NVMs), spintronics-based devices are attracting attention for the implementation of the aforementioned architectures. Multilevel voltage-controlled spin-orbit torque -based magnetic memory (MV-SOTM) spin device as synapse and voltage-controlled SOTM (V-SOTM) device as spin-neuron are capable of producing an all-spin NN. This article presents advanced XNOR operation using a computing-in-memory (CiM) mechanism wherein both V-SOTM and MV-SOTM (using series and parallel configuration) based synapses are compared. The MV-SOTM design dissipates 35.51% lesser energy as compared to the 1-bit V-SOTM. Further, the 8-bit synaptic crossbar array is implemented using both the devices with two output spin-neurons. These series and parallel MV-SOTM-based synaptic arrays consume 42.22% and 45.12% lesser power, respectively, as compared to 1-bit V-SOTM based synaptic array. Furthermore, the all-spin BNN design demonstrates a handwritten digit recognition application.

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

The majority of the combinatorial optimization problems are solved by searching a solution space that grows as an exponential function of the problem size. Such class of problems scales inefficiently on the Boolean von Neumann architecture. On the other hand, alternative computing techniques like coupled-oscillator networks are efficient in solving combinatorial optimization problems. In this article, we demonstrate the effectiveness of antiferroelectric tunnel junctions (AFTJs) in coupled-oscillator networks for solving combinatorial optimization problems such as graph coloring. AFTJs are tunnel junctions that show a high ON-/OFF-current ratio. The high ON-/OFF-current ratio of AFTJs allows a higher sense margin at low bias current. Consequently, AFTJ oscillators are more energy-efficient compared to VO2-, HfTaOx-, and TaOx-based oscillators. This article explains the origin of the large ON-/OFF-current ratio of AFTJs. A physics-based model is proposed to predict the AFTJ current. The proposed AFTJ model is compared to experimental results to show the ability of the model to predict AFTJ behavior. The proposed AFTJ model is implemented in Verilog-A and used in circuit simulations of the AFTJ-based coupled-oscillator network.

This article presents a detailed investigation of the impact of mechanical strain on transition metal dichalcogenide (TMD) material-based tunneling field-effect transistor (TFET). First, the impact of mechanical strain on material parameters of MoSe2 is calculated using the first principle of density functional theory (DFT) under meta-generalized gradient approximation (MGGA). The device performance of the TMD TFET has been studied by solving the self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. The results demonstrate that both ${I}_{\scriptscriptstyle {\rm {ON}}}$ and ${I}_{\scriptscriptstyle {\rm {OFF}}}$ increase with uniaxial tensile strain, however the change in ${I}_{\scriptscriptstyle {\rm {ON}}}/{I}_{\scriptscriptstyle {\rm {OFF}}}$ ratio remains small. This strain-dependent performance change in TMD TFET has been utilized to design an ultrasensitive strain sensor. The device shows a sensitivity ( $\Delta {I}_{\text {DS}}/{I}_{\text {DS}}$ ) of 3.61 for a strain of 2%. Due to the high sensitivity to the strain, these results show the potential of using MoSe2 TFET as a flexible strain sensor. Furthermore, the strained TFET is analyzed for backend circuit performance. It is observed that the speed and energy efficiency of ten-stage inverter chain based on controlled strain improve substantially in comparison to unstrained TFETs.

Conventional von Neumann architecture suffers from data trafficking and power hungriness between memory and processing units. Recent architectures escalating to overcome these limitations are near-memory architecture (NMA) and computing-in-memory (CiM) architecture (CMA). Spintronics-based devices, such as spin-transfer torque magnetic memory (STTM), spin-orbit torque magnetic memory (SOTM), differential spin Hall–effect-based magnetic memory (DSHEM), and multilevel voltage-controlled SOT-based magnetic memory (MV-SOTM) are a few promising contenders for post-CMOS technology. MV-SOTM spin device is used in this study to showcase the CMA to perform basic logic operations namely AND/ NAND, OR/ NOR, and XOR/ XNOR within the memory array. Furthermore, magnetic full adder (MFA) is implemented using CMA in MV-SOTM array. The performance of CMA design for MV-SOTM-based MFA is compared with SOTM-based MFA. The proposed CiM design for MV-SOTM-based MFA shows 29.2% and 12.22% performance improvement in terms of write energy and logic power, respectively. Moreover, up to 34% area reduction is achieved in comparison to SOTM-based CiM MFA.

The expected explosive growth of big data, the Internet of Things, artificial intelligence, and 5G mobile networks will not only challenge but also offer new opportunities to solid-state memories in the next decade. Mainstream technologies such as the 3-D NAND Flash and the 1T-1C DRAM technology will have to keep evolving to prolong their scaling trends and maintain their undisputed leadership in the standalone memory arena. At the same time, other memory technologies may take advantage of the rise of the new market applications, likely changing the balance among cost, performance, and reliability. Phase-change memories (PCM), magnetoresistive random-access memories (MRAM), resistive random-access memories (ReRAM), and ferroelectric memories have the potential to play a role both in the embedded and in the standalone memory market. However, all of them will need innovations to fully demonstrate their long-term performance. Finally, all the memory technologies will have to compete to prove the benefits of new applications and solutions, such as the mixing of storage and computing with in-memory computing, neuromorphic computing, and nonvolatile logic.

Magnetic tunnel junction (MTJ) has emerged as a viable candidate for next-generation memory and logic applications. Manipulation of the magnetic and electric field can control the spin and charge state variables that are of utmost importance in spintronics devices. In this article, the modeling of voltage-controlled spin–orbit torque (VCSOT)-based magnetic random access memory (MRAM) is demonstrated. VCSOT MRAM is an ultrafast device owing to a magnetic switching time of 0.7 ns. It is more energy-efficient as compared to spin–orbit torque (SOT) MRAM. VCSOT MRAM has been exemplified for multilevel cell (MLC) application to enhance the memory integration density. Two-bit serial MLC (sMLC) and parallel MLC (pMLC) designs are proposed using VCSOT MRAM. These MLCs are more energy-efficient as compared to SOT-MLCs. Moreover, 2-bit sMLC and pMLC VCSOT-MRAM significantly reduce average write energy by 91.5% and 49.6%, respectively, as compared to SOT-based MLC. Performance metrics for these devices have been illustrated, which shows the negligible read disturbance and write error rates.

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index ( $A_{\text {VT}}$ ) for the sub-10-nm SOI FinFET technology.

In this paper, a charge plasma-based monolayer transition metal dichalcogenide (TMD) tunneling field-effect transistor (TFET) is investigated by solving self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. We propose a work function engineered charge plasma-based dual-metal source TFET (DMS TFET) structure for an optimum performance of the device. The proposed TFET structure demonstrates superior performance than the conventional charge plasma TFETs in terms of ${I}_{{\scriptscriptstyle {\text {ON}}}}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{{\scriptscriptstyle {\text {OFF}}}}$ ratio, and subthreshold slope (SS). It provides ${I}_{{\scriptscriptstyle {\text {ON}}}}$ of $222~\mu \text{A}/\mu \text{m}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $2.22\times 10^{{5}}$ , a minimum SS of 42.41 mV/decade, and an average SS of 54.15 mV/decade for three-decade increase in drain current ( ${I}_{\text {DS}}$ ). The performance of the device is observed at different channel lengths. Based on this analysis, a device design guideline for sub-10-nm channel length TFETs is presented in the paper. Finally, the circuit level metrics of the proposed structure are estimated by calculating delay and energy-delay product of a 45-stage inverter chain.

Ferrimagnets (FiMs) are divided into small domains comprising of oppositely polarized magnetic moments and weak anisotropy. FiM possesses a small net magnetization with strong exchange coupling energy. When FiM comes in contact with a material having strong spin–orbit coupling, such as heavy spin Hall metal, the nonlinear magnetic exchange interaction known as Dzyaloshinskii–Moriya interaction (DMI) becomes significant, especially at the FiM/heavy metal (HM) interface. In this paper, we derive the contribution of DMI in FiM magnetization and show that DMI plays a crucial role in FiM magnetization dynamics. We show that torque is being exerted on the interfacial magnetic moments due to DMI, trying to reorient the interfacial magnetization landscape in FiM. On the other hand, exchange coupling tries to resist the external perturbation due to DMI and keep the interfacial magnetic moments at their respective equilibrium positions. Our analysis shows that simultaneous action of DMI and exchange coupling result in small tilting of the interfacial magnetic moments. Moreover, spin-polarized current, injected into the FiM, introduces oscillation due to two different types of spin-transfer torques—namely, “field-like” torque and “damping-like” torque. We also show that the oscillation frequency of magnetic moments near the FiM/HM interface is a function of only internal FiM exchange coupling and interfacial DMI when the injected spin current density is low.