Search

Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron–phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications. [ABSTRACT FROM PUBLISHER]

In the first part of this article, a physics-based surface-potential compact model to describe current–voltage (I–V) relationship in few-layered ambipolar black phosphorus (BP) transistors is presented. The proposed model captures the essential physics of thin-film BP FETs by accounting for the effects of: 1) in-plane band-structure anisotropy in BP, as well as the asymmetry in electron and hole current conduction characteristics; 2) nonlinear Schottky-type source/drain contact resistances; 3) interface traps; 4) ambipolar current conduction in the device using two separate quasi-Fermi levels for electrons and holes; and 5) the effect of temperature on the model parameters. In this article, the model is validated against measured data of back-gated BP transistors with gate lengths of 1000 and 300 nm with the BP thickness of 7.3 and 8.1 nm and for the temperature range of 200–298 K. We also validate the model against numerical TCAD data of BP transistors with channel lengths of 300 and 600 nm and BP thickness of 6 nm. The model is also applied to unipolar 2-D FETs with channel materials, such as MoS2 and WSe2. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here shows excellent agreement with experimental and numerical data over broad bias and temperature range. [ABSTRACT FROM AUTHOR]

We report a physics-based surface-potential compact model to describe current–voltage (I – V) relationship in a few-layered ambipolar black phosphorus (BP) transistors. To model the device electrostatics, the 2-D density of states of carriers and Fermi–Dirac statistics are used, while carrier transport is described using the drift-diffusion formalism. The model also comprehends the effects of interface traps and voltage-dependent Schottky-type source/drain contact resistances. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here is applicable over broad bias and temperature range. Validation of the model against measurement data of BP transistors with gate lengths 300–1000 nm and operating temperature from 200–298 K is demonstrated in a companion article. [ABSTRACT FROM AUTHOR]

We present a study of the effects of substrate orientation and longitudinal channel stress on the performance of extremely thin silicon-on-insulator (ETSOI) MOSFETs with gate lengths down to 25 nm. We find that short-channel electron and hole mobilities follow the long-channel mobility trends versus substrate orientation and longitudinal channel stress. We show that with respect to (100) silicon-on-insulator (SOI) substrates, short-channel ETSOI MOSFETs on (110) SOI substrates lead to 25% enhancement of the p-channel FET drive current at the expense of 12% degradation of the n-channel FET drive current at a fixed off-current of 100 \nA/\mu\m and a supply voltage of 1 V. Finally, we estimate that an ETSOI complementary metal–oxide–semiconductor (CMOS) on (110) SOI substrates should lead to 10% faster ring oscillators compared with those on (100) SOI wafers, which also implies that (100)-oriented wafers with (110) sidewalls are a better choice for fabricating nonplanar FinFETs and trigate CMOS circuits. [ABSTRACT FROM PUBLISHER]

We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ∼8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed OFF-state current of 100 nA/µm and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field). [ABSTRACT FROM AUTHOR]

Graphene lateral spin valves (LSVs) are promising devices for future memory and magnetic field sensing applications. In this article, we study the dependence of the nonlocal spin resistance, $\Delta {R}_{{\text {NL}}}$ , and the baseline resistance, ${R}_{{\text {BS}}}$ , as a function of the graphene channel width, ${W}$. The scaling trend is quantitatively assessed by using graphene deposited by chemical vapor deposition, which provides a large number of devices with consistent performance. As ${W}$ is scaled from 10 to $0.5~\mu \text{m}$ , the change in $\Delta {R}_{{\text {NL}}}$ matches the theory of contact-induced spin relaxation with a current spin polarization of 3%–5% and a spin diffusion length of $\lambda _{s} = 1.5$ – $2.5~\mu \text{m}$. We also observe a systematic and dramatic decrease in ${R}_{{\text {BS}}}$ , which we attribute to the reduction in charge current spreading. However, we find in the narrowest devices that a small ${R}_{{\text {BS}}}$ remains that arises due to thermoelectric effects, and this trend is confirmed using gate voltage- and charge current-dependent analyses. Finally, we introduce a nonideality factor, ${m} = \vert {R}_{{\text {BS}}} / \Delta {R}_{{\text {NL}}}\vert $ , as a figure of merit to describe the suppression of the baseline relative to the spin signal. In an LSV with ${L} = {1.5}\,\,\mu \text{m}$ , ${W} = {0.5}\,\,\mu \text{m}$ , and n-type conduction, the nonideality factor is as low as ${m} = {0.0252}\,\,\pm \,\,0.0202$ at room temperature showing that nearly ideal bipolar and symmetric spin signals can be achieved in graphene LSVs. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is a promising technology that can be used for low-cost hardware designs. However, SC suffers from its long latency. Although parallel processing can efficiently shorten the latency, duplicated stochastic number generators (SNGs) are necessary, which cause substantial hardware overhead. This paper proposes a scalable SNG based on the spin-Hall-effect (SHE), which is capable of generating multiple independent stochastic streams simultaneously. The design takes advantages of the efficient charge-to-spin conversion from the Spin-Hall material and the intrinsic stochasticity of nanomagnets. Compared to previous spintronic SNGs, the SHE-SNG can reduce the area by $1.6\times -7.8\times $ and the power by $4.9\times -13\times $ while increasing the degree of parallelism from 1 to 16. Compared to CMOS-based SNGs, the proposed SNG obtained $24\times -120\times $ and $53\times $ reduction in terms of area and power, respectively. Finally, three benchmarks were implemented, and the results indicate that SC implementations with the proposed SHE-SNG can achieve $1.2\times -29\times $ reduction of hardware resources compared to implementations with previous CMOS- and spintronic-based designs while scaling the degree of parallelism from 1 to 64. [ABSTRACT FROM AUTHOR]

Precise measurements of the mobility anisotropy along high-symmetry crystal axes in black phosphorus (BP) MOSFETs are reported. Locally back-gated BP MOSFETs with 13-nm HfO2 dielectric and channel length ranging from 0.3 to 0.7 $\mu \text{m}$ are fabricated. A single BP flake of a uniform thickness is exfoliated and etched along armchair (AC) and zigzag (ZZ) crystal axes, and the orientations are confirmed using optical and transmission electron microscopy analyses. The hole and electron mobilities along each direction are extracted using the transfer length method. The AC-to-ZZ hole mobility ratio is found to increase from 1.4 (1.5) to 2.0 (2.9) as the sheet concentration increased from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 at room temperature (77 K). The room-temperature electron mobility anisotropy is found to be similar to that for holes with an AC-to-ZZ mobility ratio increasing from 1.4 to 2.1 from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 though electrons showed only a very weak temperature dependence. A Boltzmann transport model is used to explain the concentration- and temperature-dependent mobility anisotropies which can be well described using a charge center scattering model. [ABSTRACT FROM AUTHOR]

N-and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates. [ABSTRACT FROM AUTHOR]