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This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 /spl Omega//mm for the BP-LD3 structure indicate high potentiality for analog applications.

The minimum device isolation distance (L/sub min/) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L/sub min/ is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L/sub min/ at room temperature is 1.3 mu m with a bias voltage of 2 V and an acceptor concentration of 10/sup 15/ cm/sup -3/. L/sub min/ decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V. >

Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WN/sub x/-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (L/sub G/=10, 4, 2, 1, 0.8, 0.5, 0.3 mu m, W/sub G/=20 mu m; W/sub G/-100, 40, 20, 10, 4, 2 mu m, L/sub G/=0.5 mu m). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN/sub x/-gate fabrication process. Injected excess charges at gate length below 0.5 mu m distorts the mobility evaluations. >

Asymmetric tilt-angle-implanted lightly doped drain (LDD)-WN/sub x/-GaAs MESFETs with an optimized transconductance performance are discussed. A tilt-angle implantation is used to reduce the parasitic source resistance below the gate sidewall without increasing short- and narrow-channel effects. This leads to a transconductance increase of nearly 25% for submicrometer FETs while the gate-source capacitance increase is almost negligible. The influence of the implantation angle on the threshold voltage transconductance, and Schottky-barrier characteristics is reported. >

The Schottky barrier of reactively sputtered WN x to p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFET's were fabricated with WN x gates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FET's with 2 µm × 24 µm gates were 0.088 mA/V2, consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.