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Lead-based organic–inorganic hybrid perovskite single crystals (OIHP SCs) offer promising opportunity for X-ray detection and imaging owing to their high X-ray attenuation coefficient, excellent optoelectronic properties, and simple fabrication processes. Nevertheless, it remains a key challenge to reduce its dark current and meanwhile maintain a high sensitivity. Herein, we developed an on-substrate method for growing methylamine lead bromide (MAPbBr3) SCs on aluminum oxide (Al2O3) layer coated indium tin oxide (ITO) glass. The photodiode based on this approach exhibits an ultralow-dark-current density of 1 nA cm−2 at an operative voltage of −5 V, a signal-to-noise ratio (SNR) more than 80 dB, and meanwhile retaining a high X-ray sensitivity of 2.02 $\times 10^{{3}}\,\, \mu \text{C}\cdot $ ${\mathrm {Gy}}_{\text {air}}^{-1} \cdot $ cm−2. Our further investigation reveals that the dark current was reduced due to two beneficial effects of the Al2O3 layer in tandem, including the interfacial defect passivation and blocking of hole injection by increased interfacial energy barrier. Our approach sheds light on advancing the fabrication of high-performance OIHP SCs-based X-ray sensors that can be potentially integrated with large-area readout panel at low temperature. [ABSTRACT FROM AUTHOR]

The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°. [ABSTRACT FROM AUTHOR]

By adopting atomic layer deposition (ALD) sidewall passivation, the electroluminescence (EL) and communication performances of mini-light emitting diodes (mini-LEDs) of different sizes were improved. In particular, the most significant improvement in the electroluminescence properties of the external quantum efficiency (EQE) (a 7.2% increase), leakage current, and the communication properties of the modulation bandwidth (a 20% increase) transmission rate and bit error rate (BER) was found in the smallest mini-LEDs (80 $\mu \text{m}\,\,\times $ 120 $\mu \text{m}$). According to the results of time-resolved photoluminescence (TRPL) measurements, the carrier lifetime of the samples can be affected by both the size and ALD sidewall passivation. In addition, the effects of ALD sidewall passivation for visible-light communication (VLC) were demonstrated. [ABSTRACT FROM AUTHOR]

In this work, the impact of low-pressure chemical vapor deposition (LPCVD)-SixNy stoichiometry on 2-D electron gas (2-DEG) transport characteristics of the AlGaN (3.9 nm)/GaN heterostructure and the underlying mechanism of increased 2-DEG density are studied, which reveals a new perspective of improving AlGaN/GaN performance by dielectric engineering. Among the AlGaN/GaN passivated by the LPCVD-SixNy with tailored stoichiometry, the 2-DEG density and mobility in the Si-rich sample were significantly improved by 25% and 16.3% compared with the N-rich sample, respectively. Accordingly, 30% reduction in sheet resistance of AlGaN/GaN heterostructure is obtained. The potentially strained-induced enhancement of piezoelectric polarization and corresponding 2-DEG variation by the SixNy passivation layer was excluded by the negligible change in Raman spectra among the different samples. Alternatively, the X-ray photoelectron spectroscopy (XPS) showed that the varied stoichiometry of the SixNy enables a discernible modulation effect of heterostructure energy-band. The reduced surface potential in the sample passivated by Si-rich SixNy attributes to the pronounced Ga dangling bonds (DBs) at the LPCVD-SixNy/AlGaN interfaces, which provides the near-conduction band (NCB) states and leads to enhanced 2-DEG accumulation. [ABSTRACT FROM AUTHOR]

In this study, the influence of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with different passivation (PV) layers under positive bias stress (PBS) in a moist environment and hot-carrier stress (HCS) is investigated. The Al2O3-passivated device can effectively suppress H2O molecule absorption, but the HCS reliability is inferior. The degradation behavior is attributed to the high permittivity of Al2O3, which lacks oxygen, and the oxygen from the etch stop layer (ESL) diffuses into the Al2O3 film during the process, causing the generation of oxygen vacancies in the ESL. Therefore, an optimal outer Al2O3-passivated device is proposed, in which the Al2O3 film is deposited away from the ESL. With this optimal PV structure, both the results under PBS in a moist environment and HCS can achieve good stability in the outer Al2O3-passivated device. [ABSTRACT FROM AUTHOR]

We study the impact of access region passivation on the electrical characteristics of hydrogen-terminated diamond MOSFETs with tungsten Carbide (WC) edge contacts. Our experiments reveal a significant improvement to both contact and extrinsic channel sheet resistance once the access regions are passivated with WO3, indicating that WO3 is an effective surface transfer-doping agent. We analyze a peculiar bump that appears in the subthreshold characteristics of the devices that prevents their effective turn-off. The bump is found to be mitigated when the access regions are passivated by WO3. Poisson–Schrödinger (P–S) simulations suggest that this bump arises from the field-effect action by the gate over the access region immediately adjoining the gate. This parasitic field effect arises when the surface is unpinned and with a light hole concentration. Owing to its increased surface transfer doping, the use of WO3 as surface passivation is effective in delivering a sharp device turn-off. [ABSTRACT FROM AUTHOR]

This work reports gadolinium-doped cerium oxide (CeO2) as gate dielectric, and appropriate doping of Gd can effectively prevent oxygen vacancy-related defects in CeO2 thin films. Atomic layer deposition (ALD)-derived 3 nm Al2O3 passivation layer on CeGdOx has the advantage of further reducing the leakage current of CeGdOx MOS capacitors due to the wide bandgap and compactness of Al2O3. Then, Al2O3/CeGdOx bilayer dielectric-based In2O3 thin-film transistors (TFTs) are constructed; electrical performances are systematically explored under the effect of Gd doping compared with pristine Al2O3/CeO2-gated TFT. Al2O3/CeGdOx (30 at% Gd) TFT demonstrates high performances with ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio of 1.45 $\times 10^{{7}}$ , saturation mobility of 27.28 cm2/V $\cdot $ s, subthreshold swing (SS) of 0.091 V/decade, interfacial trap states of $1.64\times 10^{{11}}$ cm−2, as well as remarkable positive bias stress (PBS) stability. Low-frequency noise (LFN) together with X-ray photoelectron spectroscopy (XPS) illustrates that Gd doping in CeO2 contributes to the reduction of interface trap density, improving electrical performance. Moreover, a resistor-loading inverter based on Al2O3/CeGdOx-gated TFT exhibits superior voltage transfer characteristics (VTC) with a voltage gain of 16 at 5 V, demonstrating the potential application of Al2O3/CeGdOx-based TFTs for future digital circuits. [ABSTRACT FROM AUTHOR]

In this study, we propose an advanced tunnel oxide passivated contact (TOPCon) solar cell structure for bifacial usage. The proposed structure, named advanced industrial TOPCon (Ai-TOPCon), adopts rear-side local carrier-selective contacts to avoid rear-side light-absorption loss. Ai-TOPCon features larger rear-side light currents and improves the power density by approximately 0.28 mW/cm2 for bifacial usage in a 20% albedo scenario. Several types of Ai-TOPCon and industrial TOPCon (i-TOPCon) are evaluated, and the optimization of the structure resulted in a power density of 28.73 mW/cm2. Loss analysis revealed that the reduced Auger recombination volume was the main factor contributing to the improvement of cell performance, and the light-absorption problem was solved by reducing the rear-side heavy-doped region. [ABSTRACT FROM AUTHOR]

Laminated hafnium oxide (HfO2)/alumina (Al2O3) fabricated by atomic layer deposition (ALD) process is employed as an encapsulation to improve the performance of carbon nanotube thin-film transistor (CNT-TFT). The outstanding hysteresis suppression ability of laminated HfO2/Al2O3 is demonstrated in the transfer characteristic of thin-film transistor (TFT) devices, with the threshold voltage variation ($\Delta{V}_{\text {th}}$) of different scanning directions decreasing from ~11.06 to ~0.48 V after encapsulation, which is mainly attributed to the removal of water and oxygen molecules adsorption on the carbon nanotubes (CNTs) backchannel surface and the passivation effect to the defects at the interface between the CNTs and the gate insulator. It appears that the CNT-TFT with laminated HfO2/Al2O3 with an optimized 5 nm/5 nm structure exhibits excellent hysteresis suppression ability and performance improvement. In addition, the TFT devices with the optimal laminated HfO2/Al2O3 layers also show great reliability and gate bias stress stability. [ABSTRACT FROM AUTHOR]

In this article, solution-derived amorphous cerium oxide (CeO2) with smooth surface as gate dielectric has been investigated. Electrical analysis has indicated that ALD-derived 3 nm Al2O3 passivation layer on CeO2 surface is benefit to reduce leakage current of CeO2 MOS capacitors. Meanwhile, solution-processed In2O3 thin-film transistors (TFTs) based on optimized Al2O3/CeO2 bilayer dielectric are integrated for the first time. Results indicate that 300 °C annealed In2O3/Al2O3/CeO2 TFT presents high performances with saturation mobility of 18.25 ± 0.92 cm2/ $\text{V}\cdot \text{s}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of (1.81 ± 0.30) $\times \,\,10^{{7}}$ , subthreshold swing of 0.071 ± 0.002 V/decade, interfacial trap states (${D}_{\,\text {it}}$) of (6.00 ± 0.48) $\times \,\,10^{{11}}$ cm $^{-{2}}$ , and remarkable positive bias stress (PBS) stability, respectively. Furthermore, a resistor-loaded inverter is fabricated with voltage gain of 12.81 at 5 V and good voltage-transfer characteristics (VTCs), demonstrating the potential application of Al2O3/CeO2 as high- ${k}$ gate stacks for future TFTs. [ABSTRACT FROM AUTHOR]

This article presents improvements of large-signal RF power performance at Ka-band of gallium nitride high electron mobility transistors (HEMTs) utilizing a scandium aluminum nitride barrier. Three samples were fabricated and measured having different passivation schemes, including gallium nitride, silicon nitride, and aluminum gallium nitride. The pinning of the Fermi level against the valence band reduced the gain and output power density of the gallium nitride passivated device, resulting in 4.5 W/mm at a drain bias of 32 V. With silicon nitride alone as the passivation, dc/RF dispersion was reduced, and gain increased significantly, boosting the output power for this device to 8.0 W/mm at 28 V, though at the cost of a reduced breakdown voltage. Adding an epitaxial aluminum gallium nitride passivating layer increased the maximum bias voltage that the devices can operate at compared to devices with the silicon nitride passivation. When biased at 40 V, the output power of the devices reached 10.8 W/mm at 30 GHz. These devices show the importance of the passivation design to large-signal RF performance in scandium aluminum nitride-based HEMTs and will help guide further improvements. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Si-rich SiN/Si3N4 bilayer passivation were studied in this article. The use of a Si-rich SiN interlayer leads to improved channel transport property, current collapse, power performance, and temperature-dependent stability. Devices without Si-rich SiN interlayer passivation exhibit an increase in the gate leakage current by over three orders of magnitudes with temperature increasing from 300 to 420 K, leading to an increase in a current collapse from 9.7% to 24.7%, while the devices with Si-rich SiN passivation exhibit a weak temperature dependence of leakage current and a constant current collapse about 5%. Small signal characterization shows that Si-rich SiN passivation results in a remarkable decrease in the effective gate length by ~15% with temperature up to 420 K. At 17 GHz, devices with Si-rich SiN interlayer passivation exhibit an output power density of 7 W/mm and a peak power-added efficiency (PAE) of 56%. The improved power performance of devices using Si-rich SiN interlayer passivation is attributed to the suppressed current collapse and superior device stability under high channel temperature. [ABSTRACT FROM AUTHOR]

In this article, InGaAs FinFETs using (010) orientation channel and nitrogen post remote plasma (RP) treatment have been fabricated. This device exhibits a peak transconductance, ${g}_{m}$ , of 2727 $\mu \text{S}/\mu \text{m}$ which is among the highest values reported for In0.53Ga0.47As FinFETs. In addition, subthreshold performances are improved with leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) of $1.13\times 10^{-{4}}~\mu \text{A}/\mu \text{m}$ , subthreshold swing (SS) of 78 mV/dec, drain-induced barrier lowering (DIBL) of 55 mV/V, and equivalent oxide thickness (EOT) ~0.8 nm. These excellent results are attributed to the strong electrostatic control and the superior high- $\kappa $ /InGaAs interface quality achieved by scaled fin width and RP passivation. [ABSTRACT FROM AUTHOR]

Self-assembled monolayers (SAMs) with three different head functional groups are prepared as passivation layers (PVLs) for amorphous InSnZnO (ITZO) thin-film transistors (TFTs). Head groups exhibit considerable modulation of surface topography and surface energy, leading to a difference in the passivation effect. This variation is attributed to the discrepancy of the binding methods determined by the head groups. Additionally, the head groups also modulate the relative direction and strength properties of dipoles at ITZO surface, which affects the surface potential and carrier density in ITZO films. As a consequence, the electric performance and stability of devices can be modulated by head groups in SAMs. These results provide a likely and low-cost method to ameliorate the capability of TFTs. [ABSTRACT FROM AUTHOR]

Nitrogenous octadecylamine (ODA) self-assembled multilayers (SAMs) are prepared as passivation layers by the vapor-phase process for amorphous InSnZnO (ITZO) thin-film transistors (TFTs). The vapor-phase proposed ODA SAMs show excellent properties as a barrier against the atmosphere and serve as an effective nitrogen doping (N doping) source. After the self-assembled process, the distribution of the oxygen vacancies is modified by N-doping in the channel of the ITZO TFTs, wherefore the ITZO TFTs with ODA SAMs demonstrate an improvement of electrical properties. In addition, the oxygen and water adsorption/desorption reactions at the back channel are suppressed by the atmosphere isolation and N-doping effect, leading to an improvement of the positive bias stability. These results indicate that the nitrogenous ODA SAMs can be likely passivation layers for high-performance oxide TFT devices. [ABSTRACT FROM AUTHOR]

The submicrometer gate HEMT is fabricated with an ultrathin-barrier (UTB) AlGaN/gallium nitride (GaN) combined with in situ SiN passivation. The sheet resistance of the UTB Al0.2Ga0.8N (4 nm)/GaN heterostructure is effectively reduced by the SiNx passivation layer grown by metal organic chemical vapor deposition (MOCVD), from 6500 to $312~ \Omega $ /⬜. With the 20-nm stress-engineered in situ SiN, the device not only provides a large output current of 1.05 A/mm but also demonstrates promising potential on the RF applications, which gives AlGaN material two records high cutoff frequency ${f} _{\text {T}}/{f} _{\text {max}}$ of 157 GHz/334 GHz for 100-nm gated device and 211 GHz/379 GHz for 70-nm gated device. During the continuous wave (CW) power measurement at 30 GHz, the 70-nm devices exhibit a large output power of 4.6 W/mm associated with a peak power-added efficiency (PAE) of 48.1% and a gain of 11.6 dB (${V} _{\text {ds}} =20$ V), and a high PAE of 53.8% with an output power density of 1.9 W/mm and a gain of 10.8 dB (${V} _{\text {ds}} =10$ V), respectively. The huge potential of the UTB-AlGaN/GaN is demonstrated for high-frequency and large-output power applications when it is combined with the in situ SiN, which is necessary for future communication systems. [ABSTRACT FROM AUTHOR]

Bottom-gate bottom contact amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) were fabricated using solution processing. The nonpassivated a-IGZO-TFTs exhibited a significant threshold voltage shift, large hysteresis in the current–voltage characteristics, and degradation in the subthreshold swing. TFTs’ performance degradation is due to the interaction of its back channel with adsorbed oxygen and water molecules in the ambient air. The hydroxy-phenyl zinc porphyrin (ZnP) self-assembled monolayer (SAM) was formed on TFTs’ back channel using a low-cost solution-based approach to passivate TFTs back channel. The passivated a-IGZO-TFTs exhibited enhanced electrical characteristics and improved stability compared with nonpassivated TFTs. Passivated TFTs presented significantly reduced hysteresis up to 87% and subthreshold slope degradation up to 71%. The passivated TFTs showed excellent stability under positive (20 V) and negative (−20 V) bias stress conducted for 5000 s. [ABSTRACT FROM AUTHOR]

Au nanoparticles (NPs) were drop-casted onto germanium (Ge) devices to investigate the influence of Au NPs on the electronic transport and photodetection properties of Ge metal–semiconductor–metal photodetectors. A significant hysteresis behavior was observed in the current–voltage curves of the Au NP-decorated Ge photodetector, which was ascribed to the energy band bending below the Au NPs and the electrostatic effect of image charges in the Au NPs. More interestingly, at the optical communication wavelength of $1.55~\mu \text{m}$ , the introduction of Au NPs effectively improved the responsivity of the device from 0.18 to 0.92 A/W. Rather than the localized surface plasmon resonance effect, the increase of responsivity in the Au NP-decorated Ge photodetector was caused by a type-II liked energy band alignment, which enhanced the spatial electron–hole separation effect. These results provide inspiration for the development of novel optoelectronic devices. [ABSTRACT FROM AUTHOR]

We report a unique OFF-state drain-to-source critical stress voltage above which the dynamic performance of AlGaN/GaN HEMTs is significantly deteriorated. Physical insights are developed through detailed experiments conducted for different design variants, increased substrate bias, varying temperature, varying stress time, and experimenting buffers with lower C-doping. The surface leakage measurements on dedicated test structures and experimentation of devices realized over GaN buffer with different carbon doping reveal that the observed phenomenon is solely caused by traps present in carbon-doped GaN buffer. Surface traps have no role to play as far as they do not modulate the electric field in the GaN buffer (discussed in Part-II). Stress time, substrate temperature, substrate bias, electric-field shape, and depletion regions formed under the gate as well as field plate region were found to play a key role in governing trap-assisted transport and carrier trapping in the GaN buffer. A deeper physical insight to explain the observed phenomena and its dependency on various conditions are developed through detailed measurements, TCAD simulations, electroluminescence, and photoluminescence spectroscopy. With the help of the physical insight gained into the underlying mechanism, a novel surface passivation scheme using a p-type oxide is reported in Part-II, which helps relaxing the field distribution across the access region and buffer, and in turn improves the dynamic performance of the HEMTs. Besides, the Part-II also unifies the mechanism across different gate-stack designs and reveals the interplay between the surface and buffer, which governs the dynamic performance of these devices. [ABSTRACT FROM AUTHOR]

The underlying mechanism responsible for the unique dynamic ON-resistance behavior is unified by demonstrating the presence of critical drain stress voltage, above which dynamic ON-resistance increases significantly, in different gate stacks. Metal–insulator–semiconductor (MIS)- and Schottky-gated HEMTs show similar dependence of critical voltage on various parameters, which establishes that gate-stack design has negligible impact on the observed phenomena. Furthermore, using the physical insights developed, this work proposes a novel surface passivation scheme to improve the dynamic performance of the device. The proposed surface passivation scheme uses p-type Al0.5Ti0.5O (AlTiO), which is deposited over SiNx passivation (or GaN cap), and is shown to be an effective tool in improving the dynamic ON-resistance of the device by modulating the electric field in the GaN buffer. The proposed passivation scheme has avoided the critical voltage to appear for the entire drain stress voltage, stress time, and substrate bias range. Detailed computational analysis in conjunction with electroluminescence (EL) and photoluminescence (PL) studies revealed an electric field redistribution due to the p-type nature of AlTiO deposited over the surface passivation/capping layer, which is responsible for relaxed electric field profile in GaN buffer and observed improvement in dynamic performance. Besides, the new observations have further helped to understand the interplay between surface conditions and GaN buffer, defining its collective role in governing the dynamic performance of GaN HEMTs. Finally, various findings and the proposal in this work have been validated for buffers having higher carbon doping and devices with p-type AlTiO deposited over GaN cap instead of in situ SiNx cap. [ABSTRACT FROM AUTHOR]

In this article, the hydrogen-terminated diamond metal-oxide-semiconductor field effect transistors (MOSFETs) which can operate at high frequency of 10 GHz are demonstrated. The devices were fabricated with a 50 nm Al2O3 gate insulator and a 350 nm Si3N4 passivation layer, which is compatible with the process of monolithic microwave-integrated circuits (MMICs). The device with gate length of 0.35 $\mu \text{m}$ shows a high drain current density of −561 mA/mm. The RF small signal characteristics and power output performances at 10 GHz for the devices with different gate widths have been investigated. With the gate width increased from 100 to 200 $\mu \text{m}$ , the extrinsic maximum frequency of oscillation ${f} _{\text {max}}$ is slightly decreased from 23 to 21 GHz, whereas the output power density at 10 GHz is improved from 1.05 to 1.26 W/mm, with associated power added efficiency increased from less than 5% to 20.77%. Comparing with the devices fabricated by the self-aligned gate process, the power output performance is significantly improved, indicating it is a promising method to fabricate high power and high frequency diamond MOSFETs by using the thick Si3N4 passivation technique. [ABSTRACT FROM AUTHOR]

We measure the electrical performance and stability of indium tin zinc oxide (ITZO) thin-film transistors (TFTs), respectively, covered with a passivation layer (PVL) of aluminum oxide (Al2O3) or scandium oxide (Sc2O3) prepared by pulsed laser deposition (PLD). The devices with the Sc2O3 PVL exhibit both satisfactory electrical performance and stability with a field effect mobility of 16.4 cm2/Vs, threshold voltage of 1.0 V, subthreshold swing of 0.09 V/decade, and especially, a minimum threshold voltage shift of 0.7 and −1.6 V under negative bias temperature stress (NBTS) and positive bias temperature stress (PBTS), respectively. This may be attributable to the suppression of oxygen vacancy formation and excellent capacity to protect the channel from environmental effects. Although the devices with the Al2O3 PVL show similar electrical performance, their stability is worse than that of the devices with Sc2O3. This shows the excellent potential of Sc2O3 thin films as a PVL. [ABSTRACT FROM AUTHOR]

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances. Besides field dependence, the critical voltage was found to be carrier energy dependent by comparing the performance of devices subjected to semi- ON-state stress with devices under OFF-state stress. Experimentation on HEMTs with different buffer carbon doping variations revealed the degradation phenomenon to be a function of carbon doping in the GaN buffer. Furthermore, detailed electric field and electron temperature analysis revealed the drain edge to be a hot spot in accelerating interaction of hot electrons with traps in the GaN buffer leading to gate current degradation. A mechanism based on hot electron–buffer trap interaction-induced thermoelastic stress buildup and subsequent defect formation in the GaN buffer is proposed to explain the observed performance degradations. Observations such as a significant rise in channel temperature and accumulation of mechanical stress in the GaN buffer validate the proposed mechanism. Finally, the processes responsible for degradation lead to catastrophic failure of the device for longer stress times by the formation of cracks and pits in the GaN buffer, as validated by the postfailure field emission scanning electron microscopy (FESEM) analysis. [ABSTRACT FROM AUTHOR]

A micromachined thermopile infrared sensor is designed and optimized with high detective sensitivity in the article. A matched chopper operational amplifier with good linearity is implemented for signal processing. Optimizations of the sensor’s structure are proposed by the adjustment of the length of the thermocouple pairs and the filling of the back-etched cavity based on the adopted thermocouple materials. A passivation layer is implemented to minimize the flicker noise of the sensor. Based on the requirement of the optimized thermopile sensor system, both the flicker noise and the low-frequency noise of the system are suppressed for achieving high sensitivity. The chopper operational amplifier circuit with a single-ended closed-loop diagram is specifically designed for signal amplification and noise suppression. The fabricated device shows improved characterizations, with the responsivity of 182.72 V/W, detectivity of $2.47\times 10^{{8}}$ cmHz1/2/W, time constant of 10 ms, and total resistance of 270 $\text{k}\Omega $. The sensitivity of the designed system, including the sensor and the amplifier, is about 15 mV/°C, when the gain is 40 dB and the sensor-target distance is 3 cm. The system shows wide applications in the fields of noncontact temperature measurement and other special applications. [ABSTRACT FROM AUTHOR]

The influence of passivation on the edge effects (EEs) present in the capacitance–voltage (${C}$ – ${V}$) characteristics of GaN Schottky barrier diodes (SBDs) with realistic geometry is analyzed by means of Monte Carlo simulations. The enhancement of the performance of SBDs as frequency multipliers is based on the optimization of the nonlinearity of the ${C}$ – ${V}$ curve, where EEs, strongly influenced by the dielectric passivation of the diode, play a significant role and must be carefully considered. The extra capacitance associated with EEs is affected by the presence of surface charges at the semiconductor/dielectric interface, which is considered by means of a self-consistent model in which the local value of the surface charge is updated according to the surrounding electron density. Our results indicate that, in realistic SBD geometries, a higher dielectric constant of the passivation material leads to more pronounced EEs. The thickness of the dielectric and the lateral extension of the epilayer are also important parameters to be taken into account when dealing with EEs. [ABSTRACT FROM AUTHOR]

This article presents the accurate modeling results of the nonlinear behavior of a wide range of silicon-based substrates at RF. The TCAD-based model includes carrier inertia effects and captures the transient nonequilibrium phenomena in the semiconductor substrate regions in response to a large-amplitude RF signal. The model is applied to coplanar waveguide (CPW) lines measured on 19 different silicon-based samples that have key differences in their material and interface parameters, such as different values for nominal doping, interface oxide charge, the presence or not of a trap-rich passivation layer, and characteristic dimensions. Furthermore, the CPW line’s distortion levels are measured from 25 °C up to 175 °C and at five fundamental frequencies under large-signal excitation from 50 MHz to 5.4 GHz. An excellent model to experiment correlation is achieved under all of these conditions, and the impact of the material and excitation parameters are discussed with strong physical insight provided by the simulation tool. [ABSTRACT FROM AUTHOR]

A new device structure, which includes a Ga2O3 current blocking layer (CBL) and a Ga2O3 surface passivation layer (SPL), is used to fabricate a GaN-based light-emitting diode (LED). Due to the inherent properties of Ga2O3 material, the current spreading phenomenon can be effectively improved and the surface leakage current and Fresnel reflection can be remarkably reduced. The appropriate thicknesses of the Ga2O3 CBL and SPL, according to the results from series experiments, are 10 and 50 nm, respectively. In an experiment, under an injection current density of 100 A/cm2, the studied LED device with a 10 nm-thick Ga2O3 CBL and a 50 nm-thick Ga2O3 SPL shows enhancements of 76.8%, 60.7%, 76.8%, and 56.2% in light output power (LOP), luminous efficacy, external quantum efficiency (EQE), and wall-plug efficiency, respectively, in comparison to a conventional LED without the designed structure. In addition, the studied LED exhibits obvious improvement in far-field radiation pattern compared to the conventional LED device. Thus, the studied structure, which includes an appropriate Ga2O3 CBL and SPL, offers a promising route to fabricate high-performance GaN-based LEDs. [ABSTRACT FROM AUTHOR]

A comprehensive study of drain current dispersion effects in $\beta $ -Ga2O3 field-effect transistors (FETs) has been done using dc and pulsed measurements. Both the virtual gate effect in the gate–drain access region and mobile traps under the gate are the most plausible explanations for the experimentally observed pulsed current dispersion and high-temperature threshold voltage shift, respectively. Unpassivated devices show significant current dispersion between dc and pulsed ${I}$ – ${V}$ response in gate lag measurements characterized by time constants in the range of 400–690 $\mu \text{s}$ both at room temperature and higher temperatures. The increasing time constant with temperature suggests a complex electron capture and emission process in the virtual gate. The reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. The effect of traps can be minimized by using surface passivation layers, in this case, silicon nitride, which shows significant improvement in the current dispersion. This work demonstrates the detrimental effect that the traps can have on the current dispersion, which significantly limits the high-frequency operation of the device. [ABSTRACT FROM AUTHOR]

The effect of atomic-layer-deposition (ALD)-derived Al2O3 passivation layer on the interface quality of Er2O3/Al2O3/InP laminated stacks and the improvement of electrical performance has been investigated systematically. The chemical bonding states measured by high-resolution X-ray photoelectron spectroscopy (XPS) reveal that the ALD-derived Al2O3 passivation layer can effectively inhibit the diffusion of substrate elements to optimize the interface quality. Electrical characterizations show that the optimized sample has demonstrated improved electrical properties, including the large dielectric constant of 20 and the suppressed leakage current density of 4.10 × 10−7 cm2. In addition, the leakage current conduction mechanisms are also investigated as a function of thickness of Al2O3 passivation layer. The optimized interface state density extracted from the conductance method has reduced from 1.30 × 1012 eV−1cm2 of Er2O3/InP to 7.27 × 1011 eV−1cm2 of Er2O3/Al2O3/InP by adjusting the passivation layer thickness. As a result, it can be also confirmed that the passivation treatment is beneficial to inhibit the element’s diffusion and optimize the interface quality, significantly controlling the capacitor degradation caused by the leakage current through the stacked oxide layer. [ABSTRACT FROM AUTHOR]

We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS technology. We model this cycled HC degradation anneal assuming Si–H bond breakage during stress and bond passivation during anneal, with the bond dissociation and passivation energies following a bivariate Gaussian distribution. Our model can describe multiple stress and anneal time scenarios well using a single parameter set and provides insights into the recovery behavior of HC-induced defects. We find no correlation between bond dissociation and passivation energies and observe that the repeated HC stress and anneal cycles suppress the low energies from the distribution of bond passivation energies, changing its shape from the Gaussian to a non-Gaussian form. [ABSTRACT FROM AUTHOR]

A 2-D analysis of OFF-state breakdown characteristics of AlGaN/GaN HEMTs with a high-k passivation layer is performed as a function of gate-to-drain distance LGD. The relative permittivity of the passivation layer εr is changed from 1 to 60, and LGD is changed from 1.5 to 10μm. It is shown that, in all cases with different LGD, the breakdown voltage Vbr increases as εr increases. When a deep-acceptor density in an Fe-doped buffer layer NDA is 1017 cm−3 and the gate length is 0.3 μm , Vbr is determined by buffer leakage current at εr ≥ 30 before impact ionization dominates. Hence, Vbr is similar at LGD = 3 – 10 μm , and the increase rate in Vbr from LGD = 1.5 μm is about 50% even at εr =60. However, when NDA is 2 × 1017 cm−3 , Vbr is determined by impact ionization of carriers even at εr ≥ 30 because the buffer leakage current is reduced. Vbr becomes about 500, 930, 1360, and 1650 V for LGD = 1.5 , 3, 5, and 7 μm, respectively, at εr = 60. These voltages correspond to gate-to-drain average electric fields of about 3.3, 3.1, 2.7, and 2.3 MV/cm, respectively. Particularly, for short LGD , the electric field profiles between the gate and the drain are rather uniform. However, in the case of LGD = 10 μm , Vbr is about the same as that (1650 V) of LGD = 7 μm , suggesting that the electric field at the drain edge of the gate becomes a critical value before the high electric field region extends to the drain enough. This may be a limitation to increase Vbr by using a high- k passivation layer in this case. However, it can be said that, to improve Vbr further at long LGD , such as 10μm , the combination of field plate or using a higher εr material may be effective because both of them decrease the electric field at the drain edge of the gate. [ABSTRACT FROM AUTHOR]

Low-cost, highly efficient, and stable solar cells demand low-temperature processing, less stringent criteria on materials, and possibility of dynamic recovery from long-term degradation–a combination of features unachievable from the perspectives of current c-Si technology. To this end, here we propose a novel solar cell architecture with an additional control gate. Our simulation results indicate that the proposed device can achieve excellent efficiency even if the back-surface passivation is suboptimal–thus allowing exploration of a wide variety of materials and low-temperature fabrication processes. Importantly, such solar cells can dynamically offset efficiency loss due to elevated temperature and interface degradation associated with long-term field operation and hence could be of broad interest to the photovoltaics (PV) community. [ABSTRACT FROM AUTHOR]

In this study, we demonstrate a 3-in-1 mini-light emitting diodes (LEDs) with 160 × 65 μm2 mini-LED subpixel chip size. Blue mini-LEDs are combining with red and green quantum dots (QDs) by using ink-jet printing technique to achieve a full-color and high-quality mini-LEDs array in the form of a monolithic chip. Subsequently, low-temperature passivated by atomic layer deposition (ALD) at 50 °C is used to effectively avoid the photo-oxidation and maintain the color purity, 99.5% National Television Standards Committee (NTSC) and 89.6% of Rec. 2020 color gamut of red as well as green QDs (GQDs) during 300 h reliability test under 50 °C/50% relative humidity (RH) condition. The environment stability L50 of both samples is 6761 and 5889 h for red and green QDs. Finally, we advocate the potential of the demonstrated highly stable full-color QD mini-LEDs to be applied in the display technology. This research also meets the requirement for a simple QD deposition method which is expected to achieve a breakthrough. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage (VBR) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of 18.5 μm exhibits a VBR of 1344 V at ID of 1 μA/mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high IDS,max of 450 mA/mm and a low specific ON-resistance of 3.92 mΩ·cm2. Moreover, a large threshold voltage of 1.6 V (at ID of 10 μA/mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications. [ABSTRACT FROM AUTHOR]

The origination of poor quality remains debating at the as-grown SiO2/4H-SiC (0001) interface during the thermal oxidation process. A low electron density layer (SiOx(0.3 < x < 2) is observed at the Si-terminated SiO2/4H-SiC (0001) interface in experiment, different from the previous reports on carbon-related defects. In this article, the SiO2/4H-SiC (0001) interface modeled with an interfacial SiOx(0.3 < x < 2) suboxide layer (~1 nm) is systematically studied by first-principles calculations. According to the calculated electronic structures, the Si–Si antibonding structures in the SiOx layer are the dominating defects that cause obvious gap states, while the oxygen and silicon vacancy are not. The energy positions of the defect states are located at ~0.72 eV above the valence band maximum (VBM), which indicates the Si–Si defect is the potential influence factor for the p-channel Silicon carbide (SiC)-MOSFET. We further study several passivation schemes by introducing nitrogen, phosphorus, boron, and aluminum at the interface to analyze the passivation mechanism. According to the calculated results of the passivation models, nitrogen passivation is an effective method, fully removing the gap states from Si–Si defects by forming Si3N, while boron passivation works for vacancy defect at the suboxide layers. The theoretical results prove the dominated defect structures at the interfacial SiOx layer and suggest that a combination passivation strategy (nitrogen and boron) may be an effective method to further improve the SiO2/4H-SiC interface. [ABSTRACT FROM AUTHOR]

Surface treatment is quite vital to reduce the reverse leakage current and improve the current On–Off ratio of gallium nitride (GaN) quasi-vertical Schottky barrier diode (SBD). In this work, we report a new nondestructive low temperature supercritical CO2 fluid (SCF) nitridation technology to treat the surface of GaN and substantially reduce the leakage current of GaN quasi-vertical SBD. The X-ray photoelectron spectroscopy (XPS) reveals the increased nitriding degree and oxygen doping degree in the form of GaOx after the SCF process results in the leakage performance improvement. As a result, the defects at metal/semiconductor interface are passivated. Also, because of NH-2 and OH− generated from the SCF process, the surface peak electric field of n−GaN decreases, and thus the breakdown voltage is enhanced. The reverse leakage current density is reduced by more than three orders of magnitude from 3.7 × 10−6 to 3.52 × 10−9 A/cm2 (at −3 V) and the ON-/ OFF-current ratio is improved by three orders from 8 × 107 to 5.74 × 1010. [ABSTRACT FROM AUTHOR]

This work investigates a low-temperature and high-pressure (LTHP) hydrogen treatment in Si-channel and SiGe-channel metal–oxide–semiconductor capacitors (MOSCAPs). The LTHP hydrogen treatment can repair dangling bonds in the SiO2/Si and SiO2/SiGe interfaces to enhance device performance. Additional parameters of the treatment, including treatment pressure and time, are also investigated to better understand the reaction mechanisms, which further proves the effectiveness and potential of this supercritical fluid (SCF)-based treatment. In addition, this treatment will not damage the front structure and materials due to the relatively low process temperature (120 °C). Therefore, this treatment can be a nondestructive postannealing process. The results of extracting interface defect density (Dit) by the conductance method show that there is an ~51% reduction in the defect density after this posttreatment, a significant decrease. Finally, a TCAD simulation of different defect densities verifies the repair mechanism of deep-level defects. [ABSTRACT FROM AUTHOR]

This article reports a systematic study focused on the mechanical stress effect of field-plate dielectric film on the electric characteristics of AlGaN/GaN high-electron mobility transistors (HEMTs). AlGaN/GaN HEMTs were fabricated on SiC substrates, where the stress of a SiN field-plate dielectric film ranged from −252 (compressive) to +26.5 (tensile) MPa. Si-rich and compressive SiN films exhibited a significant increase in the isolation leakage. On the other hand, relatively N-rich and tensile SiN films showed a significant increase in the gate leakage current of HEMTs. In addition, pulsed I – V measurements showed the suppression in the current collapse by increasing the tensile stress. Consequently, small current collapse and small gate leakage current were obtained simultaneously with good isolation, as the film stress was optimized. [ABSTRACT FROM AUTHOR]

Amongst the new materials studied for the fabrication of high-performance flexible thin-film transistors (TFTs), amorphous indium-gallium-zinc-oxide (a-IGZO) exhibits a combination of advantages that enables its application in commercial electronics. Hence, it is crucial to understand the electrical stability of a-IGZO TFTs over long periods of time. In this work, we present the effects of long-term aging on Al2O3 passivated and unpassivated flexible a-IGZO TFTs over a period of 80 months (≈ 6.5 years). It is found that although remaining functional, these devices are influenced by different instability effects. More specifically, positive gate bias stress experiments indicate that the Al2O3 passivation layer contributes to the degradation of the devices’ performance. These results show that the Al2O3 passivation, although beneficial to the initial device stability, does not prevent the degradation of the passivated devices in comparison with their unpassivated counterparts after long periods of storage. [ABSTRACT FROM AUTHOR]

A hybrid surface structure, incorporating an Ag-grid-based aluminum-doped zinc oxide (AZO) transparent conductive layer (TCL), a microhole array, 45°-sawtooth sidewalls, and an SiO2 nanoparticle (NP)/microsphere (MS) passivation layer, is proposed for the characteristic improvement of GaN-based light-emitting diodes (LEDs). In order to optimize the contact behavior between the AZO and p-GaN layers, a 2-D Ag grid is applied on the contact interface. Because series resistance Rs is reduced by the conductive Ag-grid pattern, a lower forward voltage and a better current spreading ability are obtained. Compared with a conventional GaN LED with an injection current of 200 mA, the proposed device exhibits a forward voltage of 4.01 V, reduced from 4.34 V, and presents 33%, 34.4%, 45.4%, 33.1%, and 45.3% enhancements in the light output power (LOP), luminous flux, luminous efficacy, external quantum efficiency (EQE), and wall-plug efficiency (WPE), respectively. Moreover, a more effective current spreading in the light emission mapping image and a higher intensity in the far-field pattern are achieved. Improvements of both electrical and optical properties verify that the proposed device is promising for practical applications in solid-state lighting. [ABSTRACT FROM AUTHOR]

Thermally grown SiO2 is widely used for silicon surface passivation in solar cells and other applications due to excellent interfacial properties. SiO2 films with thickness in the range of 17 nm deposited by industrially viable spray-coating technique on both n- and p-type silicon are reported. Low values of interface state density of 1.4 × 1010 cm−2 eV−1 on n-type and 2.0 × 1010 cm−2 eV−1 on p-type were achieved. Fixed oxide charges in the range of 7.1– 9.4 × 1011 cm−2 and 3.9– 6.5 × 1011 cm−2 on n- and p-type, respectively, are obtained. Excellent passivation results in the effective surface recombination velocity of 0.97 cms−1 and 8.07 cms−1 at minority carrier concentration of 1015 cm−3 on n- and p-type Czochralski silicon, respectively, without the use of capping layer. SiO2 film exhibits dielectric breakdown field strength of 4.3 MV cm−1 and 5.6 MV cm−1 and leakage current density of 2.2 × 10−8 A cm−2 and 1.1 × 10−8 A cm−2 at 1 MV cm−1 on n- and p-type silicon, respectively. These values are superior to sol-gel-based SiO2 films reported previously and are comparable to or better than those reported for other methods for the growth or deposition of SiO2 on silicon. Amorphous nature of the film is validated by high-resolution transmission electron microscopy (TEM). The X-ray photoelectron spectroscopy (XPS) analysis shows nearly stoichiometric SiOx film. [ABSTRACT FROM AUTHOR]

We introduce a deep-recessed gate architecture in β-Ga2O3 delta-doped field-effect transistors (FETs) for improvement in dispersion and breakdown properties. The device design incorporates an unintentionally doped (UID) β-Ga2O3 layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl3 plasma-based etching at ~5 W reactive ion etching (RIE) power to ensure minimal plasma damage. Etch damage incurred with plasma etching was mitigated by annealing in vacuum at temperatures above 600 °C. A gate-connected field-plate edge termination was implemented for efficient field management. Negligible surface dispersion with lower knee walkout at high VDS, and better breakdown characteristics compared to their unpassivated counterparts were achieved. A three-terminal OFF-state breakdown voltage of 315 V, corresponding to an average breakdown field of 2.3 MV/cm was measured. The device breakdown was limited by the field-plate/passivation edge and presents scope for further improvement. This demonstration of epitaxially passivated FET is a significant step for β-Ga2O3 technology since the structure simultaneously provides control of surface-related dispersion and excellent field management. [ABSTRACT FROM AUTHOR]

The sensitivity of discrete large-area power devices to the design aspects of the termination region and to the charging effects of the electroactive passivation layer on top is presented in this work. The junction termination featuring the variation of lateral doping (VLD) is revisited for such devices by focusing on the interaction with the passivation material on top. To this purpose, an ideal dielectric (SiO2) is compared with differently-doped diamond-like carbon (DLC) by incorporating the passivation layer in the TCAD setup. The simulation analysis rigorously explains the impact of the DLC material on the layout reoptimization of a specific reference diode. [ABSTRACT FROM AUTHOR]

In this article, an ultrathin-barrier (UTB) AlGaN/GaN diode featuring metal–insulator–semiconductor (MIS)-gated hybrid anode (MG-HAD) and in situ Si3N4 cap passivation is demonstrated. The intrinsic turn-on voltage (VON) as low as 0.31 V determined by the as-grown AlGaN-barrier thickness (4.9 nm) is obtained and the VON exhibits excellent uniformity. More importantly, benefit from the MIS-gated hybrid anode structure, the UTB MG-HAD features good thermal stability in reverse blocking capability. The device delivers a substantially low leakage less than 1~μm/mm at −300 V at high temperature (HT) up to 200 °C, which is more than 100 × lower than that in the reference device w/o gate dielectric. Besides, the device exhibits respectably improved dynamic characteristics due to the incorporation of in situ Si3N4-cap passivation layer and remote plasma pretreatment (RPP) prior to Al2O3 gate dielectric deposition. The UTB MG-HAD featuring precisely VON modulation and low reverse leakage is of great interest for power electronic applications. [ABSTRACT FROM AUTHOR]

In this article, the effects of two-step annealing at the active layer (AL) and the completed device on the electrical properties and stability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) are studied. The subthreshold swing (SS) and stability of a-IGZO TFT devices are greatly improved, and the hump phenomenon under the negative bias illumination stability (NIBS) is particularly well suppressed when the TFT devices are treated with an optimum two-step annealing process (200 °C of preannealing and 300 °C of postannealing). Based on the analysis of the surface morphology, internal chemical state, and electrical properties of the IGZO thin film, an improvement of two-step annealing devices may be due to hydrogen filling the oxygen vacancies in the AL and well passivating the defects between insulating layer and AL. The result illustrates that two-step annealing is a promising method for IGZO TFT, which is not only beneficial to improve the stability of the device but also suppresses the hump phenomenon in NIBS. [ABSTRACT FROM AUTHOR]

We report improvement of TiN/Y2O3/ Si0.78Ge0.22 metal-oxide-semiconductor (MOS) interface properties by employing the trimethylaluminum (TMA) pretreatment before Y2O3 deposition. It is found that the optimum number of the TMA pretreatment cycles for minimizing interface trap density (Dit) and slow trap density (ΔNst) of TiN/Y2O3/SiGe interfaces with post metallization annealing (PMA) at 450 °C is ten cycles. The reduction in Dit and Δ~Nst is attributable to less amounts of Ge–O bonds at the SiGe interfaces. On the other hand, an increase in Dit with further increasing the number of TMA pretreatment is attributable to more amounts of Al–O bonds in ILs. [ABSTRACT FROM AUTHOR]

The effectiveness of a range of alternative high-k dielectric layers as potential passivation layers for InAs avalanche photodiodes has been investigated. The suppression of surface leakage currents is investigated by analyzing the current–voltage performance of differently sized mesa diodes passivated with each oxide layer. Three potential passivation layers, such as ZnO, Al2O3, and MgO, have been identified, all of which enables the suppression of surface leakage in smaller sized devices of a radius of 50~μm and at lower temperatures of 175 K compared to a reference SU8 device. The influence of repeated temperature cycling on these layers has also been investigated with Al2O3 passivated devices, exhibiting no change in performance after multiple cooling and heating cycles. [ABSTRACT FROM AUTHOR]

High-pressure (HP) deuterium (D2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide–nitride–oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n+ poly-Si gates. The HP D2 annealing was effective for the vertically stacked GAA MOSFET as it was for a conventional planar MOSFET. In addition, the resistance of the n+ poly-Si gate was also reduced after the HP D2 annealing. This is attributed to the passivation of defects among adjacent poly-Si grains by the HP D2. The reduced gate resistance (RG) is advantageous for decreasing RC delay. Direct characterizations of dc I – V and analyses of ac low-frequency noise (LFN) supported the abovementioned behaviors. [ABSTRACT FROM AUTHOR]

The quantum efficiency and reliability of III–V semiconductor-based light emitters can be significantly degraded by nonradiative recombination resulting from the presence of harmful surface states at the mesa sidewalls of the devices. Specifically, surface states are expected to substantially affect the possibility to observe electroluminescent cooling (ELC) in III-As light-emitting diodes (LEDs). Here, we confirm the existence of significant surface currents by exploring the effect of ammonium polysulfide [(NH4)2Sx] surface passivation on a GaInP/GaAs heterojunction double diode structure (DDS) designed to study the feasibility of ELC. The DDS consists of an LED and a photodiode (PD) within a single device structure, enabling easy monitoring of the photon-mediated thermal energy transport between the LED and the PD, and eliminating challenges associated with light extraction. Our results show that the surface passivation can improve the internal quantum efficiency of the LEDs by more than 10% points under optimal bias conditions. [ABSTRACT FROM AUTHOR]

To overcome the environment susceptibility of flexible amorphous InSnZnO (a-ITZO) thin-film transistors (TFTs), a surface passivation method utilizing n-octyltriethoxysilane (OTES) self-assembled monolayers (SAMs) is developed. The electrical characteristics of the developed transistors indicate that device performance can be enhanced upon OTES passivation, exhibiting high mobility (~19.4 cm2 V−1s−1), a steep subthreshold slope (~90 mV/dec), near-zero threshold voltage (~0.6 V), and high ON– OFF current ratio (~ 7.9 × 109). The passivation layer can effectively improve the stability of flexible ITZO TFTs even under positive bias stress (PBS) and negative bias stress (NBS), and only 0.8/1.3 V threshold voltage shifts are shown after PBS/NBS. In addition, the OTES-passivated transistors exhibit good mechanical reliability and maintain its electrical characteristics during the 10-k bending period, without drastic decline. These results demonstrate that the SAM passivation method is suitable for the fabrication of flexible high-performance metal–oxide electronic devices. [ABSTRACT FROM AUTHOR]