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A method for radio frequency oxygen (O2) plasma-assisted treatment of indium zinc oxide (IZO) films with a multistacked architecture fabricated by a low-temperature (200 °C) solution process is investigated. We demonstrate that radio frequency O2 plasma-assisted posttreatment technology can improve the mobility and stability of IZO thin-film transistors (TFTs). The activity layers were formed by spin coating and subsequently thermally annealed at a low temperature of 200 °C, followed by O2-plasma posttreatment process, to form the O2 triggered multistacked architecture. The TFT devices plasma-treated for 3 min exhibit improved electrical characteristics, with a mobility of 7.09 ± 0.24 cm2/Vs, an ON OFF ratio of (1.21 ± 1.22) $\times 10^{{6}}$ , a threshold voltage of $-0.22\,\,\pm \,\,0.35$ V, and a subthreshold swing of 0.34 ± 0.02 V/dec. The improved results offered by the O2 plasma treatment led to a higher mobility and ON/ OFF ratio compared to sample device without this process. The successful fabrication of radio frequency O2 triggered multistacked architecture-based IZO TFTs showing the practical potential of high-performance low-temperature solution-processed preparation technology and radio frequency O2 plasma-assisted treatment for electrical device application. [ABSTRACT FROM AUTHOR]

Cryogenic mobility enhancement, corres- ponding to the reduction of interfacial disorder, is always a research focus in Si-based MOS device manufacturing toward practical quantum computing chips. In this work, we report the dependency of MOSFET cryogenic mobility on reactive ion etching (RIE)-induced damages at 5–75 K. We discover that RIE will introduce a lot of atomic steps and charged traps at SiO2/Si interfaces or conducting channel boundaries during the mesa formation stage, severely degrading device mobility, especially at a low temperature. With a post-RIE high-temperature SiO2 regrowth process, the device cryogenic (1.8 K) peak mobility is enhanced to ~20314 cm2/($Vs$) at a small electron density of $1.05\times10$ 12/cm2, meaning the successful removal of RIE-induced extra effective scattering centers within the optimized device. Notably, our work presents the adverse impacts of RIE on MOS device cryogenic mobilities and provides a feasible integration flow to recover device performances, which may promote the evolution of Si-based MOS quantum dot computation. [ABSTRACT FROM AUTHOR]

Plasma-enhanced atomic layer deposition is used to fabricate compact tantalum (Ta)-doped titanium oxide (TiO2) thin films as electron transport layers (ETLs) and hole blocking layers for perovskite solar cells (PSCs). The effects of Ta-doped TiO2 with different annealing temperatures on film structure and electronic properties are researched. The experimental results exhibit that the substitutional Ta-doping into TiO2 (Ta content of ~1.5%) increases the stability of crystal structure and passivates the material defects, thereby improving the film quality. The annealed Ta-doped TiO2 films have a resistivity of approximately 6.5 $\boldsymbol {\Omega } \cdot $ cm which is three orders of magnitude lower than 3.4 $\times 10^{{3}}\,\, \boldsymbol {\Omega } \cdot $ cm of intrinsic TiO2. Finally, the annealing process eliminates the defects, and therefore, improves electron transport for PSCs, leading to a clearly enhanced fill factor (FF) of 0.77 and conversion efficiency of 19.62% when compared to that of undoped TiO2 ETL devices. [ABSTRACT FROM AUTHOR]

The ohmic contact resistance (${R}_{C}$), surface resistance (${R}_{S}$), and channel resistance (${R}_{\text {CH}}$) of hydrogen-terminated diamond (H-diamond) MOSFETs were investigated in this study. Planar-type and T-type H-diamond MOSFETs were employed to analyze them. Because no interspaces exist between the source–drain and gate electrodes for the T-type H-diamond MOSFETs, then ${R}_{S}$ is zero. Both planar-type and T-type MOSFETs show low leakage current densities and good operations. By considering the relationships between the total resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and 1/ $\vert $ gate voltage-threshold voltage $\vert $ , ${R}_{C}$ and ${R}_{\text {CH}}$ for the T-type H-diamond MOSFET at a gate voltage of −10.0 V are determined to be 13.8 and 21.8 $\Omega \cdot $ mm, respectively. As ${R}_{C}$ for both MOSFETs is the same, ${R}_{S}$ and ${R}_{\text {CH}}$ for the planar-type H-diamond MOSFET are deduced to be 90.0 and 15.8 $\Omega \cdot $ mm, respectively. ${R}_{S}$ accounts for 75.3% of ${R}_{ \mathrm{\scriptscriptstyle ON}}$ for the planar-type H-diamond MOSFET, which is the main reason for its lower drain current and extrinsic transconductance than those of the T-type MOSFET. Although ${R}_{S}$ is suppressed for the T-type H-diamond MOSFET, ${R}_{C}$ occupies 38.8% of ${R}_{ \mathrm{\scriptscriptstyle ON}}$. To further improve the performance of the H-diamond MOSFETs, it is important to eliminate ${R}_{S}$ and decrease ${R}_{C}$ to further improve the electrical properties of the H-diamond MOSFETs. [ABSTRACT FROM AUTHOR]

The ferroelectricity of Zr-doped HfO2 (HZO) thin films induced by low thermal budget annealing provides great potential to implement the ferroelectric functionalities into the back end of line (BEOL) process of the standard CMOS integrated circuits. However, most of previous works need high temperature annealing or long time annealing to acquire ferroelectricity. In this work, both annealing temperature and time are optimized to achieve optimal ferroelectricity of Hf0.45Zr0.55Ox films produced by thermal atomic layer deposition (TALD) and plasma-enhanced atomic layer deposition (PEALD). The results indicate that the TALD and PEALD films exhibit maximum double remanent polarization ($2{P}_{r}$) of ~36.8 and ~ $30.0 {{ \boldsymbol {\mu }}}\text{C}/$ cm2, respectively, after annealing at 330 °C for 300 s. Furthermore, the characteristics of the above annealed films are comprehensively compared. It is found that the PEALD film exhibits a higher maximum-dielectric-constant, a higher breakdown electric field, and better endurance against switching cycles than the TALD one, but more severe wake-up effects. This is ascribed to the factor that the PEALD film contains more tetragonal phase and less defects than the TALD one. In this article, the PEALD film has moderate ${P}_{r}$ and robust endurance, which is more promising for memory devices. [ABSTRACT FROM AUTHOR]

Heat generation in integrated circuits (ICs) has become a severe issue, which limits the utilization of miniaturized semiconductor devices in high-density 3-D IC technologies. Herein, Al2O3 was doped in ZrO2 thin films by plasma-enhanced atomic layer deposition (PEALD) to enhance their antiferroelectric (AFE) characteristics for highly reliable electrocaloric (EC) cooling applications. The cycling endurance in AFE behaviors of the Al:ZrO2 thin films under a high electric field of 5 MV/cm was significantly improved because of the enlargement of the energy bandgap with high resistance in trap-induced leakage current. Hence, the reliability of the EC effect of the 1% Al:ZrO2 thin film was examined with a negligible change in adiabatic temperature change ($\Delta {T}$) of 2.6% after a cycling endurance test of $10^{{6}}$ cycles. With the competitive cycling reliabilities in AFE and EC behaviors, devices with optimized Al2O3-incorporated ZrO2 thin films show significant potential for future nanoscale cooling systems in chip-level ICs. [ABSTRACT FROM AUTHOR]

A comprehensive study of drain current dispersion effects in $\beta $ -Ga2O3 field-effect transistors (FETs) has been done using dc and pulsed measurements. Both the virtual gate effect in the gate–drain access region and mobile traps under the gate are the most plausible explanations for the experimentally observed pulsed current dispersion and high-temperature threshold voltage shift, respectively. Unpassivated devices show significant current dispersion between dc and pulsed ${I}$ – ${V}$ response in gate lag measurements characterized by time constants in the range of 400–690 $\mu \text{s}$ both at room temperature and higher temperatures. The increasing time constant with temperature suggests a complex electron capture and emission process in the virtual gate. The reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. The effect of traps can be minimized by using surface passivation layers, in this case, silicon nitride, which shows significant improvement in the current dispersion. This work demonstrates the detrimental effect that the traps can have on the current dispersion, which significantly limits the high-frequency operation of the device. [ABSTRACT FROM AUTHOR]

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget (< 400 °C). In this regard, we investigated the low-temperature process for ferroelectric Hf0.5Zr0.5O2 (HZO) capacitor with the plasma-enhanced atomic layer deposition (PEALD). It was found that, with sufficient annealing time (>50 s) in low temperature (~ 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization (Pr) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different Pr states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured Pr drift behavior over time. [ABSTRACT FROM AUTHOR]

Greater than 190 °C continuous wave (CW) lasing is achieved from 905 nm high-efficiency vertical cavity surface-emitting lasers (VCSELs). The maximum power conversion efficiency (PCE) of 46.3% for 4 μm VCSELs was demonstrated under the ambient temperature of 30 °C. The maximum PCE decreases only 10% of its value from 30 °C to 90 °C, showing stable high-temperature characteristics. The thermal resistances and active region temperatures of the device versus ambient temperature are determined experimentally. Besides, size-dependent thermal characteristics are also analyzed by characterizing the spectral and spatial properties of devices with various apertures. It is found that the higher the ambient temperature is, the less the number of high-order modes is, and single fundamental mode operation can be realized in 4 μm VCSELs even at a relatively high temperature of 190 °C. The design and characterization of these high-temperature VCSEL devices might present the basis for future laser radar application. [ABSTRACT FROM AUTHOR]

We fabricate Ge:B-blocked impurity band (BIB) far-infrared detectors using near-surface processing techniques. The current–voltage (I – V) characteristics and the energy band structure are investigated. It is found that there are three interfacial barriers in Ge:B BIB detectors due to the bandgap narrowing effect. The barrier height can be adjusted by changing the doping concentration in the contact region of BIB detectors. A new dark-current-blocking mechanism is proposed that the interfacial barriers can block the transport of carriers at low temperatures. Moreover, the greater the barrier height, the stronger the blocking effect. Utilizing this new blocking mechanism, the I – V characteristics of Ge:B BIB detectors can be better explained. By increasing the barrier heights, the dark current is reduced significantly, almost six orders of magnitude within a certain voltage range, and the working temperature is increased from the usual 4.2–10 K, which is of great significance for extending the service life of BIB detectors on outer space observation platforms. Our findings will help to better design BIB detectors and improve their performance. [ABSTRACT FROM AUTHOR]

Details of a large-area-compatible sub-600 °C process for the fabrication of high mobility field-effect transistors on single crystalline silicon are presented. It is shown that lift-off and solid-phase-epitaxy (SPE) can be used in conjunction with plasma enhanced chemical vapor deposition (PECVD) to create MOSFET transistors with mobilities comparable to other high-performance techniques. Furthermore, use of an amorphous silicon/silicon oxynitride (SiOxNy) sacrificial bilayer is shown to make the process capable of self-aligned silicidation. The topography of the deposition is studied using cross-sectional scanning electron microscopy (SEM). It is shown that a successful lift-off can be achieved through the proper design of the sacrificial bilayer despite the high degree of step coverage generally exhibited by PECVD films. Cross-sectional transmission electron microscopy (TEM) is used to reveal the microstructure of the epitaxy and silicidation. Current-voltage characteristics of the fabricated transistors are presented and the field effect mobility of electrons on the fabricated devices is reported. The developed process is particularly useful in applications where high mobility transistors need to be built on silicon/nonsilicon hybrid platforms that exclude high processing temperatures. [ABSTRACT FROM AUTHOR]

Amorphous indium gallium zinc oxide (IGZO) deposited by plasma-enhanced atomic layer deposition (PEALD) thin-film transistors (TFTs) was fabricated using SiO2 gate insulators synthesized via plasma-enhanced chemical vapor deposition (PECVD, device A) or PEALD (device B). The electrical performance of B devices was higher than that of device A. The mobilities of A and B devices were 19.39 and 21.11 cm2/Vs, and the subthreshold slopes were 0.25 and 0.22 V /decade, respectively. In addition, the device reliability of A devices shows an abnormal threshold voltage (Vth) shift of –1.25 V under positive bias temperature stress (PBTS), caused by hydrogen diffusion from the gate insulator to the channel region near the source/drain electrode. However, B devices had a normal Vth shift of +2.87 V. X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared spectroscopy (FT-IR) results showed that PECVD SiO2 has a large amount of hydrogen bonding, such as Si-OH, compared to PEALD SiO2. Rutherford backscattering spectroscopy (RBS) and elastic recoil detection (ERD) measurement results confirmed that the hydrogen content of PECVD SiO2 was 2.24%, whereas that of PEALD SiO2 was lower at 1.45%. [ABSTRACT FROM AUTHOR]

This article investigates the stability of hydrogenated amorphous silicon (a-Si:H) p-i-n junctions employed as temperature sensors in lab-on-chip (LoC) applications. The devices have been tested under forward current injection and different temperatures (from room temperature up to 90 °C) in order to reproduce the practical operating conditions. Two sets of devices with different diborane concentrations in the p-doped layer have been investigated as a case study. For both sets, a temperature-drift error of 0.05 °C/h and a sensitivity around 3 mV/°C in the range between 30 °C and 90 °C have been achieved. These results demonstrate the device suitability as a thin-film temperature sensor integrated into LoC systems that implement thermal treatment of the biological samples as, for example, DNA amplification. [ABSTRACT FROM AUTHOR]

CMOS image sensors (CISs) in back-side-illuminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The back-side configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in back-side CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in back-side gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing E' donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation. [ABSTRACT FROM AUTHOR]

A neuromorphic electronic system requires the component devices to not only mimic typical synaptic behaviors but also be energy-efficient, together with excellent uniformity and tunable memory time. For this purpose, we fabricated amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors with plasma-enhanced atomic layer deposition AlOx:H dielectrics, successfully demonstrating typical synaptic behaviors, such as excitatory and inhibitory postsynaptic current, pair-pules facilitation, dynamic filter, learning and forgetting abilities and spike-timing dependent plasticity. In particular, such synaptic transistors exhibit ultralow energy consumption down to 3.18 fJ per synaptic event and tunable extensive memory time ranging from 76.6 ms to at least thousands of seconds. The ultralow energy consumption is realized by electron trapping and releasing at and near the interface between a-IGZO channel and AlOx:H dielectric under low voltages. By adjusting the concentration of oxygen vacancy defects in the a-IGZO domain adjacent to the interface by means of changing the growth temperature of the AlOx:H dielectrics, the memory time of the device can be further tuned on a large scale. Device flexibility was also demonstrated by fabricating the synaptic transistors onto polymer substrates at room temperature. [ABSTRACT FROM AUTHOR]

This paper reports wafer-level backside process technology, established with the intent to ensure stable operation of InP ICs in the submillimeter wavelength band, which generally suffer from ground bounce and substrate resonance. Our process consists of thinning a 3-in InP wafer, forming dense vias with interval cooling steps, backside metallization with single-level wiring and crack-free dicing. We investigate the effects of the backside process on InP-based heterojunction bipolar transistors and high electron mobility transistors. The results show that the backside process contributes to stable operation up to the 300-GHz range without any degradation of transistor characteristics. [ABSTRACT FROM AUTHOR]

This brief presents AlGaN/GaN high electron mobility transistor (HEMT) devices with improved thermal and dc current–voltage (${I}$ – ${V}$) performance using a novel method of obtaining a distributed channel device, i.e., the total semiconductor area between the ohmic contacts comprise conducting and nonconducting regions. A novel oxygen (O2) plasma treatment technique is used to realize the inactive or nonconducting regions. Multifinger devices with 1-mm gate periphery exhibit extremely low gate leakage currents below $0.2~\mu \text{A}$ /mm at a gate voltage of −20 V and an increase in the saturated output current by 14% at 20-V drain voltage. Moreover, performed dc ${I}$ – ${V}$ measurements at various ambient temperatures show that the proposed method not only increases the saturated output currents by over 10% for ${1} \times {100}\,\,\mu \text{m}^{{2}}$ gate devices but also significantly reduces their knee walkout voltage from 6 to 3 V at 300 K. These results show that this device design approach can exploit further the potential of the GaN material system for transistor applications. [ABSTRACT FROM AUTHOR]

The role of traps in the operation of Schottky barrier diodes is poorly understood. To explore this, SiC Schottky barrier diodes with a high density of near-interface traps were intentionally fabricated. By applying forward current stress, we demonstrate that the barrier height can be changed by changing the occupancy of the traps. The response time of these traps extends from seconds to hundreds of seconds. We also show that these traps can subsequently be emptied by thermal emission or by tunneling. The results are inconsistent with the existence of an interfacial oxide layer, which shows that the traps are distributed in both energy and lateral depth and, consequently, clarifies their role in creating the Schottky barrier. [ABSTRACT FROM AUTHOR]

We propose a simple and inexpensive strategy for fabricating aqueous route indium oxide thin-film transistors (In2O3-TFTs) at much lower annealing temperatures (${T}_{\text {a}}= 140\,\,^{\circ }\text{C}$) using NH3 plasma-assisted treatment (PAT) process to In2O3 film surfaces. During the NH3 PAT, the substrate temperature, plasma power, and gas flow were maintained at 140 °C, 50 W, and 100 sccm, respectively. The effect of a sequence of postannealing and PAT, namely, anneal after plasma (AAP)/anneal before plasma (ABP), was studied in detail. The results show that the NH3 PAT can promote the fracture of −OH, passivate the Vo, and increase the conductivity of In2O3 films at low temperatures. The AAP instead of ABP is a suitable method to realize high-performance low-temperature processed In2O3-TFTs on account of the higher oxidation degree, appropriate N doping, as well as more effectively H doping in AAP sample. The fabricated In2O3-TFTs based on AAP exhibited acceptable electrical performance of ~1.3 cm2/ $\text {V}\cdot \text {s}$ mobility and ~107 on/off current ratio at low temperatures. The novel method for fabricating the In2O3-TFTs opens a way for the development of nontoxic, low-cost, and low-temperature oxide circuitry. [ABSTRACT FROM AUTHOR]

It has been reported that Ar plasma treatment on the n-type 4H-SiC surface before metal deposition can reduce the contact resistance. In that work, the n+ layer was formed by ion implantation at room temperature (RT). In this paper, it is found that Ar plasma treatment on the high-temperature (HT) implanted n+ layer degrades but not improves the contact resistance. A composition of RT/low-energy and HT/high-energy ion implantation can achieve low sheet resistance of the n+ layer and low contact resistance simultaneously. A twofold mechanism is proposed that the amorphous interfacial layer produced by Ar plasma treatment reduces the Schottky barrier height and the defects generated by RT ion implantation enhance current conduction by trap-assisted tunneling. [ABSTRACT FROM AUTHOR]

The effects of chamber pressure (${P}_{\text {C}}$) on the structural and chemical properties of an indium gallium tin oxide (IGTO) channel layer were examined. Smoother and denser IGTO films were obtained with decreasing ${P}_{\text {C}}$ , which were explained based on the enhanced kinetic energy of sputtered particles due to fewer collisions with the plasma atmosphere. The resulting IGTO thin-film transistor exhibited a high mobility of 35.0 cm2/Vs, subthreshold gate swing of 0.17 V/decade, threshold voltage (${V}_{\text {TH}}$) of −0.45 V, and ${I}_{\mathrm {\scriptscriptstyle {ON/OFF}}}$ ratio >108, even at a low annealing temperature of 150 °C. [ABSTRACT FROM AUTHOR]

In this paper, we report a low thermal budget manufacturing method to produce highly rectifying Schottky diodes with ultrathin ZnO films grown at near room temperature by plasma-enhanced atomic layer deposition. A bottom Schottky electrode with Pt and a top ohmic electrode with Al/Au stacks were used for metallization. The resultant diodes demonstrated high rectifying ratios on the order of 106, relatively low ideal factor ${n}$ values of 1.36 ±0.05, effective Schottky barrier height $\Phi _{B}$ values of 0.77 ± 0.01 eV, and high breakdown fields of 1.67 MV/cm extrapolated from the current–voltage (${I}$ – ${V}$) characteristics at room temperature. These specifications are among the best-reported performance of Schottky diodes with ZnO thin films in nanoscale thickness. The interface at the Schottky contacts was investigated and revealed a lateral nonuniform distribution of interface defect states. A modified Richardson plot was used to deduce a mean barrier height ($\overline {\Phi }_{B{0}}$) of 1.25 ± 0.1 eV and an apparent Richardson constantc (${A}^{\ast \ast }$) of 11.64 A/cm2/K2. In addition, ${I}$ – ${V}$ characteristics of the diodes were observed to improve with aging. This newly developed, low thermal budget technique of ZnO Schottky nanodiodes is attractive for hybrid circuit systems and polymer electronics with integration constraints. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the influence of both source gas and deposition temperature in plasma-enhanced chemical vapor deposition (PE-CVD) for a SiO2 passivation layer on the electrical properties and reliability of a bottom-gate In–Ga–Zn–O thin-film transistor (IGZO TFT). Two gas chemistries consisting of SiH4–N2O–N2 and tetraethoxysilane (TEOS)–O2 were utilized as the source gases for the PE-CVD SiO2 deposition, and the deposition temperature (${T}_{D}$) was adjusted from 180 °C to 380 °C. The TFT properties were basically identical for both gas chemistries at ${T}_{D}$ of 180 °C. When ${T}_{D}$ increased to 300 °C or higher, the TFTs with the SiO2 passivation deposited by SiH4–N2O–N2 gas chemistry (SiH4-SiO2) drastically changed from the transistor to the conductor. In contrast, the TFT with TEOS-SiO2 passivation maintained its TFT characteristics even at ${T}_{D}$ of 380 °C, despite the degradation of subthreshold characteristics and a negative shift of turn-on voltage were observed due to an electron injection barrier lowering as ${T}_{D}$ increased to 310 °C or higher. We also revealed that a stacked SiO2 passivation that is deposited at a different ${T}_{D}$ is an effective technique to improve the performance and reliability of the IGZO TFT. [ABSTRACT FROM AUTHOR]

In this paper, the effects of N2O plasma treatment (PT) at various temperatures on the performances of InMgZnO (IMZO) thin-film transistors (TFTs) were investigated. As a result, the TFTs with N2O plasma-treated (10 W) IMZO channel layers at 100° for 10 min showed five times higher linear field-effect mobility compared to the untreated IMZO. The N2O PT did not cause any significant changes to the crystal structure, surface roughness of the IMZO thin films. However, an X-ray photoelectron spectroscopy study confirmed that the oxygen-vacancy defect density of the channel layer decreases via the N2O PT with temperature increased, and the reduction of oxygen vacancies leads to a decrease of off-current (IOFF). It was found out that the refractivity of the channel layer increases with PT temperature increased, and the improvement of the film density makes the on-current (ION) higher, resulting in high mobility and high I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} ratio. Our study suggests that moderate N2O PT temperature can be adopted to improve the device performances. [ABSTRACT FROM PUBLISHER]

Nickel germanide (NiGe) was formed from atomic layer deposition (ALD) Ni on Ge and a subequent annealing process; the Ni film with low resistivity ( 34~\mu \Omega \cdot \text cm ) at 15 nm was obtained by N2 + H2 plasma treatment after Ni precursor injection. The formed NiGe film showed low specific contact resistivity ( \rho c) values of 9.01 \mu \Omega \cdot \text cm^2 for an NiGe/n+Ge contact and 3.61 \mu \Omega \cdot \text cm^2 for an NiGe/p+Ge contact. These values were comparable to those obtained using sputtered Ni. In addition, the ALD process-based NiGe showed excellent thermal/electrical stability up to 600 °C. [ABSTRACT FROM AUTHOR]

Hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) compensation pixel circuits were fabricated on polyethylene naphthalate substrates at amax-imumtemperature of 170 °C. The typical a-Si:H TFTs showed a field-effect mobility ( \mu \text {FE} ) of 0.8–1.1 cm ^2 /Vs, a threshold voltage ( VT ) of 2–3.3 V, a subthreshold swing (SS) of ~0.65 V/decade, and an ON/OFF current ratio of 10^7 – 10^8 . Under DC gate-bias stress without compensation, the TFT drive current decreased by ~50% withoutmechanical strain and ~60% with applied tensile strain. The TFT circuits effectively compensated for the change in the TFT drive current to within 10% of the original drive current value under mechanically strained and unstrained states. The orientation of the TFT within the circuit was found to affect the circuit compensation; TFTs having a channel length perpendicular to the mechanical strain were found to have a 50% higher threshold voltage shift ( \Delta VT ) compared to devices parallel to the applied strain. [ABSTRACT FROM PUBLISHER]

Enhancement of the properties of zinc oxide (ZnO)-based Schottky diodes has been explored using a combination of plasma-enhanced atomic layer deposition (PE-ALD) ZnO thin films and silver oxide Schottky contacts deposited by reactive radio-frequency sputtering. The electrical properties of the ZnO thin films were systematically tuned by varying the deposition temperature and oxygen plasma time during PE-ALD to optimize the performance of the diode. Low temperature (80 °C) coupled with relatively long oxygen plasma time (>30 s) PE-ALD is the key to produce ZnO films with net doping concentration lower than 1017 cm−3. Under the optimal deposition conditions identified, the diode shows an ideality factor of 1.33, an effective barrier height of 0.80 eV, and an ON/OFF ratio of 3.11 \times 10^5 . [ABSTRACT FROM AUTHOR]

Amorphous InAlZnO (a-IAZO) films were grown by pulsed laser deposition at room temperature and annealed at various temperatures. The amorphous state of a-IAZO films is thermally stable at high temperatures up to 700 °C. The films exhibit a high visible transmittance above 95% and an appropriate resistivity on the order of 10^6~\Omega \cdot \text cm . As the annealing temperature increases, the optical bandgap and resistivity decrease in general. The microcracks form in films at an annealing temperature above 500 °C. The a-IAZO films annealed at 400 °C are suitable for channel layers of thin-film transistors (TFTs) and the devices demonstrate good performances with an on/off ratio of 10^8 and field-effect mobility of 2.2 \text cm^2\cdot \text V^-1\cdot \text s^-1 . The observations will provide useful physical insight into film properties and also offer basic design guideline for a-IAZO TFTs. [ABSTRACT FROM AUTHOR]

We describe the development and optical characterization of a planar medium infrared (mid-IR) InSb photodetector on a GaAs substrate technology, capable of integrating MESFETs, to demonstrate a new active pixel device architecture. Our results pave the way for the development of integrated mid-IR focal plane array circuits on a single chip. Device structures with areas down to 0.0016 mm $^{{ {2}}}$ were investigated. By deploying a silicon nitride passivation layer, we were able to reduce leakage current in reverse bias by up to 27% to yield an improved rectifier. Extensive optical characterization was carried out in the near- and mid-IR wavelength range. Responsivities of up to 3.54 A/W and quantum efficiency values above unity were obtained in the near-IR range as a consequence of illumination above the bandgap causing impact ionization. In the mid-IR range, responsivities of up to 0.97 A/W were observed. The bandwidth of the devices proved compatible with video-rate standard sampling rates. [ABSTRACT FROM PUBLISHER]

We investigated the SiN/gallium nitride (GaN) interface properties formed by the microwave-excited plasma-enhanced chemical vapor deposition (PECVD) with SiH4/N2/H2 gases. The interface and insulating properties of SiN films on GaN formed by the microwave-excited PECVD strongly depend on SiH4 flow rate. Although the interface trap density is lower than 10^11 cm ^\mathrm -2 eV ^\mathrm -1 at the relatively high SiH4 flow rate of 1 sccm, the breakdown electric field is very low ( $\sim 1$ MV/cm). Using the SiH4 plasma pretreatment before the stoichiometric SiN deposition, both low interface trap density and high breakdown voltage greater than 2 MV/cm are obtained. In this case, the clearly ordered Ga bonding near the SiN/GaN interface is estimated by an electron energy loss spectroscopy. The formation of SiN film on GaN using the microwave-excited PECVD is a very useful technique for the high-quality interface properties. [ABSTRACT FROM AUTHOR]

To identify the individually optimized thermal annealing conditions for reducing the contact resistivity between highly Ga-doped ZnO (GaZnO) and doped-GaN and for improving the electrical and optical properties of GaZnO, the results of the one-step and two-step growth/annealing processes of GaZnO at various growth and thermal annealing temperatures are compared. The one-step (two-step) process corresponds to the condition of thermal annealing for the whole GaZnO layer (only for a 10-nm GaZnO layer of the first-step growth). The two-step process always results in lower contact resistivity on either p-GaN or n-GaN at any annealing temperature. Lateral and vertical light-emitting diodes (LEDs) with GaZnO layers on the top are fabricated to show that the LED samples with the two-step process have the lower device resistance levels, higher emission efficiencies, and weaker efficiency droop effects, when compared with those with the one-step process. In the lateral LED sample with the two-step process, the combination of the effective atomic interdiffusion at the GaZnO/p-GaN junction under the optimized annealing condition and the preservation of the superior electrical property in the major GaZnO layer without annealing leads to its better performance, when compared with that of the lateral LED sample with the one-step process. [ABSTRACT FROM AUTHOR]

We report high-performance homojunction amorphous-indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) with low-resistive a-IGZO source/drain (S/D) electrodes. The a-IGZO S/D electrodes are selectively treated with high-power NF3 plasma, which reduces their resistivity from \sim 16 to 5.5 \times 10^{\vphantom {R^{R^{}}}{-3}}~\Omega \,\cdot \, cm. X-ray photoelectron spectroscopy indicates an increase in weakly bonded oxygen and a substantial amount of indium–fluorine and zinc–fluorine bonds at the a-IGZO top surface (extending to \sim 7$ nm into the bulk) after plasma treatment. Temperature-dependent conductivity measurements show metallic behavior of the a-IGZO after treatment. It is concluded that fluorine atoms substitute for oxygen atoms—generating free electrons in the process and/or occupy oxygen vacancy sites—eliminating electron trap sites. As a result, the homojunction TFTs show good ON-state characteristics with typical field-effect mobility, subthreshold gate-voltage swing, and turn-ON voltage of 19 ± 1 cm ^{2} / \text{V}\,\cdot \,\text{s} , 178 ± 30 mV/decade, and −3.2 ± 1.5 V, respectively. Good stability at high temperature and under bias and light stress are also exhibited by the homojunction TFTs, verifying a stable doping effect by the NF3 plasma treatment. [ABSTRACT FROM PUBLISHER]

The thermal behavior of several electrically conducting solids under high incident electron fluence in high vacuum was evaluated. At electron energies of up to $\sim 200$ keV, the depth-dose relationship for electron penetration into the materials was considered, and the resulting energy deposition profile from the surface was revealed to extend to a maximum of \sim 175\mu \text{m} below the surface depending on the anode material. Black body radiation is considered as the major mechanism that balances the power deposited in the material on the timescales of interest. Comparing the radiated power density at the sublimation temperature for different materials, metallic/nonmetallic, revealed that pyrolytic graphite anodes may radiate over 20 times more power than metallic anodes before failure due to sublimation. In addition, transparent pyrolytic graphite anodes (with a thickness on the order of several tens of micrometer) potentially radiate up to 40 times that of metallic anodes, since heating by the electron beam is approximately uniform throughout the thickness of the material, thus radiation is emitted from both sides. Experimental results obtained from titanium and pyrolytic graphite anodes validate the thermal analysis. [ABSTRACT FROM AUTHOR]

GeOx/Ge interfaces are fabricated by plasma postoxidation of Al2O3Ge (100) structures at 300^\circC and room temperature (RT). It is found that reduction of oxidation temperature results in a significant decrease of the GeOx/Ge interface roughness and a slight increase of the interface trap density. The Ge p- and n-channel MOSFETs with the GeOx/Ge interfaces oxidized at the RT provide 20% and 25% enhancement, respectively, of high field hole and electron mobilities than those of MOSFETs oxidized at 300^\circC. This mobility enhancement is attributable to the reduction of GeOx/Ge interface roughness, which has been proven by theoretical calculation of surface-roughness-limited mobility using the real MOS interface roughness directly extracted from transmission electron microscopy results. As a result, high hole and electron mobility of 179 and 378 cm^2/Vs, respectively, have been obtained at a Ns of 10^13~cm^-2 in MOSFETs fabricated by the RT plasma postoxidation. [ABSTRACT FROM AUTHOR]

This paper proposes a long last sustain waveform to improve the high-temperature misdischarge in an AC-PDP. We have confirmed that, when applying the interval time during which the X electrode and the Y electrode are grounded before the reset period in the next subfield after the sustain period at high temperature, the VA minimum voltage is reduced. The interval time reduces the probability of exoelectron emission at high temperatures. Therefore, the interval time can improve the high-temperature misdischarge. However, due to the nature of the ADS driving method, there are limitations when increasing the driving time. Thus, we proposed the long last sustain waveform, in which either the X electrode or the Y electrode is applied to VS voltage, instead of the interval time. The VA minimum voltage is significantly decreased, when the long last sustain waveform was applied within the same interval time, rather than grounding the X and Y electrodes. In particular, the effect of the X long last sustain waveform showed the best results. We also proposed the ascending X long last sustain waveform to optimize the length of the long last sustain waveform according to each subfield. The ascending X long last sustain waveform further reduced the VA minimum voltage. In this paper, the VA minimum voltage can be decreased to approximately 12 V, by applying the proposed ascending X long last sustain waveform, in comparison with the existing drive method, at higher temperatures. [ABSTRACT FROM PUBLISHER]

Because of the rapid diffusion of hydrogen in zinc oxide even at a relatively low temperature, zinc-oxide-based thin-film transistors (TFTs) with hydrogen-doped source/drain regions suffer from degraded thermal stability. The use of boron, which is a heavier and a more slowly diffusing dopant, is systematically investigated as a replacement of hydrogen. Its effectiveness as a dopant has been studied in terms of a range of process conditions, including its implantation dosage and the subsequent heat treatment temperature, time, and ambience. The lowest resistivity of 2 \m\Omega\-cm has been obtained at a boron dose of \10^16/\cm^2. Self-aligned top-gated zinc-oxide TFTs with source/drain regions doped with implanted boron are shown to be more stable than those doped with hydrogen, even when subjected to the relatively high temperature needed for the formation of a good-quality passivation layer. [ABSTRACT FROM PUBLISHER]

We have fabricated submicrometer ultralow-power thin-film transistors (TFTs) with stack gate dielectric structure formed by the nitric acid oxidation of Si (NAOS) method. A 1.8 nm NAOS \SiO2 layer effectively blocks the leakage current, and consequently, the thickness of a gate oxide layer deposited on the NAOS \SiO2 layer can be made as thin as 20 nm. Because of the thin gate oxide layer, submicrometer TFTs with gate length in the range of \0.6–\0.9 \ \mu\m can be fabricated. The operation voltage of the TFTs can be set as low as 1.5 V because of the low threshold voltages (i.e., -0.6 V for P-ch TFT and 0.6 V for N-ch TFT). The drain current versus source–drain voltage curves possess an ideal feature with sufficiently high saturation currents even at 1.5 V operation voltage. The drain current versus gate voltage curves show a sharp current increase, and the subthreshold swing value is \sim80 mV/dec for both P-ch and N-ch TFTs. The on/off ratio is \sim \!\!\10^9 for both P-ch and N-ch TFTs, and the channel mobility is \sim\!\!\100 \ \cm^2/\V\!\cdot\!\s for P-ch TFT and \sim\200 \ \cm^2/\V\!\cdot\!\s for N-ch TFT. [ABSTRACT FROM AUTHOR]

The discharge characteristics, particularly the address discharge characteristics, were examined relative to an ambient temperature from -\5\ ^\circ\C to +\65\ ^\circ\C in an ac plasma display panel. As the ambient temperature increased, the statistical delay time decreased due to an increase in the exoelectron emission from the MgO surface by thermal activation. In contrast, the formative delay time increased due to an increase in the wall voltage variation during an address period. It was also found that the wall voltage variation during an address period depended on the level of the scan high voltage. Therefore, a temperature-adaptive driving waveform with multiscan high voltages is proposed to produce a stable address discharge irrespective of a variable ambient temperature. [ABSTRACT FROM PUBLISHER]