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The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°. [ABSTRACT FROM AUTHOR]

In this work, we report the impact of source region’s random dopant fluctuations (RDFs) induced variability on n-type silicon double gate (DG)-TFETs via 3D-device simulation. We have observed that source region’s RDF induces strong variability in the analog and RF figures of merit (FOMs) of the devices. This is the first report showing detailed impact of RDF on DG-TFET device and based circuit. The impact of RDF is analyzed by taking RDF only in source region as tunneling barrier width depends mostly on source doping and so does the ON-state current. The variation of analog and RF FOMs, such as transconductance $({g}_{m})$ , transconductance generation factor $({g}_{m}/{I}_{d})$ , output resistance $({R}_{o})$ , intrinsic gain $({g}_{m}{R}_{o})$ , capacitances $({C}_{{gs}}$ , ${C}_{{gd}}$), gate delay $({T}_{m})$ , cutoff frequency $({f}_{T})$ , and subthreshold swing (SS), is reported. We benchmark the device analog and RF performance of the RDF sample with respect to continuum one. On the basis of observed effective deviation in characteristics, common-source amplifier circuit is simulated to analyze the deviation in voltage-transfer characteristic (VTC) and gain–bandwidth product (GBWP). [ABSTRACT FROM AUTHOR]

Vertical, gigapascal-level mechanical stress (MS) is induced at different locations along the channel of 40-nm effective gate length planar CMOS field-effect transistor (FET) devices and electrical parameter variations are investigated. In both p-and n-channel devices, the threshold voltage, mobility, and ON-current are seen to change proportionally with the additional MS, while gate-induced drain-leakage current increases exponentially. A clear effect of the location of the applied force along the source–drain direction is observed on the transistor parameters. Simulations show that a mechanical load located closer to the FET source induces a stronger asymmetry between the source and drain stresses. This leads to asymmetric subband splitting/warping, which reduces the backscattering rate at the source, in line with theoretical predictions on the importance of the channel barrier near the source for current in quasi-ballistic transistors. [ABSTRACT FROM AUTHOR]

A novel GaSb/GaAs type-II heterojunction TFET on SELBOX substrate (HJ-STFET)-based dielectric-modulated ultrasensitive label-free biosensor has been demonstrated in this article. The SELBOX substrate has been used in the proposed TFET-based sensor to reduce the lattice heat and improve the ${I}_{\mathrm {ON}}/{I}_{{\mathrm {OFF}}}$ ratio. Cavities in the gate oxide of the TFET are created to form dual-cavity (DC) HJ-STFET structure. These cavities contain the biomolecules to be sensed through the principle of gate-dielectric modulation. To validate the results, the analytical modeling of surface potential has been compared to simulated outcomes for different dielectric constant values of biomolecules. The threshold voltage sensitivity (${S}_{VT}$) and ${I}_{\mathrm{ON}}/{I}_{\mathrm{OFF}}$ sensitivity parameters of the proposed DC-HJ-STFET structure have been thoroughly investigated considering different biomolecules. The proposed DC-HJ-TFET structure is shown to have a higher current sensitivity ($\sim 6.67\times10$ 11) and threshold voltage sensitivity (0.37 V) values over some recently reported TFET-based biosensors. Finally, we have verified the drain and back gate biasing, as well as linearity fit verification, on the proposed biosensor’s performance. [ABSTRACT FROM AUTHOR]

A silicon single-photon avalanche diode (Si-SPAD) with a deep multiplication zone was fabricated using 0.11- $\mu \text{m}$ -CMOS technology. Deep n-well (DNW) implantation with three energy levels was performed to prepare a deep junction, and the highest breakdown voltage (${V}_{\text {BR}}$) and lowest dark count rate (DCR) were obtained at the highest DNW implantation energy. In addition, devices with different structures were manufactured: a shallow junction, deep junction with mask DNW, deep junction with mask DNW without shallow trench isolation (STI), and deep junction with blank DNW. The blank DNW structure exhibited a lower edge breakdown risk and less deviation between samples compared to those of mask DNW structure in terms of the ${V}_{\text {BR}}$ and DCR. Moreover, a new edge breakdown risk was observed between DNW and p-well (PW) in the DNW blank structure, which could be alleviated by adjusting the PW sizes. According to the measurement results, the STI structure was preferable in terms of fill factor. Measurements were obtained from real fabricated test device structures, and technology computer-aided design (TCAD) for various factors associated with Si-SPADs with deep multiplication structures was performed. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p+/i/n+ nanowire via well-calibrated TCAD simulations. The 4F2-like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (106 at 25 °C and 1-ns read duration) of state “1” to state “0,” and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of ~3 s at 25 °C. The long RT, considering a severe WL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (~3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices. [ABSTRACT FROM AUTHOR]

In this article, we propose silicon-nitride-pillar (SNP) and silicon-pillar (SP) structures that can be applied to a COP structure, which is the mainstay of the recent 3-D nand flash structure, by applying the IGZO-nitride-pillar (INP) and IGZO-pillar (IP) structures that showed very good erase performance announced in previous studies and verify them through device simulation. The proposed structure can supply holes through pillars formed by epitaxial growth in the P+ crystal silicon subregion, which is generally used in the existing semiconductor manufacturing process. As a result of simulation, the proposed structure showed a fast erase speed of 10 $\mu \text{s}$ , and the SNP structure could prevent breakdown by appropriately controlling the thickness of the silicon nitride barrier. In addition, the SP structure with the silicon nitride barrier removed was able to maintain a fast erase speed even when the thickness of the pillar was reduced to 5 nm. Therefore, it was confirmed that the proposed structure can operate more than 100 times faster than the existing GIDL erasing structure if proper structure and operating conditions are secured. [ABSTRACT FROM AUTHOR]

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $\mu \text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value. [ABSTRACT FROM AUTHOR]

In this work, a novel one-transistor active pixel sensor (1T-APS) with adjustable self-adaptive sensitivity enabled by floating source/drain (S/D) is demonstrated on 22-nm fully depleted Si-on-insulator (FD-SOI) platform. Additional control gates (CGs) with floating S/Ds are incorporated into the sensor, which are parallel to the sensing gate (SG). For weak illumination, the CG channel keeps closed so that the photoresponse is only active for SG controlled region, resulting in high linear sensitivity, while the CG channel will automatically turn on when the illumination is strong enough. Correspondingly, the CG controlled region is connected with SG controlled region for photoresponse together, resulting in a relatively lower linear sensitivity. For very strong illumination, the 1T-APS will automatically switch to logarithmic response mode due to the activated virtual photodiode in the FD-SOI substrate. The sensitivity transition points in the linear–linear region and the linear–logarithmic region can be further adjusted by the bias of CG and back gate, respectively. The adjustable self-adaptive sensitivity indicates the great potential of the proposed 1T-APS for high-quality image sensing. [ABSTRACT FROM AUTHOR]

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

Three silicon nanowire (SiNW) field effect transistors (FETs) with 15-, 12.5- and 10.6-nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental ${I}_{D}$ – ${V}_{G}$ characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in $\mathit {k}$ -space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed ${I}_{D}$ – ${V}_{G}$ characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations. [ABSTRACT FROM AUTHOR]

In this article, we introduce a novel vertical tunneling transistor that uses two germanium source regions and a T-shaped silicon channel and investigate its performance for low-voltage digital/analog and biosensing applications, by using numerical simulations. The switching performance of the device is improved by employing two highly doped N+ pocket regions next to the germanium source regions. To increase the validity and accuracy of the obtained results, calibration with the results of an experimental report is carried out. As a biosensor, the performance of the device in detection and separation of different biomolecules is studied, too. Some of the main achievements among the various digital/analog and biosensing performance metrics are $I_{on} = 88.9 ~\mu \text{A}/\mu \text{m}$ , SS $_{\mathrm{avg}} =25.28$ mV/dec, ${f}_{T} =192.64$ GHz, and ${S}_{I_{D}}= 6.95\times10$ 5. [ABSTRACT FROM AUTHOR]

This article investigates the effect of proton radiation on the mechanical structure of microelectromechanical systems (MEMS) inertial devices, including gyroscopes and accelerometers. To distinguish the effect of radiation on MEMS element and the circuit, the mechanical part and electronics are shielded by an aluminum barrier separately in the experiments where 7-Mev protons with a dose rate of $1\times10$ 7– $1\times10$ 9 p/(cm $^{2}\cdot s$) are utilized. The results show that proton radiation on the MEMS mechanical structure may not cause device function failure or output drift but increase the white noise. The angle random walk and bias stability of the MEMS gyroscopes exhibit a linear relationship with the proton dose rate. Based on these observations, we propose a particle collision model to describe this effect for the first time. The radiation noise can dominate the output noise when the dose rate is more than $3.1\times10$ 7 p/(cm $^{2}\cdot s$) for the custom-designed gyroscopes. However, this phenomenon is not found in the accelerometers since the radiation noise did not exceed the inherent device noise level. Finally, in order to evaluate the effects of proton radiation caused by the application-specific integrated circuit (ASIC), the ASIC is exposed alone to protons, which makes the device’s output abnormal such as spikes, drift, and even failure. These findings discriminate the different effects of MEMS structure and circuit on device performance under irradiation and also give guidance to determine the radiation failure mechanism of MEMS inertial devices. [ABSTRACT FROM AUTHOR]

In this work, the impact of low-pressure chemical vapor deposition (LPCVD)-SixNy stoichiometry on 2-D electron gas (2-DEG) transport characteristics of the AlGaN (3.9 nm)/GaN heterostructure and the underlying mechanism of increased 2-DEG density are studied, which reveals a new perspective of improving AlGaN/GaN performance by dielectric engineering. Among the AlGaN/GaN passivated by the LPCVD-SixNy with tailored stoichiometry, the 2-DEG density and mobility in the Si-rich sample were significantly improved by 25% and 16.3% compared with the N-rich sample, respectively. Accordingly, 30% reduction in sheet resistance of AlGaN/GaN heterostructure is obtained. The potentially strained-induced enhancement of piezoelectric polarization and corresponding 2-DEG variation by the SixNy passivation layer was excluded by the negligible change in Raman spectra among the different samples. Alternatively, the X-ray photoelectron spectroscopy (XPS) showed that the varied stoichiometry of the SixNy enables a discernible modulation effect of heterostructure energy-band. The reduced surface potential in the sample passivated by Si-rich SixNy attributes to the pronounced Ga dangling bonds (DBs) at the LPCVD-SixNy/AlGaN interfaces, which provides the near-conduction band (NCB) states and leads to enhanced 2-DEG accumulation. [ABSTRACT FROM AUTHOR]

The low-field hole mobility in p-type inversion-mode silicon (Si) and germanium (Ge) nanosheet (NS) transistors is rigorously calculated by a physics-based theoretical model, where momentum scatterings from phonons, charged impurities, and surface roughness are all considered. With a holistic physical picture of carrier scattering mechanisms, the effects of material, crystal orientation, channel width, strain/stress, and temperature are investigated comprehensively by the in-house developed numerical simulator. This sound and prospective theoretical work paves the way for clarifying the physics of achieving high hole mobility in ultrascaled NS channels, presenting some valuable insights and guidelines about the device design and fabrication for the next-generation CMOS technology. [ABSTRACT FROM AUTHOR]

The field effect diode (FED) is an attractive device to use in various digital and analog applications, but all previously proposed FEDs are based on the silicon-on-insulator (SOI) technology. In this article, a bulk version of FED (BFED) is proposed for the first time. Both SOI-FED and BFED are simulated using TCAD tools as a semiconductor drift-diffusion solver. The proposed bulk FED can operate as well as a regular SOI-FED. Most sensitive parameters in the design of the BFED are doping and thickness of $\text{p}^{+}$ -drain and $\text{n}^{+}$ -source. The effect of these parameters is investigated on the output characteristics of the BFED. [ABSTRACT FROM AUTHOR]

As a transmitter power amplifier (PA), the electrical output characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs) are closely related to the drain current versus drain voltage (${I}_{d}$ – ${V}_{d}$) characteristics. Any abnormalities in the ${I}_{d}$ – ${V}_{d}$ characteristics will seriously affect device performance. Therefore, many groups have investigated the kink effect of GaN HEMTs. One of the commonly used measurement methods of the kink effect is the ${I}_{d}$ – ${V}_{d}$ forward and reverse sweep. In this study, we used the same method for Al2O3/Si3N4–AlGaN/GaN metal–insulator–semiconductor HEMT (MIS HEMT) devices. We found that not only did the kink effect occurred but ${I}_{d}$ also increased abnormally during the reverse sweep and after a series of electrical measurements. At the end of the forward sweep, impact ionization caused by a high ${V}_{d}$ generated electron–hole pairs and some holes accumulated under the gate region, which caused the negative shift of the threshold voltage (${V}_{\text{Th}}$), leading to an abnormal increase in ${I}_{d}$ during the reverse sweep. [ABSTRACT FROM AUTHOR]

A novel method to fabricate the oxidized silicon-terminated (C–Si–O) diamond metal-oxide-semi- conductor field-effect transistors (MOSFETs) by replacing the retained SiO2 masks with an atomic layer deposition (ALD)-Al2O3 film as the main gate insulator was proposed for the first time. Compositional analysis across the SiO2 masks and on the air-exposed C–Si–O (111) diamond surface has been carried out by utilizing secondary ion mass spectroscopy (SIMS) and Auger electron spectroscopy (AES) techniques, respectively. Furthermore, we revealed that, under selectively epitaxial growth of diamond through a SiO2 mask, a carbon-rich film was formed on SiO2 and C–Si bonding was realized at the SiO2/(111) diamond interface. The fabricated device with a source and drain distance (${L}_{SD}$) of $3 \,\mu \text{m}$ exhibits a distinct threshold voltage (${V}_{TH}$) of −5.6 V and a maximum drain current density (${I}_{D\_{}{MAX}}$) up to −311 mA/mm, which is a record value among normally-off single-crystalline diamond MOSFETs to date. In the case of having ALD-Al2O3 as the main gate insulator, normally-off operation of the C–Si–O diamond MOSFETs has a stark contrast with the typically normally-on performance of the hydrogen-terminated (C–H) diamond MOSFETs, which is mainly due to the smaller negative electron affinity of C–Si–O diamond compared with that of C–H diamond. These results indicate that the proposed C–Si–O (111) diamond MOSFETs with excellent normally-off operation and large drain current density are promising to fulfill the requirements of fail-safe and current drive capabilities in power device applications. [ABSTRACT FROM AUTHOR]

Gate sidewall spacers, a pathway to the fringing fields, play a crucial role in the device design. In this article, using well-calibrated TCAD models, we have explored the impact of a sidewall ferroelectric (FE) spacer on a negative capacitance (NC) FinFET. In the proposed study, the FE layer is present beneath the gate electrode and at the spacer region that operates in the NC region. Through three novel FE–dielectric (FE–DE) spacer configurations, we found that proficient electrostatic control can be attained with the optimized stacked placement of the spacers. The fringing fields alter the FE polarization present at the spacer stack and modulates the channel charge, which is a prime objective of this work. Furthermore, we have varied the FE parameters, drain doping, and extension length to optimize the proposed FE–DE spacer configurations. We have done mixed-mode simulations to design an inverter and a three-stage ring oscillator to emphasize our results. The optimized spacer configuration shows~3.9% overshoot due to higher gate capacitance (${C}_{GG}$); however, the $I_{\mathrm{ON}} / I_{\mathrm{OFF}}$ ratio is approximately twic than that of the baseline counterpart. The results reveal that the optimized spacer configuration also mitigates the negative differential resistance (NDR), which allows the NC-based devices to be an efficient candidate for analog applications. [ABSTRACT FROM AUTHOR]

In this article, we report on the electrical performance of AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using gold (Au)-free process, after being transferred onto flexible Kapton tape. The transfer process followed in this work can be easily scaled-up to wafer level and involves a relatively simple process of epoxy bonding of the thin device layer onto the Kapton substrate. Electrical characteristics of the flexible HEMT indicate 5%–10% higher ON-current when bent with a radius of curvature of 2.1 cm (at low drain bias voltages), while the OFF-state performance remains unaffected. Initially, 2-DEG properties such as field-effect mobility and carrier concentration have been extracted. While FATFET measurements indicate negligible change in field-effect mobility, ${C}$ – ${V}$ measurements indicate $\sim 10$ % reduction in 2-DEG concentration after transfer. The comparison of the electrical characteristics of Au-free HEMTs indicates $\sim 50$ % reduction in the ON-current of the transferred devices. This is attributed to heating of the transistor channel caused due to low thermal conductivity of the polymer Kapton tape. Electrical characteristics of the flexible HEMT carried out under drain pulsing further support the above observation. This work is among one of the few reports on Au-free AlGaN/GaN HEMT operation on flexible Kapton tape. [ABSTRACT FROM AUTHOR]

A high-resistance Si-based AlInGaN/GaN heterojunction epitaxy specifying AlN/AlGaN laminated buffer layers and AlInGaN barrier layer with 45% Al composition was successfully produced to show a high electron density of $1.93\times10$ 13 cm−2 and mobility of 2829.24 cm2/Vs and based on which a novel varistor is proposed in this work. The varistor is composed with a narrow groove etched into the GaN channel and Ti/Al/Ni/Au (20/130/50/50 nm) metal electrodes attached to the epitaxy surface. The processes to fabricate the varistor were investigated in-depth, including a narrow groove etching based on dry-wet hybrid cyclic etching technology employing oxygen plasma and hydrochloric acid and an optimized metal electrodes ohmic contact process based on HCl:H2O = 1:10 liquid surface treatment and annealing at 875 °C to achieve a low contact resistance of $0.45 \Omega \cdot $ mm. The device with a groove width of $3 ~\mu \text{m}$ and length of $600 ~\mu \text{m}$ exhibits typical varistor characteristics with opening voltage ($V_{{\mathrm {ON}}}$) of 33.8 V and a high nonlinear coefficient of 82.97 in the current range from 1 to 10 mA. The $V_{{\mathrm {ON}}}$ value of the varistors is directly proportional to the narrow groove width with a scaling coefficient of 10.18 V/ $\mu \text{m}$ , which means $V_{{\mathrm {ON}}}$ can be adjusted by altering the width of the groove. The varistor with a simple structure could be used in GaN on-chip integrated switches, electro-static discharge (ESD) protection, and other applications. [ABSTRACT FROM AUTHOR]

The cross-sectional scaling-induced electronic property variations of the Ge and Si nanowires are studied numerically. After removing extra atoms from bulk materials to build the nanowires, not only the lateral quantum confinement is enhanced, but also the cross-sectional size will expand due to the breaking of the intrinsic strain balance. Compared with Si, the strain release-induced size expansion is more obvious in the Ge nanowires, shrinking the bandgaps and thus providing another bandgap modulation direction relative to the quantum confinement. At specific sizes, the strain release effect dominates the modulation and reduces the bandgaps of Ge nanowires even below the bulk value, while the reductions in Si nanowires are negligible, enlarging the band offsets of their heterostructures. As an application, the Ge/Si heterostructure tunnel FET (TFET) is designed and the TCAD simulation reveals a subthreshold swing (SS) of 13.8 mV/dec and an ON-state current of $93 ~\mu \text{A}/\mu \text{m}$ , three orders of magnitude larger than that using the bulk materials. [ABSTRACT FROM AUTHOR]

While considering the low power demand as a fundamental bottleneck for nanoscale devices, this work comprehensively investigates a novel concept that incorporates the area-scaled tunneling in a nanosheet field-effect transistor (NSFET) at a 5-nm technology node. Integrating the area scale tunneling phenomenon with NSFET provides improved electrical performance. We observed ${\sim } 50\times $ improvement in drain current and $\sim 2\times $ improvement in subthreshold slope (SS) by incorporating epitaxial layer over the source region underneath the gate. Furthermore, 100 mV of the shift in tunneling onset voltage (${V}_{T, \mathrm{\scriptscriptstyle ON}}$) is also noted when source doping increases from $1 \times 10^{{18}}$ to $1 \times 10^{{20}}$ cm $^{-{3}}$. The gate–source overlap (${L}_{\text {OV}}$) significantly improves the transconductance without sacrificing the output resistance. It is examined that epitaxial layer thickness (${T}_{\text {EPI}}$) of 3–4 nm gives the best possible drive current for the proposed device. However, the OFF current exhibits an inversely proportional relation with ${T}_{\text {EPI}}$. It is worth highlighting that optimum ${T}_{\text {EPI}}$ can be determined by only considering the suitable epitaxial layer doping profile (${N}_{\text {EPI}}$). A linear shift in ${V}_{T, \mathrm{\scriptscriptstyle ON}}$ of the proposed device with work function (WF) is also reported in our work. Finally, the concept of multiple stacking is explored to boost the device’s performance. Including the presented device design guidelines, the ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ ratio of $\sim 4.5 \times 10^{{8}}$ with an average SS of ~20 mV/dec is successfully demonstrated for the proposed device. [ABSTRACT FROM AUTHOR]

Adding interbridges (IBs) as additional channels between nanosheets (NSs) can reduce not only the maximum temperature in local hotspot of device but also the junction temperature difference among channels. The Si0.98Ge0.02 IBs added into pSi NSs reduce the maximum device temperature by 9 °C and the maximum junction temperature difference among channels by 5 °C. This is attributed to the higher thermal conductivity of IBs than internal spacer (7 versus 2 W/K/m) to increase heat exchange between NSs. Further increasing the width of Si0.98Ge0.02 IBs from 5 to 10 nm can cause 14 °C reduction in the maximum device temperature and 6 °C reduction in the junction temperature difference due to 1.1X enhancement of heat exchange between NSs. Increasing the height of Si0.98Ge0.02 IBs from 20 to 30 nm can reduce the maximum device temperature by 22 °C but slightly increase the junction temperature difference by 1 °C due to 30% decrease in the heat exchange between NSs. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS). [ABSTRACT FROM AUTHOR]

In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet field-effect transistors (NSFETs) by locally inserting an oxide material only under the gate region. NSFETs with punchthrough stoppers (PTSs) doping of the substrate region have been widely adopted to reduce substrate leakage; however, band-to-band tunneling (BTBT) under negative bias remains a serious problem in such devices. By only inserting the oxide material under the gate region, the electric field from the gate to the drain–substrate junction is dispersed. Furthermore, since there is no oxide material under the source and drain (S/D) region, there is no stress reduction along the channel direction coming from the silicon-on-insulator (SOI) structure. We performed technology computer-aided design (TCAD) simulations, and the results show that the proposed structure effectively reduces both the tunneling current in the NSFET with PTS structure and the OFF-current in the NSFET without PTS structure, compared with those of conventional NSFETs. [ABSTRACT FROM AUTHOR]

Silicon-based conventional photodetectors have always been a vital part of many electronic and optoelectronic circuits because of their low fabrication cost, high device performance, and simple configuration. However, due to the relatively poor light–matter interaction and narrow bandgap in Si, these photodetectors generally suffer from a certain compromise in their photoresponsivity as well as broadband photoresponse. Here, a novel approach of coupling reduced-graphene oxide (rGO) decorated $\beta $ -In2S3 with Si has been demonstrated. $\beta $ -In2S3 thin film has been grown by a direct and transfer-free method on Si substrate and rGO has been drop-casted on $\beta $ -In2S3. This introduction of a double-heterojunction architecture results in a photoresponsivity of ~30.41 A/W at 625 nm at an applied voltage of −4 V with the response and recovery times of 60 and $40 ~\mu \text{s}$ , respectively, along with a broadband response in the wavelength range of 400–1200 nm. The rGO acts as an efficient hole transporting layer, which readily reduces the recombination of the photogenerated electrons and holes, leading to high photoresponse. These results highlight a simple and cost-effective strategy to construct high-performance broadband photodetectors, which can be useful in future optoelectronic devices. [ABSTRACT FROM AUTHOR]

In this work, low frequency noise (LFN) in Schottky junction trigate silicon nanowire (SiNW) field-effect transistors (FETs) (SJGFETs) fabricated on bonded silicon on insulator (SOI) substrate is systematically analyzed. The LFN exhibited a typical 1/ ${f}$ spectrum and can be well described by the carrier number fluctuation (CNF) with correlated mobility fluctuation (CMF) model. It was found that CNF is the dominant component of the LFN, while CMF associated with the Coulomb scattering near the buried oxide (BOX)/SiNW channel interface plays an insignificant role. Applying a substrate bias can further modulate the LFN of the SJGFETs, and the effect is ascribed to the nonuniform energy distribution of the BOX/SiNW channel interface traps. Confining current path in the channel bulk away from the interface brought limited gain in terms of LFN performance. Finally, our experimental results suggested a possible transition of CMF mechanism from Coulomb scattering to surface roughness scattering when the current path is pushed away from the BOX/SiNW channel interface to the channel bulk. [ABSTRACT FROM AUTHOR]

In this article, we have evaluated the merits of monolithically cointegrated alternate channel complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile strained germanium ($\boldsymbol {\varepsilon }$ -Ge) for the p-channel FinFET and variable indium (In) compositional InxGa1-xAs ($0.10\le {x} \le0.53$) for the n- channel FinFET. The device simulation models were calibrated using the experimental results of Ge and InGaAs FinFETs and subsequently transferred to the cointegrated Ge and InxGa1-x As structure while keeping the device simulation parameters fixed. The device parameters, such as ${V}_{\text {T}}$ , ${I}_{\text {on}}$ , ${I}_{\text {off}}$ , and subthreshold-swing (SS), were determined for identical fin dimensions for n- and p-channel FinFETs as a function of In composition that alters the tensile strain in Ge. These parameters are controllable during the heteroepitaxial growth by varying In composition in InxGa1-xAs. $\boldsymbol {\varepsilon }$ -Ge p-FinFET is shown to be superior in terms of SS and ${I}_{\text {on}}/{I}_{\text {off}}$ ratio compared with other competing architectures. The cointegrated architecture of CMOS inverter exhibited an optimum performance over a range of In compositions from 20% to 40% while driving fan-out fan-out 1 (FO-1) and FO-4 load configurations. In addition, the CMOS inverter with symmetric rise and fall times as well as noise-immune functionality demonstrated 150 GHz of operating frequency with 30-nW total power dissipation at 20% In composition, and hence a superior power-delay-product comparable with International Technology Roadmap for Semiconductors (ITRS) standards. Moreover, the three-stage CMOS ring oscillator performance was evaluated with various In compositions to be stable and power efficient. Thus, the cointegrated approach has a potential to: 1) simplify large-scale CMOS integration and 2) be compatible with optoelectronic materials. [ABSTRACT FROM AUTHOR]

A tunable and reconfigurable logic gates based on an electrolyte-gated transistor (EGT) array are co-integrated with neuromorphic synapses. The tunable and reconfigurable operations of the various logic gates are controlled by analog conductance modulation with nonvolatility of the fabricated EGT. The EGT array was uniformly fabricated on an entire 4-in wafer with the aid of CMOS compatible processes. Initiated-chemical vapor deposition (i-CVD) method was adopted for the deposition of the ultrathin polyethylene glycol dimethacrylate (pEGDMA) electrolyte layer. Therefore, the logic gates could be co-integrated with synaptic devices on the same in-plane substrate for integrability. Basic inverter operation with switching threshold tunability ranging from −1 to +1 V was demonstrated with good operational stability. In addition, NAND and NOR gate operations were realized by modulating the conductance level of a specified cell in the array configuration. [ABSTRACT FROM AUTHOR]

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

The purpose of this article is to provide insight into ambipolar transport properties of the CMOS-like pseudo-inverter ($\Psi $ -inverter) in silicon-on-insulator (SOI) substrate. The $\Psi $ -inverter demonstrated in this work simply uses three probes instead of metal contact. The channel is controlled by the bottom gate and shows ambipolar conduction. The ambipolar voltage transfer characteristics (VTC) from the Si thin-film layer of the SOI device is extracted. The $\Psi $ -inverter operates both in the first and third quadrants, achieving remarkable gains as high as 25.8 and 936.1 at drain voltages ${V}_{{\mathrm {DD}}}$ = 3 and 7 V, respectively. Moreover, TCAD simulated results are approximated to the experimental data considering top Si interface traps to reveal the electrostatic potential and carrier concentration profiles. Exceptionally sensitive surface properties and high gain of the $\Psi $ -inverter demonstrated in our work enable it a promising candidate for sensor applications. [ABSTRACT FROM AUTHOR]

Junctionless transistors (JLTs) have promising strengths such as extremely simple structures without p-n junctions, better reliability, and low flicker noise, for overcoming scaling challenges for advanced sub-5-nm nodes. In this article, channel-width-dependent operation in the partially depleted regime of tri-gate JLTs was investigated in comparison to conduction in conventional inversion-mode (IM) transistors. A large difference in transconductance (${g} _{m}$) against gate-to-channel capacitance (${C} _{gc}$) and the reduced amplitude of the first peak on $dg_{m}$ / $dV_{g}$ were identified under the partially depleted regime in JLTs, due to a severe transverse ${E}$ -field near-threshold voltage (${V} _{th}$). However, the impact of ${E}$ -field was weakened as decreasing channel width of JLTs. These works provide key information for a better understanding of the channel-width-dependent performance of JLTs and for implementing practical applications with them. [ABSTRACT FROM AUTHOR]

The theoretical temporal resolution limit of silicon (Si) image sensors is 11.1 ps. The super temporal resolution (STR) is defined as a frame interval less than this limit. The temporal resolution of burst image sensors is significantly affected by “mixing” of signal electrons traveling from different starting positions. For example, the penetration depths of photons incident to a surface of a photodiode (PD) disperse exponentially, resulting in mixing of the photoelectrons from different depths at the other end, which causes a distribution of the arrival times. The temporal resolution is proportional to the standard deviation of the arrival time. Toward STR imaging, this article proposes measures to suppress various mixing phenomena during the travel of the signal electrons: 1) a germanium (Ge) PD for visible light to practically eliminate the effect of vertical mixing caused by the distribution of the penetration depth; 2) an inverted pyramid PD to efficiently suppress the horizontal mixing, keeping a 100% fill factor; 3) a standard column PD with negative potential on the vertical walls to squeeze the trajectory bundle of electrons falling on the guide gate on the front side; and 4) a resistive guide gate to linearize the potential profile to maximize the horizontal drift velocity to minimize the mixing together with the squeezed electron bundle. [ABSTRACT FROM AUTHOR]

The development of high-performance multispectral photodetector with narrowband and tunable spectral sensitivity is of importance but remains highly challenging to date. Here, we have reported on the fabrication of a Si Au/n-type Si/Au photodetector with tunable narrowband sensitivity not only in ultraviolet but also in near-infrared region, which is related to the controlled charge collection narrowing (CCN) mechanism. What is more, the negative response peak of the device can be readily tuned from 365 to 605 nm, and the positive response peak can be modulated from 938 to 970 nm when the bias varies from 0.1 to −0.1 V. In particular, the full-width at half-maximum is as small as 92 and 117 nm when the negative and positive response peaks approach the ultraviolet short wavelength end and near-infrared long wavelength end, respectively. The opposite polarity of the device responses in ultraviolet-visible and near-infrared regions renders the present Si photodetector potentially important in future multiple band optoelectronic systems. [ABSTRACT FROM AUTHOR]

Top-gated (TG) molybdenum disulfide (MoS2) field-effect transistors (FETs) suffer from surface damage, unintentional doping, and other defects introduced to the MoS2 channel during the direct deposition of the gate dielectric. In addition, the delicate MoS2 cannot withstand high-temperature processing or annealing. To overcome these obstacles, a novel path to prepare TG MoS2 negative-capacitance (NC) FETs is proposed in this study. A ferroelectric HfZrO2 (HZO) is first deposited on the mica flake by pulsed laser deposition (PLD) and then annealed by rapid thermal processing. Subsequently, the HZO/mica stack is integrally transferred onto the MoS2 surface, without needing to expose the MoS2 flake to harsh temperatures or PLD environments. TG multilayered MoS2 NCFETs with the HZO/mica stack are fabricated and demonstrate stable NC effects and superior performance with a subthreshold swing (SS) of 49 mV/dec, ON/OFF current ratio above 107, and anticlockwise hysteresis voltages of 64 mV, which are attributed to vital contributions from the damage-free mica/MoS2 van der Waals heterojunction interface and reasonable capacitance matching between the mica dielectric and the ferroelectric HZO film. Moreover, the experimental results of the dual-gate MoS2 transistor modulated by the bottom gate show that a positive bottom-gate bias can increase drain current and decrease hysteresis voltage, and a negative bottom-gate bias can reduce SS. Therefore, the proposed approach changes the current situation that the PLD method is hardly used to fabricate TG MoS2 transistors and opens a new window for nanoelectronics. [ABSTRACT FROM AUTHOR]

Serious agglomeration of ultrathin TiSix employed in source–drain (S–D) ohmic contacts after high-temperature annealing was manifested in previous work. This severely restricts its application in state-of-the-art DRAM peripheral 3-D FinFET transistors. In this work, the effects of hafnium (Hf) interlayer on the thermal stability of ultrathin TiSix in TiSix/n+-Si ohmic contacts were systematically studied. As-prepared ultrathin TiSix and TiSix/n+-Si ohmic contacts with 0-, 1-, 2-, and 3-nm Hf interlayers were characterized by means of specific contact resistivity ($\rho _{\text {c}}$), transmission electron microscopy (TEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). It is found that compared to the counterparts with 0-, 2-, and 3-nm Hf, the presence of 1-nm Hf interlayer is proven to be effective in enhancing the thermal stability of ultrathin TiSix significantly. With 1-nm Hf, amorphous HfO2, and Hf silicate are readily formed, which hinders the interdiffusion between Ti and Si atoms and resultant agglomeration of ultrathin TiSix films. This is thought to be responsible for such a remarkably enhanced thermal stability of ultrathin TiSix in TiSix/n+-Si ohmic contacts. [ABSTRACT FROM AUTHOR]

Conventional bulk silicon is approaching its physical limit in the continued scaling of field-effect transistors (FETs). To extend the scaling limit of silicon-FETs, 2-D silicon semiconductors are highly desired because of the atomic thickness and mature CMOS-compatibility. By employing the hybrid honeycomb-kagome (hhk)-silicene monolayer as transport channel, we study the performance of sub-5-nm p- and n-type FETs based on ab initio quantum transport simulations. The hhk-silicene pFET (nFET) can be scaled down to 2-nm (3 nm) gate length (${L}_{g}$) with performances fulfilling the high-performance requirements of International Technology Roadmap for Semiconductors (ITRS) for 2028 horizon. Besides, with ${L}_{g}$ scales down to 3 nm, the subthreshold swing (SS) of the hhk-silicene FETs still can break the thermal limit of 60 mV/dec. The subthermal switches of hhk-silicene FETs benefit from the relatively isolated bands near the Fermi level. This work reveals the great potentials of hhk-silicene for ultrascaled and steep-slope FETs in future. [ABSTRACT FROM AUTHOR]

We studied nitrogen (N) incorporation effects on the electrical characteristics of SiO2 fabricated by plasma-enhanced atomic layer deposition (PEALD). To determine whether N could be incorporated into the SiO2, nitrous oxide (N2O) plasma with different plasma powers (100, 150, and 200 W) was used during the SiO2 deposition, and the film properties were compared with SiO2 fabricated using a conventional oxygen (O2) plasma reactant. Compared to the O2 plasma reactant, the hard breakdown is improved by 27.5% as N2O plasma power increases up to 150 W, whereas it is degraded at a N2O plasma power of 200 W. These results are found to describe the relationship between the N content and film properties. The N content in the SiO2 films fabricated using increasing N2O plasma power of 100, 150, and 200 W gradually increased by 0.2%, 0.4%, and 0.5%, respectively. However, the N2O plasma power of 200 W results in increased O deficient Si bonding. To investigate the effects of continuous plasma exposure at the bottom layer during the SiO2 deposition, we fabricated indium–zinc oxide (IZO) top-gate bottom-contact (TG-BC) thin-film transistors (TFTs) using the SiO2 as a gate insulator (G.I). Compared to the O2 plasma, the IZO TFTs using N2O plasma reactant during the G.I deposition show stable transfer characteristics. The IZO TFT using N2O plasma with 150-W power during the G.I deposition shows the optimal positive/negative bias temperature stress (P/NBTS) results, with the threshold voltage ($V_{\mathbf {TH}}$) variations of 0.0 and −0.3 V, respectively. [ABSTRACT FROM AUTHOR]

The thermal stability of molybdenum oxide (${\text{MoO}}_{x)}$ -based carrier selective contact silicon solar cells (Ag/ITO/MoOx/n-Si/LiFx/Al) is investigated under ambient annealing conditions for different time durations. The devices remain stable up to 150 °C for 15 and 30 min of annealing. However, at 200 °C, the cells degrade with a decrease in the fill factor and open-circuit voltage ($V_{{\text {oc}}}$); the degradation rate is significant at 30 min. The illumination-dependent $V_{{\text {oc}}}$ study has indicated the charge transport barrier at the MoOx/c-Si interface in a degraded cell. The dark current density-voltage analysis of the degraded cells has also shown charge carrier recombination and series resistance at low- and high-forward bias conditions, respectively. To identify the device degradation with the temperature, ITO/MoOx and MoOx/c-Si interfaces are analyzed in terms of contact resistivity ($\rho _{c}$) using extended transfer length method (ETLM). After annealing at 200 °C, a significant increase in $\rho _{c}$ of the MoOx/c-Si interface (from ~17 to $\sim 385~\text{m}\Omega $ -cm2) is observed in comparison to the ITO/MoOx interface (from ~16.5 to $\sim 39~\text{m}\Omega $ -cm2), reflecting the crucial role of MoOx/c-Si junction in cell degradation. The thermal degradation of the MoOx/c-Si interface is due to a decrease in the MoOx film’s work function (WF) upon annealing, which creates a transport barrier for charge carriers. The reduction in the MoOx WF results in misalignment of c-Si’s valence band and MoOx’s conduction band, leading to inefficient carrier transport through band-to-band tunneling, which is also confirmed from the numerical simulations. [ABSTRACT FROM AUTHOR]

The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ of more than 106 and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method. [ABSTRACT FROM AUTHOR]

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents a PSOI technology platform with the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET),this technology achieves an ON-state resistance of 1435 $\text{m}\Omega $ mm2, an over 50% improvement compared with the state-of-the-art SOI technologies while maintaining competitive reliability. [ABSTRACT FROM AUTHOR]

Here, we demonstrate holey silicon-based thermoelectric cooling devices using simple fabrication processes and evaluate their cooling performance using infrared thermography. While lateral thermoelectric coolers require a suspended structure and thermal isolation for optimal performance, our design simply combines a silicon device layer with an insulating Pyrex substrate and enables demonstration of thermoelectric cooling by holey silicon even on a bulk heating stage instead of a local hot spot. Our work shows that holey silicon with $1.9~\mu \text{m}$ wide necks and 21 $\mu \text{m}$ deep trenches provides a temperature reduction of 1.2 °C over a 300 $\mu \text{m}\,\,\times $ 300 $\mu \text{m}$ area when the underlying heating stage is set to keep the background at $100~^{\circ }\text{C}$. Our model attributes the cooling performance to the unique thermal anisotropy of holey silicon and predicts greater performance with deeper holey silicon trenches, smaller holey silicon necks, and higher background temperatures or stronger heating. These findings indicate holey silicon-based thermoelectric cooling can be very useful for thermal management of various electronic devices and handling on- chip hot spots. [ABSTRACT FROM AUTHOR]

Direct bidirectional current discharge paths between input/output (I/O) and ground (GND) are imperative to achieve robust charged device model (CDM) protection for very stringent design window in advanced low-voltage (LV) processes. In this brief, a compact and fast response dual-directional silicon-controlled rectifier (CFR-DDSCR) has been proposed. Using P-electrostatic discharge (ESD) implantation layer to implement each diode-triggered silicon-controlled rectifier (SCR) within only one n-well, the inherent defect of the prior art (i.e., the cumbersome p-well/n-well triggering diode) is eliminated, ensuring the low resistance of auxiliary triggering path and the compactness of silicon footprint. Moreover, by shielding all internal shallow trench isolation (STIs) with floating high- ${k}$ metal gates (HKMGs), an all-gate-bounded SCR structure is realized, and all triggering diodes evolve into gated diodes with compact current paths, thus improving the CDM protection capability greatly. Experimental results indicate that the CFR-DDSCR, with a design window suitable for 1.2 V-CMOS technologies, acquires a higher effective CDM robustness (73% improved), a faster turn-on speed (64% improved), and a more compact layout (31% shrunk) compared with its conventional counterpart, which is promising for the advanced LV CDM protection. [ABSTRACT FROM AUTHOR]

This work reports gadolinium-doped cerium oxide (CeO2) as gate dielectric, and appropriate doping of Gd can effectively prevent oxygen vacancy-related defects in CeO2 thin films. Atomic layer deposition (ALD)-derived 3 nm Al2O3 passivation layer on CeGdOx has the advantage of further reducing the leakage current of CeGdOx MOS capacitors due to the wide bandgap and compactness of Al2O3. Then, Al2O3/CeGdOx bilayer dielectric-based In2O3 thin-film transistors (TFTs) are constructed; electrical performances are systematically explored under the effect of Gd doping compared with pristine Al2O3/CeO2-gated TFT. Al2O3/CeGdOx (30 at% Gd) TFT demonstrates high performances with ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio of 1.45 $\times 10^{{7}}$ , saturation mobility of 27.28 cm2/V $\cdot $ s, subthreshold swing (SS) of 0.091 V/decade, interfacial trap states of $1.64\times 10^{{11}}$ cm−2, as well as remarkable positive bias stress (PBS) stability. Low-frequency noise (LFN) together with X-ray photoelectron spectroscopy (XPS) illustrates that Gd doping in CeO2 contributes to the reduction of interface trap density, improving electrical performance. Moreover, a resistor-loading inverter based on Al2O3/CeGdOx-gated TFT exhibits superior voltage transfer characteristics (VTC) with a voltage gain of 16 at 5 V, demonstrating the potential application of Al2O3/CeGdOx-based TFTs for future digital circuits. [ABSTRACT FROM AUTHOR]

Insufficient signal-to-noise ratio (SNR) limits the quality of cardiac pulses measured by multitap CMOS image sensors (CISs). We present an in-pixel temporal redundant samplings (TRS) method for enhancing the SNR through sampling the charges originated by one individual optical scene into the multiple storage taps in turn with the identical time window, enabling magnification of the image signal in shot noise domain. Modeling indicates that the linear SNR increases with a factor square root of TRS sampling number, which is also verified by characterization results utilizing a four-tap CIS. Application results show that the high-frequency (HF) noise components observed in the measured cardiac pulses can be attenuated by 67.9%, 48%, and 53.6% with heart rate detection accuracies up to 99.7%, 99.3%, and 98.7% by applying TRS modes under given conditions of stable ambient, background light (BGL) variation, and motion disturbance, respectively. Moreover, the proposed method is as well foreseeable to be extended to other multitap-involved imaging applications. [ABSTRACT FROM AUTHOR]

In this work, the localized backside etching (LBE) structure is introduced as a strategy for total ionizing dose (TID) irradiation hardening. Immunity to TID-irradiation-induced radio frequency (RF) property degradation is observed for the first time in SOI substrates with the LBE structure. Identical co-planar waveguide transmission lines (CPW TLines), crosstalk characterization structures, and planar spiral inductors are designed and fabricated on different 8-in SOI wafers to characterize the RF properties of substrates. Electrical characterization in the frequency ranges from 100 MHz to 40 GHz reveals that the LBE structure is beneficial to suppressing the parasitic surface conduction (PSC) effect, which will lead to better RF properties of SOI substrate. It is shown that under 60Co $\gamma $ -ray irradiation, RF losses are significantly increased in the case of conventional substrates. In contrast, LBE substrates are almost insensitive to TID irradiation due to suppression of PSC. A developed physical model is proposed to characterize the behavior of inductors under PSC and TID effects, and the improvement by LBE structure on RF TID tolerance is separated through model parameter extraction. [ABSTRACT FROM AUTHOR]

High-efficiency, high-speed phototransistors applicable in visible wavelength and the near-infrared regime are highly desirable for optical communication links utilized for data centers, high-performance computing, and laser radar application. To overcome the intrinsic weak absorption of silicon material and alleviate the compromise between efficiency and speed of the device, a SiGe/Si heterojunction phototransistor (HPT) with photon-trapping nanoholes is demonstrated in this article. With photon-trapping nanohole structures, the absorption efficiency of the HPT is greatly improved near the whole band ranging from 600- to 1000-nm wavelength compared to one without nanoholes. The responsivity of nanohole-assisted HPT is 25.69, 27.02, and 15.65 A/W at 650-, 850-, and 940-nm wavelength, exhibiting 85.22%, 192.42%, and 848.48% improvement compared with its counterpart without nanoholes. The thin base region also allows a high speed of the HPT with a transient response of 0.45 ns at 850-nm wavelength. [ABSTRACT FROM AUTHOR]

The existing Bessel beam generators generally require bulk optics counterparts and additional spatial laser sources, which adds complexity and bulkiness to the system. In this work, we propose Bessel beam devices with high compactness based on vertical-cavity surface-emitting lasers (VCSELs) and microdielectric axicons made by Si3N4. The transparent microaxicons are fabricated by one-step direct writing of focused ion beam (FIB) on the surface of meticulously designed top-emitting VCSELs. Zero- and first-order Bessel beams are obtained by engineering the lasing modes of the VCSELs through simply adjusting the oxide aperture diameter. Even if the VCSEL device works at multimode, Bessel beams can still be realized. This method provides great compatibility with different VCSEL configurations and emitting wavelengths. Such high-compactness devices may enable advanced research and applications relevant to Bessel beams. [ABSTRACT FROM AUTHOR]