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Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, an static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows $1.14\times /1.17\times $ shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay.

A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (

An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.

A bipolar-mode multibit soft-error mechanism in static random-access memory (SRAM) devices has been explored by utilizing a 3D device simulation of an inverter constructed with a driver n-MOSFET, a load resistor, and capacitors. Generally, a well tap was not set at every SRAM unit cell so as to increase the packing density. We have introduced a model structure where a p-well for arranging the driver n-MOSFET in a CMOS inverter does not have the well tap in the analyzed cell, and we have studied the inverter action when a drain junction of the n-MOSFET in an OFF-state is hit by an alpha -particle. We found that the p-well is forwardly biased by generated excess carriers. The forward bias at the p-well switches the n-MOSFET from the OFF-to the ON-state, like an on action of an n-p-n transistor, and the output potential of the inverter changes from high to low. This bias change results in a flip on the state of the SRAM unit cell. When a series of n-MOSFETs (or p-MOSFETs) is arranged in the same well and the well tap is not arranged in every unit cell, the switch-on action of the MOSFET is sequentially induced, like a chain reaction. We have developed a multidrain model by adding a p-n junction around the n-MOSFET in the p-well and have successfully demonstrated the chain reaction. In addition, we have demonstrated the soft-error occurrence in an unit cell with the help of circuit simulation. This is the mechanism of multiple soft errors by the bipolar-mode operation. A key factor for evaluating the tolerance of the bipolar-mode soft error is a forwardly biased time at the well (i.e., a well-floating time). The well-floating time (tfloat) is dependent on an initial charge (Qi) in the depletion layer and a resistance (-Rwell) between the well and the tap. The tfloat has been precisely analyzed as functions of Qi and -Rwell, and a critical charge, defined by Qi over which the memory state is flipped, has been clarified for single-and two-bit errors.

This paper describes the device design guidelines for floating channel type surrounding gate transistor (FC-SGT) DRAM cells with high soft-error immunity. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional storage capacitor. The cell itself arranges the bit line (BL), storage node, and body region in a silicon pillar vertically and hence, achieves a cell area of 4F/sup 2/ (F: feature size) per bit. A thin-pillar FC-SGT with a metal gate can maintain a low leakage current without using a heavy doping concentration in the body region. Furthermore, as the silicon pillar thickness is reduced, the device enters into the fully depleted operation and as a result can realize excellent switching characteristics. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor that causes soft errors to occur. However, the parasitic bipolar current can be suppressed and its duration can be shortened as the silicon pillar thickness is reduced. As a result, the amount of stored charge lost in the storage capacitor can be effectively decreased by using a thin-pillar FC-SGT. In the case of a 10-nm-thick FC-SGT, the amount lost due to the parasitic bipolar current is decreased to about 28% of that due to the leakage current. Therefore, FC-SGT DRAM is a promising candidate for future nanometer high-density DRAMs having high soft-error immunity.

We present here an extensive static random access memory (SRAM) bitcell development methodology that has led to the qualification and production of the smallest 6-T SRAM bitcell reported in 0.13-/spl mu/m CMOS technology. No additional processing steps were employed in accomplishing this result. Such a methodology is being extended also to subsequent technology generations. The development efforts included the electrical evaluation of several candidate 6-T SRAM bitcell architectures for both high-density and high-speed applications. Based on the electrical evaluations, the chosen cell architectures were incorporated in silicon and verified for their robustness with respect to critical design rules, yields and reliability. The methodology for optical proximity correction for bitcell development has been described here. Minor process enhancements to ensure compatibility of the overall process flow with the SRAM bitcells are described. The use of SRAM-specific electrical test structures serves an important role in validating the electrical performance and confirming the robustness of the bitcells in a manufacturing environment. The monitoring of V/sub ddmin/, the minimum voltage at which the memory is functional was used to drive overall process improvements and reliability. Lastly, measurements of soft error rates demonstrated excellent immunity of the bitcells to single event upsets.

Soft-error tolerance of static random-access memory (SRAM) devices has been predicted by using three-dimensional (3-D) and time-dependent device simulation in conjunction with circuit simulation. An inverter model developed for 3-D device simulation is described, along with the analysis of the inverters device response as a function of time. The output thus obtained was applied as an input voltage source in circuit simulation of unit SRAM cell and the stability of this bistable circuit is studied on that basis. The effects on soft-error immunity of changes in alpha-particle injection conditions and in load resistance and capacitance are described. The validity of the presented model is examined through comparison of the bit-error-rate dependence on incident angle of alpha particles to that of measured rates. To simulate the angular dependence, we introduce statistical distribution models for alpha-particle energy, position of incidence on the device surface, and angle of incident. Results of device/circuit simulation carried out with many sets of energy, position, and angle are presented. Reasonable agreement between results of simulation and experimental data without the use of adjustment parameters is demonstrated. A map of soft-error tolerance on the CR plane with critical charge Q/sub c/ as a parameter is presented and its derivation explained. An analytic expression for the tolerance is clarified by proposing an equivalent circuit model for the simulation of alpha-particle injection at the output node in an inverter circuit. Inverter modeling is shown to be essential to obtaining SRAM soft-error tolerance to high degrees of accuracy.

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 10/sup 11/ cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.

This paper clarifies alpha-particle-induced soft error mechanisms in floating channel type surrounding gate transistor (FC-SGT) DRAM cells. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional (3-D) storage capacitor. The cell itself arranges bit line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F/sup 2/ (F: feature size) per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor to cause soft errors. When an alpha particle penetrates the silicon pillar, generated electrons are collected to the storage node or BL due to the tunneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Consequently, the current flows not only in the surface but also in the entire body region due to the floating body effect. This parasitic bipolar current becomes the largest when an alpha particle penetrates the silicon pillar along the vertical axis. However, in case of FC-SGT DRAM cells, the surrounding gate structure can suppress the floating body effect compared with floating channel type SOI DRAM cells. As a result, the loss of the stored charge in the storage capacitor can be drastically decreased by using FC-SGT DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high-density DRAMs having high soft-error immunity.

This paper presents an analytic integral model for the accelerated soft error rate (ASER). The model took into account the physical and structural parameters as four alpha incident angles and an angular function. Two angles were related to charge collection and another two angles and an angular function were related to measurement configuration and how much alpha flux arrived. The model was verified by measuring ASER in 8 M static RAM. The model could explain ASER characteristics of saturation, exponential dependence, and vanishing with the power supply voltage. The model also reproduced an extraordinary phenomenon that there is a maximum in ASER with respect to the thickness of the capping layer on the static RAM.

This is the first report of abnormal behavior in the soft error rate (SER) dependence on supply voltage (Vcc) for a bottom-gated polysilicon PMOS thin-film transistor (TFT) static random access memory (SRAM). We found that the TFT SER does not continuously improve (as is expected and desirable) with increasing Vcc when Vcc exceeds -Vth (threshold voltage) of the TFT within a range of about 0-2 V. This was confirmed with samples of TFT with Vth intentionally varied from 0 to -5 V (by adjusting channel doping). A possible explanation of this Vcc independence is proposed in the form of a SPICE simulation with as little as a 0.1-V TFT transient Vth shift due to the TFT's floating body. The accelerated SER was measured by using an Americium alpha particle source.

Alpha-particle-induced soft error in 256 M DRAM was numerically investigated. A unified model for alpha-particle-induced charge collection and a soft-error-rate simulator (SERS) was developed. We investigated the soft error rate of 256 M DRAM and identified the bit-bar mode as one of dominant modes for soft error. In addition, for the first time, it was found that trench-oxide depth has a significant influence on soft error rate, and it should be determined by the tradeoff between soft error rate and cell-to-cell isolation characteristics.

Neutron-induced soft error rates (SERs) of subhalf-micron CMOS SRAM and Latch circuits were studied both experimentally and analytically to investigate cosmic ray neutron-induced soft errors (SEs). Because the neutron beam used in the measurement has an energy spectrum similar to that of sea-level atmospheric neutrons, our SER data corresponds to those induced by cosmic ray neutrons. The /spl alpha/-particle induced SERs were also measured for comparison with the neutron-induced SER's. Neutron-induced SEs occurred in both circuits. On the other hand, /spl alpha/-induced SEs occurred in SRAM, but not in the Latch circuits. The measured SERs agreed with simulated results. We discussed the significance of how cosmic ray neutrons affects CMOS circuits at ground level.

This paper provides conclusive evidence that cosmic rays cause soft errors in commercial dynamic RAM (DRAM) chips at ground level. Cosmic-ray-induced soft errors in electronic components have long been a problem for the designers of satellites and spacecraft, but they have not generally been considered to be an important influence on memory chip soft error rate (SER) in terrestrial environments. In an experiment designed to determine the effect of cosmic radiation on the SER of a sample of DRAM chips at ground level, the SER of a large number of chips was measured at various locations and altitudes around the US: near sea level in Essex Junction, VT; 200 m underground in a Kansas salt mine; at an altitude of 1.6 km in Boulder, CO; and at 3.1 km in Leadville, CO. The results reported here show that even at sea level there is a significant component of the SER that can be attributed to the effects of cosmic rays, and that the magnitude of the effects increases dramatically at higher altitudes. >

A new isolation structure for soft-error immunity has been developed. This structure, SEPIA (soft-error-preventing isolation by charge absorption), is suitable for advanced ULSIs such as 256-kb bipolar SRAMs. The SEPIA structure combines charge absorption and trench isolation. Experiments and simulations show that SEPIA reduces the amount of alpha-particle-induced charge collected in transistors. Electrons which diffuse in the substrate are absorbed by SEPIA. The collected charge is reduced to 20-30 fC, which is about 1/5 of the charge collected with the conventional structure. With SEPIA the amount of charge collected decreases as the transistor size is scaled down. SEPIA is thus more effective in the small transistors that will be used in advanced ULSIs. >

The alpha-particle-induced soft-error mechanism in a high-speed bipolar static RAM (SRAM) which is used for mainframe computers is investigated using a three-dimensional (3-D) device and a circuit simulator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cell's soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an effective-charge model is proposed. This model incorporates weight coefficients that express the memory cell's soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAMs are simulated using the effective-charge model. >

A static latch design is analyzed whose single event upset (SEU) sensitivity is extremely dependent on its logic state. The authors employ a modification of a hardened static memory cell to construct an asymmetrical latch. Both the original and asymmetric latches are illustrated. The original idea was that resistors in the drain lines provide voltage division at the feedback point for p-drain strikes (or voltage transients). Proper choice of the resistor value relative to the on resistance of the n-channel transistor will insure that the feedback voltage can never reach the switch point of the opposite inverter, preventing cell upset for any p-drain transient. Such latches respond symmetrically with respect to logic state, displaying essential immunity to one SEU mechanism. A simple AND gate for two of these asymmetric response latches provides high-speed error correction for a single bit, and the combination represents a hardened logic element. >

A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p/sup -/-substrate are completely shielded by n/sup +/-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10/sup 5/ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell. >

We study soft error rates (SER) in VLSI circuits, where the charge capable of causing a soft error becomes only a few percent of that created by a typical alpha-particle impacting on the circuits. Theoretical investigations are done considering a DRAM test vehicle, with the assumption that it is exposed to alpha-particles emanating from materials on the chip. We examine the effects of scaling on the SER and investigate the performance of several device structural modifications that can be introduced to decrease SER. We present experimental results on the achieved reduction in the charge that surface nodes collect when structural modifications are introduced. We find, both experimentally and theoretically, that the most promising modification is the incorporation of a buried grid of opposite conductivity type from the substrate. In general, however, as stored change shrinks, multiple errors become prevalent, and SER reduction due to fabrication changes becomes less effective.

A new VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFET's and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both storage capacitor nodes are kept electrically floating in retention periods and one storage capacitor node is formed in a thin SOI film, an alpha-particle hit does not destroy the stored charge of this memory cell. It is sufficient for an SOI-PMOSFET to provide only three orders of magnitude ON/OFF current ratio. Experimental memory cells were fabricated using polysilicon film as an SOI film. Measuring them confirmed the main effectiveness of this memory cell.

A new physical soft error mechanism in dynamic RAM's and CCD's is the upset of stored data by the passage of alpha particles through the memory array area. The alpha particles are emitted by the radioactive decay of uranium and thorium which are present in parts-per-million levels in packaging materials. When an alpha particle penetrates the die surface, it can create enough electron-hole pairs near a storage node to cause a random, single-bit error. Results of experiments and measurements of alpha activity of materials are reported and a physical model for the soft error is developed. Implications for the future of dynamic memories are also discussed.

Alpha-particle-induced soft-error immunity in a 1-kB GaAs SRAM was improved by a buried p-layer, which was formed in isolation regions as well as in FET regions and was designed to be completely depleted. The mean time between failures exceeded 10/sup 4/ at an alpha-particle fluence of about 2.0*10/sup 4/ cm/sup -2/-s/sup -1/ with a 1.0- mu Ci/sup 241/Am source. The alpha-particle energy had a peak at 4.0 MeV and was distributed from nearly 0 to 4.6 MeV. This value is five orders of magnitude better than that for a conventional SRAM without a buried p-layer. This improvement in the soft-error immunity can be achieved without increasing the access time or the power consumption by depleting the p-layer completely. Also discussed is the possibility of using a conductive p-layer scheme for higher integration of GaAs SRAMs. >

Recent investigations [1] have found low levels of alpha particles (< 0.1 counts/cm2. h) emitted from the immediate chip environment to be responsible for soft errors in 16K MOS dynamic RAM's. We have investigated this problem in two related studies. First, we review the interaction of alpha particles with the Si lattice and present range-energy and specific ionization data. Experimental values of the actual charge collected at shallow junctions for 4.9-MeV alpha events are presented. The dynamics of the collection process and the influence of the interface electric field in p-p+epitaxial material are identified. We further show the dependence of the collected charge on the incident particle energy and angle. Second we review the operation of current memory devices and indicate how soft failures due to alpha particles can be identified. We present soft error rate versus duty cycle data for a number of devices displaying different failure modes. The dependence of the soft error rate on incident particle energy and angle is also shown. Finally, we propose a simple accelerated test to evaluate device susceptibility to this failure mode.

A 12-ns access-time 0.5-Mb CMOS DRAM (dynamic random-access memory) operated at liquid-nitrogen temperatures is discussed. Comprehensive measurements, featuring a low-temperature e-beam tester, focused on circuit concerns particularly relevant to high speed. The results, including the first reported measurements of soft error rate (SER) at low temperatures, show that noise, power, and SER do not preclude very high-speed liquid-nitrogen DRAM operation. >

The alpha -particle-induced soft-error phenomena for VLSIs are investigated using a three-dimensional device simulator and a new experimental method. The scope of the present work includes a description of: the scalability of the funneling length (size effects and proximity effects), the effects of reduced supply voltages, the potential barrier effect of an n/sup +/-p/sup +/-p (substrate) structure, compulsory exposure experiments, and a new effect that causes the soft error ( alpha -particle source-drain penetration effect, or ALPEN). A new funneling length behavior that cannot be explained by Hu's model (1982) is discussed. According to this behavior, it was found that a critical charge for a given soft-error rate, which determines the limitation of planar and trench memory cells, can be scaled down. Furthermore, it is shown that the ALPEN effect, which occurs when an effective channel length of a MOSFET is comparable to the effective funneling length, puts a new constraint on deep submicrometer VLSI design. >

A small-area static memory cell with high soft-error immunity is proposed. The driver MOSFET has a vertical structure. Its source region is buried in the substrate to which the ground potential is applied on order to shield the surface drain region from noise charges. The transfer MOSFET is a lateral type. These changes result in a reduction of the memory cell size and the gate area with the same effective gate width, since the channel is formed around the trench gate electrode. High soft error immunity is also expected because the drain region is shielded from noise charges induced by a-particles. A test circuit for a 1-bit memory cell was fabricated by using the 1.3 mu m process technology. The cell size was 0.75 times as large as the conventional memory cell size, and its soft error rate was only 0.04 times that of the conventional one. The results show that this memory cell is suitable for future multimegabit SRAMs. >

Intrinsic gettering (IG) and P/P+epitaxial wafers are compared in terms of soft error endurance and other characteristics of a 64k bit dynamic RAM. It was confirmed that soft error rate is improved in IG wafers, while it is deteriorated in P/P+epitaxial wafers. However, when epitaxial layer thickness is reduced to a certain value, the soft error rate tends to be improved. Several other characteristics of 64k bit DRAM's were also evaluated for devices made on IG and epitaxial wafers with various denuded zone (DZ) widths and epitaxial layer thicknesses, respectively.