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A p-channel metal–ferroelectric–insulator–silicon field-effect transistor (FET) with a 300-nm-thick \SrBi2\Ta2\O9 (SBT) ferroelectric film and a 10-nm-thick HfTaO layer on silicon substrate was fabricated and characterized. The device shows a nearly unchanged memory window of about 0.9 V after a \2 \times \10^11-cycles fatigue test, an on/off current ratio of more than \10^7, and a field-effect mobility of approximately 42 \cm^2/\V \cdot \s. Moreover, a drain-current on/off ratio as high as \10^5 was obtained with a fixed gate voltage of 2.5 V after over a \10^5-s elapsed time without any obvious degradation. These results may suggest that the Pt/SBT/HfTaO/Si FET is suitable for high-performance ferroelectric memory. [ABSTRACT FROM AUTHOR]

A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao–Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations (i.e., threshold voltage shifts) of the JLFET, which has been recently proposed as a promising candidate for the JFET. [ABSTRACT FROM AUTHOR]