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Your search keyword '"Thean, Aaron Voon-Yew"' showing total 21 results
Start Over Author "Thean, Aaron Voon-Yew" Journal ieee transactions on electron devices
21 results on '"Thean, Aaron Voon-Yew"'

2. Indium-Gallium-Zinc-Oxide (IGZO) Nanowire Transistors

Author

Han, Kaizhen, primary, Kong, Qiwen, additional, Kang, Yuye, additional, Sun, Chen, additional, Wang, Chengkuan, additional, Zhang, Jishen, additional, Xu, Haiwen, additional, Samanta, Subhranu, additional, Zhou, Jiuren, additional, Wang, Haibo, additional, Thean, Aaron Voon-Yew, additional, and Gong, Xiao, additional

Published
2021
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6. Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2

Author

Yu, Hao, primary, Schaekers, Marc, additional, Peter, Anthony, additional, Pourtois, Geoffrey, additional, Rosseel, Erik, additional, Lee, Joon-Gon, additional, Song, Woo-Bin, additional, Shin, Keo Myoung, additional, Everaert, Jean-Luc, additional, Chew, Soon Aik, additional, Demuynck, Steven, additional, Kim, Daeyong, additional, Barla, Kathy, additional, Mocuta, Anda, additional, Horiguchi, Naoto, additional, Thean, Aaron Voon-Yew, additional, Collaert, Nadine, additional, and De Meyer, Kristin, additional

Published
2016
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8. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes

Author

de Oliveira, Alberto V., primary, Simoen, Eddy, additional, Mitard, Jerome, additional, Agopian, Paula G. D., additional, Martino, Joao Antonio, additional, Langer, Robert, additional, Witters, Liesbeth, additional, Collaert, Nadine, additional, Thean, Aaron Voon-Yew, additional, and Claeys, Cor, additional

Published
2016
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12. Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

Author

Ritzenthaler, Romain, primary, Schram, Tom, additional, Spessot, Alessio, additional, Caillat, Christian, additional, Cho, Moonju, additional, Simoen, Eddy, additional, Aoulaiche, Marc, additional, Albert, Johan, additional, Chew, Soon-Aik, additional, Noh, Kyoung Bong, additional, Son, Yunik, additional, Mitard, Jerome, additional, Mocuta, Anda, additional, Horiguchi, Naoto, additional, Fazan, Pierre, additional, and Thean, Aaron Voon-Yew, additional

Published
2016
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14. Low-Frequency Noise Characterization of GeOx Passivated Germanium MOSFETs

Author

Fang, Wen, primary, Simoen, Eddy, additional, Arimura, Hiroaki, additional, Mitard, Jerome, additional, Sioncke, Sonja, additional, Mertens, Hans, additional, Mocuta, Anda, additional, Collaert, Nadine, additional, Luo, Jun, additional, Zhao, Chao, additional, Thean, Aaron Voon-Yew, additional, and Claeys, Cor, additional

Published
2015
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16. Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching 1 \times 10^-9 Ohm-cm2.

Author

Yu, Hao, De Meyer, Kristin, Schaekers, Marc, Peter, Anthony, Pourtois, Geoffrey, Rosseel, Erik, Everaert, Jean-Luc, Chew, Soon Aik, Demuynck, Steven, Barla, Kathy, Mocuta, Anda, Horiguchi, Naoto, Thean, Aaron Voon-Yew, Collaert, Nadine, Lee, Joon-Gon, Song, Woo-Bin, Shin, Keo Myoung, and Kim, Daeyong

Subjects
COMPLEMENTARY metal oxide semiconductors, TITANIUM silicides, AMORPHIZATION, SILICON analysis, ELECTRICAL resistivity, ELECTRIC resistance, NANOSTRUCTURES
Abstract

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity ( \rho c ) of (1.3 – 1.5) \times 10^-9 ~\Omega \cdot \text cm^2 on Si:P. This PCAI + TiSix technique utilizes light amorphization (low-energy implantation), thin Ti and TiSix film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSix-induced \rho c reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced \rho c variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low \rho c is strongly correlated with the formation of interfacial TiSix crystallites between amorphous TiSi alloy and Si. [ABSTRACT FROM PUBLISHER]

Published
2016
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17. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes.

Author

Claeys, Cor, de Oliveira, Alberto V., Agopian, Paula G. D., Martino, Joao Antonio, Simoen, Eddy, Mitard, Jerome, Langer, Robert, Witters, Liesbeth, Collaert, Nadine, and Thean, Aaron Voon-Yew

Subjects
FIELD-effect transistors, HOLE mobility, THRESHOLD voltage, RUTHERFORD scattering, HEAT
Abstract

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

Published
2016
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18. Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

Author

Walke, Amey M., primary, Vandooren, Anne, additional, Rooyackers, Rita, additional, Leonelli, Daniele, additional, Hikavyy, Andriy, additional, Loo, Roger, additional, Verhulst, Anne S., additional, Kao, Kuo-Hsing, additional, Huyghebaert, Cedric, additional, Groeseneken, Guido, additional, Rao, Valipe Ramgopal, additional, Bhuwalka, Krishna K., additional, Heyns, Marc M., additional, Collaert, Nadine, additional, and Thean, Aaron Voon-Yew, additional

Published
2014
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20. Vertical GAAFETs for the Ultimate CMOS Scaling.

Author

Yakimets, Dmitry, Eneman, Geert, Schuddinck, Pieter, Bao, Trong Huynh, Bardon, Marie Garcia, Raghavan, Praveen, Veloso, Anabela, Collaert, Nadine, Mercha, Abdelkarim, Verkest, Diederik, Thean, Aaron Voon-Yew, and De Meyer, Kristin

Subjects
FIELD-effect transistors, INTEGRATED circuit design, SWITCHING circuits -- Design & construction, ELECTRIC oscillators, ELECTRODES
Abstract

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

Published
2015
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21. Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET.

Author

Walke, Amey M., Vandooren, Anne, Rooyackers, Rita, Leonelli, Daniele, Hikavyy, Andriy, Loo, Roger, Verhulst, Anne S., Kao, Kuo-Hsing, Huyghebaert, Cedric, Groeseneken, Guido, Rao, Valipe Ramgopal, Bhuwalka, Krishna K., Heyns, Marc M., Collaert, Nadine, and Thean, Aaron Voon-Yew

Subjects
LOGIC circuits, HETEROJUNCTIONS, SEMICONDUCTOR junctions, FIELD-effect transistors, QUANTUM confinement effects
Abstract

This paper presents a new integration scheme to fabricate a Si/Si0.55~Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-\mum gate length device shows on current in excess of 20 \muA/\mum at VGS=VDS=1.2~\rm V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by \sim0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration. [ABSTRACT FROM AUTHOR]

Published
2014
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