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This paper utilizes electrical analyses and a study of physical mechanisms to investigate metal gate structure-dependent performance in amorphous InGaZnO (a-IGZO) thin-film transistors. The effects of different shielding areas between the IGZO layer and metal gate are investigated. In devices with shorter metal gate lengths, an abnormal rise in capacitance at the off-state in capacitance–voltage ( ${C}-{V}$ ) characteristic curves can be observed. This can be attributed to the stronger electric field induced by the edge of the metal gate under bias sweep when the metal gate length is shorter than the IGZO layer length. Light illumination measurements indicate a negative shift in threshold voltage and an increase in subthreshold-leakage current regardless of relative metal gate length. Moreover, negative threshold voltage shift becomes more severe with a more obvious hump in ${C}-{V}$ characteristic curves under back-light illumination of a shorter width device, a phenomenon which has been verified by simulation.

A new multiple-gate poly-Si thin-film transistor (TFT) with a bottom field plate (FP) is proposed. The FP disperses the high current density away from the top corner of the spacer channel with the highest electric field, leading to an improved kink effect. Moreover, owing to an inversion layer induced by the FP at the bottom region of spacer poly-Si channel, a higher on-state current is achieved. In addition, the electric field near drain area is reduced, leading to a lower off-state current. Overall, the new multiple-gate poly-Si TFT shows improved characteristics as compared with the counterpart without a bottom FP.

This paper investigates the impact of fin width ( Wfins = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various Wfins is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as Wfin is reduced. A thinner Wfin FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest Wfin FinFET possesses the largest bulk oxide trap density (NBOT) than that of a thicker Wfin FinFET. Moreover, the noise of the thinnest Wfin (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest Wfin FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI.

Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V/sub t2/, I/sub t2/) of ESD protection devices under various metal level stack structures, shows that i) I/sub t2/ depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V/sub t2/ increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and DC electrical stress by transmission line pulse, as well as AC electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads are independent of bonding pad metal level structures.