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In this article, the single-event-transient (SET) in reconfigurable field-effect transistor (RFET) is evaluated by 3-D technology computer-aided design (TCAD) simulation for the first time. The effects of linear energy transfer (LET) values, electrical bias, strike location, and angle are investigated in detail. For heavy ion with LET of 10 MeV·cm²/mg and characteristic radius of 1 nm, the peak value of drain SET current is up to 0.237 mA for n-type program, which is much higher than the saturated conduction current of 2.22 μA/μm. The peak SET current increases from 0.18 to 0.36 mA as $V_{DS}$ ranges from 0.8 to 1.4 V. The drain voltage ( $V_{DS}$ ) has a great impact on SET response and a higher lateral electric field will worsen the SET effects. The most sensitive position is confirmed to be not only related to the electric field distribution, but also the distance away from drain terminal. A serious SET effect is observed with a smaller angle. Furthermore, the impact of SET effect on NAND2/NOR2 multifunctional logic gates circuit based on RFETs is also evaluated. When striking the end of the changing edge of the input signal, the rise and fall relative propagation delays of NAND2 logic gates circuit are up to 34.49% and 35.04% respectively, with LET of 6 MeV·cm²/mg. This work provides guidelines for RFET radiation-hardened technology in future extreme environment electronics applications.

Design optimization of emerging nanoscale transistor technologies often requires careful design tradeoff between many objectives, including speed, power, variability, and so on. By leveraging machine learning (ML) methods, we develop a multiobjective optimization (MOO) framework for 2-D-material-based field-effect transistors (FETs) near the scaling limit. The MOO design framework performs gradient-free efficient global optimization and offers the option of using active learning. Optimum designs with a tradeoff between transistor speed, power, and variability are identified automatically for transition metal dichalcogenide (TMDC) and black phosphorene FETs by applying the MOO design framework that couples ML methods to quantum transport device simulations. The design optimization results show that the International Roadmap of Devices and Systems (IRDS) target of 2025 and 2028 technology nodes can be met by 2-D FETs.

We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on 2-D materials. The electrostatics along the electrolyte-gated 2-D-semiconductor stack is treated by solving the Poisson equation, including the site-binding model and the Gouy–Chapman–Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2)-based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations.

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/Hf x Zr1- x O2/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO2 or SiON) and Hf x Zr1- x O2 materials ( ${x} =0.75$ , 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization ( ${P}_{\text {s}}{)}$ of the Hf x Zr1- x O2 decreases from $25.9~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.5Zr0.5O2) to $20.3~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.6Zr0.4O2), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when ${P}_{\text {s}}$ further decreases to $8.1~ \boldsymbol {\mu }\text{C}$ /cm2 (Hf0.75Zr0.25O2), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of ${P}_{\text {s}}$ could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.

This article investigates the applicability of dual-material gate-oxide-stack double-gate tunnel field effect transistor (DMGOSDG-TFET) as a biosensing element with the ability to assess the health parameters and disease onset. For this, employment of gate work-function engineering along with the gate-oxide-stack approach and asymmetrical doping at ${p}^{+}$ source and ${n}^{+}$ drain region are introduced for the first time to implement DMGOSDG-TFET-based biosensor. Also, a nanogap cavity is created by etching a portion of gate dielectric material toward the source end for the accomplishment of biomolecules conjugation in the proposed device. The main focus of this article is to estimate the underlying device sensitivity in the presence of different charged as well as neutral biomolecules. To explore such effects, different dielectric constants and negative charge densities of the biomolecules are considered independently in the nanogap cavity. Next, the sensing performance of the presented device is analyzed in terms of switching-ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), transconductance-to-current ratio ( ${g}_{m}/{I}_{ds}$ ), and average subthreshold-swing. A deep investigation of device performance is also performed with different fillings of the nanogap cavity and step-profiles arising out from the steric hindrance. The device sensitivity is analyzed for different cavity lengths and cavity thicknesses for the best outcomes. In addition, a comparative sensitivity analysis of DMGOSDG-TFET with single-material gate-oxide-stack double-gate tunnel field effect transistor (SMGOSDG-TFET) and metal–oxide–semiconductor field effect transistor (MOSFET)-based biosensor is also presented in this work. The device implementation and all the simulations are carried out using technology computer-aided design (TCAD) tool. All of the sensitivity-assessments disclose that DMGOSDG-TFET can be a good candidate for biosensing applications.

In this article, we propose a standard ternary inverter (STI) based on a dual-pocket tunnel FET (DP-TFET) for low-power applications. Using 2-D device simulations, we demonstrate that if appropriate doping concentration and length are chosen for the dual-pocket, then the device can exhibit ternary inverter voltage transfer characteristics (VTCs) with three stable output voltage levels. Ternary inverter characteristics are obtained by two tunneling mechanisms in the device: 1) gate bias-independent within-channel tunneling and 2) gate bias-dependent source-channel tunneling. We also demonstrate that the ternary inverter obtained could be operated at different supply voltages by controlling the pocket doping concentration.

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- ${k}$ (Hk) MOSFET concept in this article with the step high- ${k}$ insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of $42~\mu \text{m}$ . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Bias Temperature Instability (BTI) has always been a critical reliability issue in a field effect transistor (FET). In a negative capacitance (NC) FET, a study of BTI with considering the traps at different interfaces is needed to investigate the device performance, which is not yet explored. In this work, for the first time, we have addressed the individual and the combined effect of bulk traps and the interface traps introduced at different interfaces in an NC fully depleted silicon on insulator (FDSOI) FET. We found: 1) interface Si–SiO2 and SiO2–HfO2 or bulk HfO2 traps nullify the threshold voltage variation and 2) the presence of traps changes the ferroelectric (FE) polarization and in turn vertical field distribution which leads to an increased OFF current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ). Further, it causes the early end of lifetime (EOL) due to bulk HfO2, and HfO2–SiO2 traps for NC FDSOI. These results have been extracted by using a well-calibrated TCAD framework. Since the current amplification and the subthreshold reduction in NC transistors can be achieved by increasing the FE thickness; but in our work, we found that increasing the thickness is not appropriate as the higher FE thickness predominantly degrades the NC device performance, and a thickness optimization is highly required from the reliability perspective.

Semiconductor doping is limited by such practical concerns as bandgap narrowing and solid solubility limits of dopants. Bound-charge engineering (BCE) bypasses these limits by doping with surface bound charge located on the interface between a semiconductor and an adjacent low-permittivity oxide; it can be used to reduce depletion lengths of junctions in field-effect transistors (FETs). BCE is established by basic electrostatics and is widely applicable to emerging materials and novel devices. In this work, an analytical surface potential model for gate-all-around BCE-assisted silicon nanowire FETs, with arbitrary and possibly distinct spacer and gate oxides, is derived. This model is based on scaling theory and verified against atomistic quantum transport simulations; it provides an intuitive formalism for developing and modeling devices with BCE.

The p-n homojunction devices based on 2-D-layered materials (2DLMs) with unusual physical characteristics are gaining extensive research on their use in photodetectors. However, the current fabrication of p-n homojunction devices based on 2DLMs needs a complex doping method. In our work, the laser-irradiation method is a simple and straightforward selective p-type doping technique for the 2-D semiconductor molybdenum ditelluride (MoTe2). The laser-oxidized product MoO x is responsible for p-type doping in MoTe2. The laser-irradiation technique has been used to directly write an in-plane MoTe2 p-n homojunction device, where the laser-scanned region is p-doped and the neighboring region is electrically n-doped by applying a positive back-gate voltage. The MoTe2 p-n homojunction device has been used as a photodetector, which shows a high photoswitching ratio of 105 under the illumination of 633 nm at $6.5~\mu \text{W}$ and a short photoresponse time of $232~\mu \text{s}$ . The selective p-doped technique using a laser-irradiation method can be used in future logic circuits based on 2-D materials.

Hf0.5Zr0.5O2 (HZO)-based ferroelectric field-effect transistors (FeFETs) with HfO2 seed layer were investigated for radiation-hard nonvolatile memory applications. First, it was found that the HZO thin films grown on HfO2 seed layer showed improved crystallinity and ferroelectricity compared with those directly grown on SiO2 thin film, leading to a larger memory window (MW), better endurance, and retention properties of the HZO-based FeFETs with HfO2 seed layers. Moreover, after 1 Mrad(Si) 60Co $\gamma $ -ray irradiation, the memory properties of the HZO-based FeFETs with HfO2 seed layer were also better than those without the HfO2 seed layer. Especially, the HZO-based FeFETs with an HfO2 seed layer have a larger remaining MW (0.66 V) than that (0.29 V) of the FeFETs without an HfO2 seed layer after $1\times 10^{4}$ program/erase cycle. This work represents a first attempt to realize the high performances of radiation-hard HfO2-based FeFETs.

2-D layered MoS2 is considered as a promising candidate for novel nanoelectronic devices in recent years. However, a large number of structural defects in MoS2 have been widely reported, which will greatly degrade the electrical performance of MoS2 devices. In this work, it is demonstrated that the structural defects in MoS2 can be repaired by a reasonable-power O2-plasma treatment, e.g., a 30-W O2-plasma treatment on MoS2 results in an enhanced carrier mobility of 69.82 cm2/Vs, which is 2.5 times higher than that of the untreated devices, a reduced subthreshold swing of 131.27 mV/dec, and a high ON/OFF current ratio of $3.18\times 10^{{6}}$ . These are attributed to the fact that the suitable-power O2-plasma treatment can effectively repair the structural defects in MoS2 and reduce the scattering centers, improving the electrical performance of MoS2 FETs. However, a high-power O2 plasma will generate high-energy oxygen ions to bombard the MoS2, introducing more new defects and deteriorating the electrical performance of MoS2 FETs.

This work explores the fabrication and characterization of an ionic liquid channel field effect transistor (FET) incorporated within the trench structure on SiO2. The trench structure allows any liquid to be accommodated, thereby eliminating the mold creation on the device or the requirement for an intricate architecture to store liquid. For the fabrication of the trench, we followed a standard photolithography process with the help of selective etching of aluminum and SiO2. The fabricated trench surface is characterized using atomic force microscopy (AFM) and contact angle analysis. The electrical characterization of the proposed FET structure is also performed with 0.01-mM potassium chloride (KCl) solution as an ionic channel. We tested both the n-FET and p-FET type characteristics which can be controlled by the back gate biasing condition. The dc characterization shows a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 105 for both the n-FET and p-FET. The device further shows an improvement in K+ mobility and Cl− mobility of $2.24 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ and $4.96 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ , respectively. We also carried out the FET structure modeling to estimate the effective ${C}_{{\mathrm {ox}}}$ for the trench SiO2 structure. It is observed that the total capacitance after the inclusion of Debye length is $1.29 \times 10^{-4} {\mathrm {F/m}}^{2}$ . Furthermore, the number of ions is also calculated from the electrical characteristics, and it is almost comparable with the number of ions in the molar solution. Overall, the proposed fabricated structure, although simple, enables to accommodate any liquid as a channel and provides an easy way to develop electrolyte-based sensors.

This article reports on the use of transfer doping (TD) to create holes in a diamond substrate using defects in Al2O3 that are located at an energy below the top of the diamond valence band. The energy bands of a metal–Al2O3–diamond structure are analyzed for use as a method to make electrical contact to the diamond. The structure is also analyzed for use as part of a field-effect transistor, where the metal acts as the gate. While it is found that the metal can easily dominate the charges in a thin Al2O3 layer, preventing efficient TD of the diamond, we found that the use of a thick Al2O3 layer, a high defect density, or a high work function metal can all serve to permit efficient TD. It is shown that a metal–Al2O3–diamond structure, utilizing a high defect density in a few nm thick Al2O3 layer, can provide a good electrical contact to the diamond because electrons can tunnel through the Al2O3 layer and because a high hole concentration is formed under the metal contact in the diamond substrate.

The operation of reconfigurable field effect transistor (RFET) is governed by Schottky barrier, ungated regions as well as control and polarity gates. The inherent architecture of RFET, apart from lowering the effective drain bias, impedes the use of existing mobility extraction methodologies. In this brief, we propose a simple and effective methodology to evaluate the resistance offered by various regions, ascertain the effective drain bias across the un-gated transistor, and extract apparent low field mobility and its degradation coefficients in RFET. The developed analytical expressions for drain current ( ${I}_{{\text {DS}}}$ ) and transconductance ( ${g}_{m}$ ) of RFET are able to accurately predict current ( ${I}_{\text {DS}}$ ) - control gate ( ${V}_{\text {CG}}$ ), and ${g}_{m}$ – ${V}_{\text {CG}}$ characteristics.

The poor response time and incomplete recovery of MoS2 sensor at room temperature (RT) have been a serious issue to obstruct its widely sensing applications. In present work, we comprehensively studied three methods: rising temperature, building field-effect transistors (FETs), and adding light illumination to improve the performance of the device. The related sensing mechanism of the three processes was also analyzed. The high response rate up to 2510%, low theoretical concentration detection limit down to 693 ppb, and excellent recovery at RT to NO2 were achieved for the MoS2 FET sensor with the aid of light illumination. This significant improvement in sensing performances is mainly attributed to the activated sensing layer by phonon energy transfer and enhanced population of the charge carrier raised from optical energy. Schottky barrier modulation was also an important factor to impact sensing performance. Furthermore, the MoS2 nanosheets exhibit good photosensing characteristics such as rapid photon response, high light-induced photocurrent, and so on. It has been demonstrated that the light illuminated FET configuration can effectively accelerate response time and promote recovery rate of MoS2-based sensor operating at RT, which provides a strategy to design an optoelectronic device with optimal sensing properties.

The outstanding physical and electrical properties of transition metal dichalcogenides (TMDs) as semiconductor materials demonstrate a promising platform for future electronic devices. Among all the TMDs, MoTe2, in which the bandgap is close to that of the silicon (Si), is a more favorable candidate than others to be applied in next-generation integrated circuits (ICs). However, the conventional physical or chemical doping method is complicated for fabricating the MoTe2 logic ICs. The transistors with additional polarity gates (PGs) are defined as polarity-controllable transistors (PCTs). The PG can dynamically control the type of charge carriers (n- or p-type) in the source/drain by electrostatic doping without the need of any physical or chemical doping, and thus reconfigure the transistor between n-type and p-type. In our work, the ambipolar conduction property in MoTe2 enables the fabrication of high-quality polarity-controllable MoTe2 transistors (PCMTs) that are promising as building blocks to construct the MoTe2 logic ICs. The on/off ratios of the PCMTs are above 107 for both n-type and p-type. The highest field-effect mobility $\mu $ of p- and n-type MoTe2 transistors are 38 and 42, respectively. The inverter (INV) based on the PCMTs has achieved a high gain of 37. Furthermore, the logic-gate cell library, which includes INV, negative- AND (NAND), negative- OR (NOR), exclusive- OR (XOR), and maJority (MAJ) is demonstrated using PCMTs. The above-mentioned desirable properties make PCMTs promising for future applications in 2-D-semiconductor-material-based logic ICs.

In ultrascaled field-effect transistors (FETs), the thermionic limit to subthreshold swing (SS) represents a serious issue impeding their low-power application. Here, we propose a novel tunneling cold source FET (TCS-FET) to realize steep-slope (with SS less than 60 mV/dec) low-power devices, in which a p-n junction serves as cold source as a result of self-filtering of the electronic thermionic tail. Our first-principles calculations on the electrical properties of the TCS-FET based on monolayer MoS2 predict that large ON/OFF current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) up to $1.6 \times 10^{9}$ and steep SS as small as 32 mV/dec can be obtained. Moreover, by considering atomic doping at the source, we demonstrate that defects engineering is effective in optimizing both ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ and SS of the devices. This study is important for guiding the design of nanoscale steep-slope FETs based on 2-D materials.

Analytical models of low-frequency noise (LFN) characteristics for planar-type tunnel field-effect-transistors (TFETs) are proposed. A surface-potential-based current–voltage model is developed to physically represent the current fluctuation due to charge trapping/detrapping in the gate dielectric. An LFN model can be analytically derived from the current fluctuation with a reasonable approximation. The proposed model is verified using Technology Computer Aided Design (TCAD) and measurement data, which are in good agreement with each other. The analytical model can not only serve as a valuable reference and tool for low-power analog circuit design but also provide physical insights into the LFN of TFETs.

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Three-independent-gate FETs (TIGFETs) are Schottky-barrier-based devices, which can be reconfigured to be either n- or p-type allowing for innovative compact logic gate implementations. In this article, we present an aggressively scaled 10-nm gate-all-around silicon–germanium nanowire TIGFET device evaluated with Synopsys Sentaurus Poisson-based Technology Computer-Aided Design (TCAD) simulations at a 0.7-V nominal supply voltage as typically used at this technology node. The operation of the TIGFET device is described in detail, with particular care given to the majority current contributions for each operating mode. When considering a silicon–germanium channel, the maximum TCAD-simulated current drive is 880.20 and $806.58~\mu \text{A}/\mu \text{m}$ for n- and p-type operation, respectively, thus making TIGFET devices competitive with FinFET technology at the 10-nm node. These simulations are verified using device physics calculations. Further simulations of the carrier densities for each of the TIGFET-operating configurations are performed to confirm that the simulated device is operating as intended.

The HfZrO x (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass-produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current–voltage, capacitance–voltage, and polarization–voltage measurements to test high- and low-temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory.

Steep-slope switching is effective to reduce the required energy for switching, however, at least 60 mV of gate voltage is required to modulate the current by an order of magnitude at room temperature. In this article, a numerical study of cold-source transistors based on chiral graphene nanoribbons (CGNRs) is presented. In cold-source transistors, the high-energy electrons are filtered out to break the room-temperature limitation, which can be realized by using CGNRs with narrow density of states (DOS) distribution. Our numerical results indicate that CGNR transistors can achieve sub-60 mv/decade subthreshold swing and similar ON-state current to conventional transistor. Moreover, the effect of the DOS distribution of CGNRs on the transport characteristics is investigated. This work provides a potential option for low-power electron devices and provides guidance for the design of cold-source transistors.

In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length ( ${L}_{\mathrm {ch}}$ ) and channel thickness ( ${T}_{\mathrm {ch}}$ ) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing.

Recently, 2-D transition metal dichalcogenides (TMDs) lateral heterojunction field-effect transistors (FETs) have been demonstrated experimentally, in which metallic TMDs were used for the source/drain. In this work, we systematically investigate the contact property and device performance of monolayer 1T/1T $^{\prime }$ -2H MoS2, MoSe2, and MoTe2 FETs. Schottky barrier (SB) heights are extracted from density functional theory calculations, and nonequilibrium Green’s function transport simulations have been performed to study device characteristics. Our simulation results show that the inherent SB strongly affects the overall performance of these devices. Here, we optimize the performance of TMD lateral heterojunction FETs by using two different approaches. First, we have improved the electrostatic control by scaling equivalent oxide thickness and gate underlap, which boosts both ON- and OFF-state characteristics, making the device suitable for high-performance applications. On the other hand, moderate doping has been used in the gate underlap region, improving ON/OFF current ratio with negligible impacts on ON-state characteristics, and this approach is more preferred for low-power applications. This study reveals that 1T $^{\prime }$ -2H MoTe2 FET shows the highest ON current ( $\sim 1$ mA/ $\mu \text{m}$ ) among the three with a reasonably small subthreshold swing (80 mV/dec) if properly scaled, while 1T-2H MoS2 FET exhibits the highest ${I} _{\scriptscriptstyle{\text{ON}}}/{I} _{\scriptscriptstyle{\text{OFF}}}$ (~107) when ohmic contact is established with moderate doping in the gate underlap region. This study not only provides physical insight into the electronic devices based on novel TMD heterostructures but also suggests engineering practice for device performance optimization in experiments.

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at ${V}_{\text {DD}}$ /2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NM $_{M}$ ) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization ( ${P}_{r}$ ) and coercive electric ( ${E}_{C}$ ) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states.

Low-frequency noise characteristics of ZnO nanowire field-effect transistors (FETs) are presented at temperatures down to 10 K. The carrier number fluctuation (CNF) model and Hooge’s model are used to analyze the low-frequency noise in the studied devices. From 293 down to 200 K, the normalized noise power spectrum density (PSD) is proportional to $({g}_{m}/{I}_{d}{)}^{{2}}$ due to CNF caused by the trapping and detrapping process between the channel carriers and oxide traps near the semiconductor and the dielectrics interface. In this case, the low-frequency noise is induced by flat-band voltage fluctuation. The density of the traps in the gate dielectrics near the Fermi level ranges from 9.4 $\times \,\,10^{{10}}$ to 3.8 $\times \,\,10^{{10}}$ cm $^{-{2}}$ eV $^{-{1}}$ from 293 and 200 K. At lower temperatures, from 150 down to 100 K, the noise mechanism is mobility fluctuation, attributed to electron and space-charge scattering due to the hoping process and slow motions of electrons. The extracted Hooge’s parameter in this temperature ranges in the order of $10^{-{3}}$ to $10^{-{2}}$ . In the temperature range from 30 down to 10 K, the low-frequency noise is dominated by both CNF and mobility fluctuation caused by Coulomb scattering between oxide traps and electrons.

We present a nonvolatile resistive-gate metal–oxide–semiconductor-field-effect transistor (RG-MOSFET). An RG-MOSFET comprises a MOSFET and dielectric layers sandwiched between the top and bottom electrode metal–dielectric–metal (MDM). The gate of the MOSFET is electrically connected to the bottom electrode of MDM in series. Dielectric layers of MDM are composed of a resistance-switching layer made by hafnium oxynitride (HfON) and a resistance-nonswitching layer by hafnium dioxide (HfO2). RG-MOSFET as a memory can be achieved by resistance changes in the HfON. Eight distinguishable resistance values can be programmed randomly, which is performed as a 3 bit per cell through the edge Fowler–Nordheim (FN) mechanism between the top electrode metal and the drain of RG-MOSFET. The external voltage applied to the top electrode is divided by the MDM and the gate dielectric, and the threshold voltage ( ${V}_{\text {th}}$ ) of an RG-MOSFET is modulated by different resistance values of MDM. Therefore, states stored in MDM can be read out from the drain-current level of an RG-MOSFET. FORMing-free characteristic of MDM is required for bipolar operation. A ratio of drain current between the high-resistance state (HRS) and the low-resistance state (LRS) is $10^{{5}}$ . Gradual SET/RESET is executed to tune the drain current by pulse operations; $10^{{5}}$ endurance cycles of RG-MOSFETs are demonstrated, and a retention test can be passed for more than ${5} \times 10^{{6}}$ (35 days) at 125 °C.

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS2 field-effect transistors (FETs) are investigated. The experimental results show that MoS2 FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO2 dielectric, which will couple with the carriers in MoS2 channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS2 FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS2 FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS2 FETs.

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration ( ${N}_{\text {ch,eff}}$ ). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage ( ${V}_{\text {TH}}$ ) increases as the ${N}_{\text {ch,eff}}$ of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower ${N}_{\text {ch,eff}}$ show the more severe rate of deterioration in the transconductance ( ${G}_{\text {m}}$ ) and ON current ( ${I}_{\text {ON}}$ ). By increasing ${N}_{\text {ch,eff}}$ to reduce the electric field ( ${E}$ -field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage ( ${V}_{\text {GOD}} = {V}_{G}$ – ${V}_{\text {TH},\text {initial}} = -{3.5}$ V) to perform the NGBS test.

We analyzed the low-frequency noise (LFN) of dual-gated field-effect transistor (DG-FET) biosensors with Schottky contacts. We found the flicker noise at the sensing insulator–semiconductor interface to be the major noise source while employing Schottky contacts to have minimal noise contribution with a sufficiently large back-gate bias voltage. The measured noise dependence on transconductance further indicated the presence of a nonuniform energy distribution of interface trap density at the said sensing interface. Based on these findings, we argued that the DG structure is advantageous over its single-gated (SG) counterpart; although they possess the same intrinsic lower limit of detection (LLOD), the former could offer a larger signal gain at the optimum LLOD thanks to sufficient channel carrier supply through back-gating instead of biasing the sensing interface toward band edge with higher trap density.

In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the parameter extractions of vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) devices, combining the capacitance characteristics of gate–source, ${C}_{\text {GS}}$ ( ${V}_{G}$ ) and gate–drain ${C}_{\text {GD}}$ ( ${V}_{G}$ ), measured using the above cited technique, with those measured conventionally. In doing so, we have been able to extract semiconductor capacitance ( ${C}_{\text {SC}}$ ), interface trap capacitance ( ${C}_{\text {it}}$ ), doping profile concentration ${N}$ ( ${x}$ ), and interface trap density ${D}_{\text {it}}$ ( ${E}$ ) of different regions of VDMOSFET.

In spite of the increasing use of machine learning techniques, in-memory computing and hardware have increased the interest to accelerate neural network operation. Henceforth, novel embedded nonvolatile memories (eNVMs) for highly scaled technology nodes, like ferroelectric field effect transistors (FeFETs), are heavily studied and very promising. Furthermore, inference and on-chip learning can be fostered by further eNVM technology options, such as multibit operation and linear switching. In this article, we present the advantages of hafnium oxide-based FeFETs for such purposes due to their basic three-terminal structure, which allows to selectively activate or deactivate selected devices as well as tune linearity and dynamic range for certain applications. Furthermore, we discuss the impact of the material properties of the ferroelectric layer, the interface layer thickness, and scaling on the device performance. Here, we demonstrate good device properties even for highly scaled devices ( $100\,\,nm \times 100$ nm).

The organic field-effect transistors (OFETs) have developed rapidly in recent years. However, compared with the p-type OFETs, the n-type devices always show poorer performance due to their hard electron injection and low stability. It is necessary to further improve the charge injection properties of n-type OFETs. In this work, indium (In) layers, as an interlayer above contacts, were adopted for electron injection improvement in the n-type poly((N, $\text{N}^{\prime }$ -bis(2-octyldodecyl)-1,4,5,8-naphthalenedicarboximide-2,6-diyl)-alt-5, $5^{\prime }$ -(2, $2^{\prime }$ -bithiophene)) (N2200) OFETs. The injection barrier, such as Schottky barrier, at the metal/semiconductor interface was effectively weakened with the In interlayers thickness ( ${T}_{In}$ ) increasing from 0 to 6 nm. The mechanism of electron injection changed from thermionic emission to tunneling, as the ${T}_{In}$ reaching 6 nm. It results in a marked improvement in electrical properties for N2200 OFETs. The mobility increased from 0.09 to 0.29 cm ${}^{2}\cdot \text{V}^{-1}\cdot \text{s}^{-1}$ while the subthreshold swing decreased from 2.7 to 0.8 $\text{V}\cdot $ dec−1 with the ${T}_{In}$ . This work provides an efficient approach for the electron injection improvement in n-type OFETs.

Electrospinning one-dimensional (1-D) semiconductor nanofibers have been regarded as one of the most promising building blocks for future nanoelectronics with high performance because they can exhibit a broad range of device functions. However, electronic devices based on electrospinning-driven nanofibers often suffer from poor performance and inferior quality. In current works, continuous and uniform high-quality indium oxide (In2O3) nanofibers were obtained by electrospinning. The surface morphology, crystallinity, optical, and electrical properties of the In2O3 nanofibers were investigated by X-ray diffraction, scanning electron microscopy, optical spectroscopy, and electrical measurements. It has been detected that the field-effect transistors (FETs) with optimized electrospinning time of 30 s demonstrated superior electrical performance, including a high field-effect mobility ( $\mu _{{\mathrm {FE}}}$ ) of 9.1 cm $^{2}\cdot \text{V}^{-1}\cdot \text{s}^{-1}$ and a large ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of 107. The high- ${k}$ Al2O3 dielectric layer has also been used to greatly reduce the operating voltage (from 30 to 3 V), significantly improve $\mu _{{\mathrm {FE}}}$ (to 27.7 cm $^{2}\cdot \text{V}^{-1}\cdot \text{s}^{-1}$ ), and strengthen stability over cycling. To prove the device’s potential in more complex logic circuit applications, a resistor-loaded inverter was further integrated, and the maximum voltage gain of 9.8 was demonstrated at an ultralow operating voltage of 3 V. The present findings have demonstrated that electrospinning can potentially be used as a straightforward and cost-effective means for the assembly of 1-D nanostructures for use in next-generation low-power devices.

Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate–drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design.

Ultrascaled WS2 field-effect transistors (FETs) fabricated on exfoliated multilayer channels with excellent ON-state and OFF-state performance are reported. Recorded high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and ultralow contact resistance ( ${R}_{C}$ ) were achieved in a double-gated FET at a scaled overdrive voltage ( ${V}_{OV}\boldsymbol = {V}_{GS}\boldsymbol -{V}_{TH}$ ), reaching >600 ( $\boldsymbol \mu \text{A}/\boldsymbol \mu \text{m}$ ) normalized to footprint at ${V}_{DS}\boldsymbol =1$ V and ${V}_{OV}\boldsymbol =2$ V with a ${R}_{C}~\sim ~500$ ( $\Omega \times \mu \text{m}$ ). We report statistics of more than 50 FETs with varying channel lengths, showing excellent OFF-state behavior with small threshold voltage ( ${V}_{TH}$ ) variations, near-ideal subthreshold slope (SS), and small drain-induced barrier lowering (DIBL). Various channel thicknesses ( ${T}_{CH}$ ) ranging from 2.1 to 7 nm were carefully evaluated in terms of short channel effects (SCEs) and ON-state current, and a WS2 body thickness of 2.1 nm (three layers, the thinnest in our statistics) shows the best performance in both ON-state and OFF-state.

The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The “cantilever” or “airbridge” structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the $\text{P}\boldsymbol +$ source and effectively cuts the leakage current path off. The InAs $\boldsymbol /$ GaSb LTFETs with this buried drain technique exhibits ${I}_{ \mathrm{\scriptscriptstyle ON}} \boldsymbol / {I}_{ \mathrm{\scriptscriptstyle OFF}} > {10}^{{7}}$ and SS $\boldsymbol /$ dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications.

In this article, the transfer and output characteristics of an electrostatically doped (ED) 4-armchair silicene nanoribbon (4-ASiNR) field-effect transistor (FET) with three gates are investigated. The numerical simulations are carried out based on the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Green’s function (NEGF) formalism, implemented in the NanoTCAD ViDES simulator. Results show that ED SiNR-FET has better characteristics than chemically doped (CD) SiNR-FET. Additionally, ED-device is inherently free of negative impacts of impurities on the transistor’s performance. The ED SiNR-FET functionality is analyzed using different channel lengths, introducing the extended channel ED-device (ECED) with an improved ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $3.8\times 10^{5}$ and a significant ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of 4.6 mA/ $\boldsymbol \mu \text{m}$ . A 15 nm ECED SiNR-FET with an 8 nm channel is studied under different temperatures and supply voltages. Based on the results, low-power (LP) and high-performance (HP) applications are suggested for the ECED-device, with the minimum subthreshold swing of 64 mV / dec and the maximum transconductance of $63~\boldsymbol \mu \text{S}$ , respectively.

A novel post-oxidation annealing (POA) process with supercritical N2O (SCN2O) fluid is reported to be highly effective in improving the interface properties of the SiO2/4H–silicon carbide (SiC) (0001) systems. After SCN2O POA, the interface state density reduces to $2.8 \times 10^{{11}}$ eV−1cm−2, which is about 3.5 times lower than that after a traditional high-temperature N2O POA process. Meanwhile, the highest oxide critical electric field shows an increase of 18.19% and the near-interfacial oxide traps is reduced by 69.90% compared with that after N2O POA process. The process temperature is as low as 120 °C. The significantly reduced processing temperature avoids additional defect generation while the supercritical state provides a stronger nitridation effect. SCN2O annealing is a promising candidate for POA process toward high-performance SiC power metal-oxide-semiconductor field effect transistors (MOSFETs).

We fabricate Josephson junction field-effect transistors (JJ-FETs) using InAs quantum well heterostructure as the channel, epitaxial Al as superconducting electrodes, and scaled-down Al2O3 gate dielectrics. A systematic investigation of the gate voltage ( ${V}_{{G}}$ ) dependence of the critical current, normal state conductance, and characteristic voltage of the JJ-FETs coupled with capacitance measurements reveals different ${V}_{{G}}$ regimes in the proximity effect characterization of JJ-FETs. Self-consistent Poisson–Schrodinger simulations allow us to associate these ${V}_{{G}}$ regimes with the carriers populating one or more subbands at different vertical locations in the heterostructure. We also discuss the importance of oxide/channel interface quality and its impact on the practical implementation of JJ-FET Boolean logic gates with signal restoration.

The OFF-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ ) and threshold voltage ( ${V}_{{\mathrm {T}}}$ ) of a HfO2-based threshold-switching (TS) device for phase-transition fully depleted silicon-on-insulator (FDSOI) device on silicon substrate can be improved, e.g., ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ is increased by implementing a multilayered HfO2/Al2O3 (rather than HfO2 layer only). The HfO2/Al2O3 layer with the atomic layer deposition (ALD) cycle ratio of 3:1 (i.e., Hf:Al = 3:1) shows approximately $3.47\times 10^{11}\,\Omega $ of average ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ and approximately 2.12 V of average ${V}_{{\mathrm {T}}}$ . Next, ${V}_{{\mathrm {T}}}$ can be modulated by adjusting the work function of the bottom electrode. We demonstrate that a high work function of the bottom electrode results in stronger built-in electric-field and tunneling, decreasing ${V}_{{\mathrm {T}}}$ and ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ . The Hf3Al1-based TS device with platinum electrode shows approximately 0.88 V of average ${V}_{{\mathrm {T}}}$ and approximately $2.81\times 10^{9}\,\Omega $ of average ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ . The phase-transition FDSOI device used in this work is fabricated by connecting the optimized TS device in series to the drain electrode of a baseline FDSOI device, whose channel length is 130 nm. The phase-transition FDSOI device shows the minimum subthreshold slope of 9 mV/decade owing to the abrupt resistive switching of the TS device. Additionally, it exhibits an increase in the ON/ OFF-state current ratio by three times because of high ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ .

AlGaN/gallium nitride (GaN) ion-sensitive field-effect transistors (ISFETs) were fabricated as pH sensors. The sensitivity of the AlGaN/GaN ISFETs was evolved with gate recess process and ammonium hydroxide (NH4OH) treatment. By performing the gate recess process, the threshold voltage ( ${V}_{\text {T}}$ ) of the ISFET increased from −3.33 to −0.31 V and the maximum conductance ( ${G}_{\text {M}}$ ) of the ISFET increased from 0.8 to 2 mS, with the current sensitivity of the pH sensor improving from 52.25 to $78.86~\mu \text{A}$ /pH. Further, after performing the ammonium hydroxide treatment, the ${V}_{\text {T}}$ of the ISFET increased from −0.33 to −0.14 V, with the current sensitivity of the pH sensor improving from 78.86 to $84.39~\mu \text{A}$ /pH. To characterize the surface conditions the X-ray photoelectron spectroscopy (XPS) was deployed. The results indicated that many nitrogen vacancies ( ${V}_{\text {N}}$ ) were introduced during the recess process, leading to a negative ${V}_{\text {T}}$ shift and a smaller potential sensitivity ( ${S}_{V}$ ), which can be improved by ammonium hydroxide treatment.

This article reports fabrication and characterization of field effect transistor (FET) device consisting of zinc oxide (ZnO) nanoparticle–glutathione-S-transferase (GST) composite channel for successful in vitro detection and quantification of glutathione (GSH) in solution and in cancerous cell. The functionalized channel layer is synthesized by means of electrostatic binding between ZnO nanoparticles and GST. Detection of glutathione can be confirmed by the change in output current characteristics of the device in real time whenever the conjugation reaction between GSH and 1-chloro-2, 4-dinitrobenzene (CDNB) in the presence of GST takes place on the channel of the device. The characterized device had a sensitivity of $60.22~\mu \text{A}$ /dec and limit of detection (LoD) of 43.96 nM. Thus, from the device characteristics, GSH could be quantified. Subsequently, laboratory grown HeLa, MCF-7 (both cancerous), and human embryonic kidney (HEK-noncancerous) cells were characterized with the fabricated device and both the cancerous cells resulted in significantly higher drain current compared to noncancerous HEK cells. The fabricated device resulted in a sensitivity of 210.86 nA/cell and LoD of 30 cells when characterized with HeLa cells. This detection paves way for a device-based early detection scheme for cancer by measuring the GSH concentration in human cell cytosol.

The ferroelectric (FE) polarization switching behavior in the HfZrO2 (HZO) FE/dielectric (FE/DE) stack is investigated systematically by charge responses from pulse measurements. The trapped charge density at the FE/DE interface related with the FE polarization switching is found to be $1.2\,\times \,10^{14}$ cm−2 according to the leakage-current-assist polarization switching mechanism. Furthermore, by the time-dependent nonswitching charge responses, the extra FE/DE interface trap density of $1.1\,\times \,10^{13}$ cm−2 is confirmed, which is not related but can be detected along with the FE polarization switching. The quantitative characterization reveals the huge amount of FE/DE interface traps and their dominant role in the FE operation of HZO FE/DE stack, which improves the proposed leakage-current-assist polarization switching model. This improved model provides a more comprehensive understanding of the polarization switching in the HZO FE/DE stack and new insights on HZO negative-capacitance (NC) and FE field-effect transistors (FETs).

Wearable bio-sensing devices are considered promising for ubiquitous heath monitoring. To accurately read out small bio-signals, the development of high-performance flexible front-end circuits is crucial. Oxide semiconductors are considered one of the most promising active channel materials for on-polymeric-foil electronics. In this article, a high-gain flexible complementary metal–oxide–semiconductor (CMOS) inverter with a beta ratio of 1, a desirable feature for device miniaturization, was demonstrated by monolithically integrating a top-gated n-type indium gallium zinc oxide (IGZO) thin-film transistor (TFT) and a bottom-gated p-type SnO TFT on a 5.5- $\mu \text{m}$ -thick polyimide substrate. The influence of atomic layer deposited (ALD)-HfO2 capping layer on the properties of oxide active channels has been analyzed. The flexible inverter exhibited a high static voltage gain of 370 V/V and balanced noise margins (noise margin high of 4.8 V, noise margin low of 4.7 V) for a supply voltage of 10 V. In addition, the voltage transfer characteristics remained virtually unchanged when the device was subjected to an outward or an inward bending radius of 2.5 mm, indicating the complementary oxide-TFT-based inverter is practical for flexible electronics applications.