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In this paper, a single-inductor dual-output (SIDO) dc–dc converter is proposed. The significant feature of the proposed converter is feeding a constant power load in low-voltage side (LVS) port, where even feeding a variable load at LVS does not have any cross regulation to high-voltage side port with the desired approximation. Magnificently, both merits are obtained in open-loop manner, which is an outstanding characteristic in comparison with that of the existed converters. In this paper, soft commutation and soft switching of switches and diodes are investigated along with the aforementioned main novelty. Moreover, detailed theoretical analyses of the proposed SIDO dc–dc converter in continuous conduction mode are presented besides the comparisons with some other structures. Finally, theoretical analyses are verified through a 1500 W experimental prototype results. [ABSTRACT FROM AUTHOR]

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn-on of part power switch and soft turn-off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a visible light communication (VLC) system consisting of a single-stage buck–boost power factor correction converter operating in the discontinuous conduction mode with dimming capability. Additionally, this paper proposes the on–off M-frequency shift keying modulation for the VLC system. This modulation allows for the transmission of more than a single bit for each switching period without affecting the dimming characteristics of the light-emitting diode luminaire. The design of the whole system is discussed in detail, including both transmitter and receiver modules. A 20-W laboratory prototype was built in order to verify the proposed modulation scheme. The experimental evaluation showed a good performance of the transmitter, which was able to perform simultaneously the desired functions, namely power factor correction, dimming, and data transmission. The receiver also achieved the desired performance with a low bit error rate (BER). The results showed that the proposed system was able to transfer data between emitter and receiver with a bit rate of 1.11 Mb/s at a frequency of up to 375 kHz over a distance of 10 m, and with a BER lower than $10^{-3}$ under the influence of external lighting sources with illuminance levels up to 500 lx. [ABSTRACT FROM AUTHOR]

The extra-LC auxiliary-resonant-snubber-based converter (ELCARSC), as a soft-switching converter, has the advantages of low switching loss, low electromagnetic interference noise, and low-output distortion caused by the dead-time effect. However, the dead-time effect is still the main problem in a high-precision application. Besides, the traditional control and compensation methods rely on the accuracy of the circuit parameters, especially the junction capacitance, thus resulting in compensation error. Therefore, this paper proposed a novel high-precision control method through modulating the initial resonant current to eliminate the dead-time effect of ELCARSC. The method does not need complicated online calculation and reduces the dependence on the accuracy of the circuit parameters, especially the influence of the junction capacitances of the switches. In this paper, the dead-time effect of the ELCARSC is analyzed. The output voltage error with the conventional variable-timing control method is analyzed. Subsequently, the proposed modulated initial resonant current control is introduced. Finally, a prototype was developed that verified the effectiveness of the control method. The quality of the output current and voltage is improved by utilizing the proposed control method. However, the peak current of the auxiliary switch is increased. [ABSTRACT FROM AUTHOR]

This paper presents a uniform control strategy for the bidirectional ac/dc interlinking converter (BIC) in hierarchical controlled hybrid microgrid. The uniform control strategy unifies different control structures for multifunctional BIC in terms of power management, ac and dc voltage support. With the unified control structure, various triggering mechanisms for BIC mode-switch are not compulsory in response to the relevant scenario changes in the power network. Therefore, the negative consequences, such as unsmooth transition and system collapse due to the inaccurate or slower mode switch, can be avoided. Moreover, the uniform control strategy is also applicable for the hierarchical controlled hybrid microgrid, whose control architecture is typically comprised of the centralized and decentralized levels. This enables the communication fault ride-through capability and the impact from the communication failures can thus be mitigated. To sum up the above two features, the proposed control strategy is able to provide a smooth operation for the BIC without control mode switch in the event of unintentional scenario changes in power or communication network. To verify the validity of the proposed uniform control strategy, the controller hardware-in-the-loop experimental results have been provided in this paper. [ABSTRACT FROM PUBLISHER]

The nine-switch converter is a multiport converter having two three-phase terminals and a dc-link, just like a 12-switch back-to-back (BTB) converter, but with 25% reduction of active switch count. However, the reduction from 12-switch to 9-switch may not always be an efficient choice considering losses in the switches. Only the load–source combination for the ac–ac common frequency mode and the source–source combination for the ac–dc different frequency (ac–dc DF) mode have been reported, so far, to yield relatively lower loss for the nine-switch converter. This paper shows that the nine-switch converter can have relatively lower loss even with a load–source combination, instead of only source–source combination in its ac–dc DF mode—when the upper terminal is connected to a dc load and the lower terminal is connected to an ac source. Mathematical proof is presented with derivation of the particular operating parameters for which the nine-switch converter will have comparatively lower losses. The analysis is validated with simulation and experimental results of a 1-kW system. Finally, the benchmark of the application criteria of the nine-switch converter for having lower conduction loss than the BTB converter is updated in this paper. [ABSTRACT FROM AUTHOR]

For power converters with inductive loads, a freewheeling path is needed for the current due to reactive power. The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Hence, an antiparallel SiC Schottky diode is normally implemented to eliminate its conduction. However, the external SiC Schottky diode is not fully utilized as it only works during the dead time. In this paper, the hard-switching SR is investigated in an SiC three-phase inverter and compared with a conventional inverter using freewheeling diode (FWD). An improved power loss model for the two inverters has been developed. It is found that the inverter using SR has higher efficiency due to the smaller switching loss. A 7-kW prototype of SiC three-phase inverter is built, which achieves a peak efficiency of 98.8% ($\pm$ 0.15%) and 98.5% ($\pm$ 0.15%) at 40 kHz using SR and FWD, respectively. This paper confirms that the SiC MOSFET is an ideal candidate for the SR. [ABSTRACT FROM PUBLISHER]

Thanks to the favorable advantage of low cost, integrated three-port dc–dc converters with reduced switches have attracted extensive attention. In order to provide more new topologies, this paper aims to propose a programmable topology derivation method, which effectively simplifies the cumbersome process of the conventional combination method. Instead of the manual connection and examination, the proposed alternative can quickly and rigorously derive multiple viable integrated three-port dc–dc topologies from a great number of possible connections with the aid of computer program. Besides, generalized analysis is also accomplished, with which performance characteristics of all derived converters are simultaneously obtained and then a comprehensive comparison can be easily conducted to select a preferred one for the practical application. Finally, an example-specific application with one input and two outputs is given, with topology selection, design, and experimental results demonstrated in detail. [ABSTRACT FROM AUTHOR]

Power converter is critical but prone to be failure in switched reluctance motor (SRM) drives. The open- and short-circuit fault characteristics of freewheeling diode in asymmetric bridge power converter are analyzed in details. Based on logic judgment, four online fault diagnostic methods with digital phase current analysis of power converter are proposed in this paper. The fault features are extracted by analyzing the relationship between chopping signal and the current information from some special positions. The four fault diagnostic methods are carried out according to the current obtained by detecting dc bus current and the lower freewheeling bus current, the chopped bus current, the upper excitation bus current and lower freewheeling bus current, the lower excitation bus current, and dc bus current, respectively. Comparisons between the four diagnostic methods are conducted. Simulations and experiments on a 12/8 SRM validate the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

This paper proposes two coupled-inductors-based Z-source networks, called the modified series and tapped switched-coupled-inductors quasi-Z-source networks (mSSCL-qZSN and mTSCL-qZSN, respectively). These networks offer high voltage gains with less-than-unity winding turn ratios $(n < {\text{1)}}$ , resulting in a reduced inductive element size. Other advantages include a less number of active components and their lower ratings and a higher efficiency. In addition, a lower magnetic core size is required for the proposed ZSNs due to the lower peak magnetizing current. The performance principles and detailed comparative analysis are provided and confirmed through experiments on a 200-W dc–dc converter. [ABSTRACT FROM AUTHOR]

In recent years, modular multilevel converter (MMC) is considered for medium-voltage variable speed drives (VSD) due to its modularity and higher reliability. However, the major drawback of the MMC-based VSD is the higher capacitor ripple voltage at lower operating speeds. In literature, this ripple voltage is reduced by injecting a high-frequency circulating current into each arm. This additional circulating current increases the overall current rating of the devices, inductors, and capacitors. Alternatively, the capacitor ripple voltage can be reduced at the lower output frequency by reducing the dc-bus voltage. This paper proposes a new configuration using a multipulse diode-bridge rectifier to reduce the dc-bus voltage when the drive is operated at lower speeds. Therefore, the capacitor ripple voltage decreases without injecting any circulating current. In addition, a new technique is proposed to maintain the peak-to-peak value of the submodule capacitor ripple voltage constant at near-zero speed. The proposed converter with 24-pulse rectifier configuration is simulated in MATLAB/Simulink, and the experimental validation is carried out on a prototype with 12-pulse rectifier. [ABSTRACT FROM AUTHOR]

The current-fed dual active bridge (CF-DAB) dc–dc converter gains growing applications in photovoltaic (PV) and energy storage systems due to its advantages, e.g., a wide input voltage range, a high step-up ratio, a low input current ripple, and a multiport interface capability. In addition, the direct input current controllability and extra control freedom of the CF-DAB converter make it possible to buffer the double-line-frequency energy in grid-interactive PV systems without using electrolytic capacitors in the dc link. Therefore, a PV system achieves high reliability and highly efficient maximum power point tracking. This paper studies the optimized operation of a CF-DAB converter for a PV application in order to improve the system efficiency. The operating principle and soft-switching conditions over the wide operating range are thoroughly analyzed with phase-shift control and duty-cycle control, and an optimized operating mode is proposed to achieve the minimum root-mean-square transformer current. The proposed operating mode can extend the soft-switching region and reduce the power loss, particularly under a heavy load and a high input voltage. Moreover, the efficiency can be further improved with a higher dc-link voltage. A 5-kW hardware prototype was built in the laboratory, and experimental results are provided for verification. This paper provides a design guideline for the CF-DAB converter applied to PV systems, as well as other applications with a wide input voltage variation. [ABSTRACT FROM PUBLISHER]

In this paper, a novel transformerless interleaved high step-down conversion ratio dc–dc converter with low switch voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive voltage division, the main objectives of the new voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses of active switches. As a result, the proposed converter topology possesses the low switch voltage stress characteristic. This will allow one to choose lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input voltage, 25-V output voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance. [ABSTRACT FROM PUBLISHER]

Direct current voltages unbalance of respective power cells is an inherent and critical problem in a cascaded multilevel converter, which is widely used in the solid-state transformer. In this paper, an n -dimension space vector pulse width modulation is presented to address this issue in a three-level H-bridge-based cascaded multilevel converter. This algorithm utilizes the redundant switching pairs of the inner cell and the redundant vectors of mutual cells to balance capacitors’ and cells’ voltages. Meanwhile, a smooth vector transition strategy is included in this algorithm to avoid the level-skip phenomenon. The calculation processes are analyzed in one-cell, two-cells, and three-cells modes, respectively. It is simple, calculable, and flexible to extend in n-cells mode. Finally, the voltage balancing capacity of the inner cell and mutual cells with smooth level transition are verified by simulations and experiments not only at startup but also with unbalanced loads. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology of 3-$\phi$ , multilevel inverter (MLI) configuration for five or higher level operation with reduced switch count. The proposed solution consists of two basic units (BUs) of multilevel converter and a T-structured 3-level inverter (3-LI). Both BUs are equally shared by the three phases maintaining symmetry among the phases. Moreover, for a higher level operation of the proposed MLI, the modifications required are at two BUs only and not at three legs of the inverter. It further helps in reducing the requirement of extra components for higher level operation compared to the conventional solutions. Furthermore, the topology also has the benefits of reduced switching and conduction loss. An algorithm is also devised to generate the switching pulses for the BUs and the 3-LI, using a carrier-based space vector modulation technique. Presented topology is compared with other existing topologies to prove its advantage. All the details regarding the operating modes and pulse width modulation techniques employed for the proposed system are given and supported by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

A modified scheme for reactive power compensation using static VAr compensators (SVCs) has been proposed in this paper for unbalanced four-wire system. The conventional SVC-based scheme requires both delta ( $\Delta $ $)$ - and star (Y)-connected SVCs for the same purpose. The proposed scheme uses a single-equivalent delta-connected thyristor controlled reactor (TCR) along with a combination of Y- and $\Delta $- connected thyristor switched capacitors for this purpose. The single-equivalent $\Delta $ -TCR in the present scheme is the result of a virtual Y-TCR and the conventional $\Delta $-TCR. This can reduces effective number of switching devices, cost, complexity, and space requirement compared to the conventional SVC-based schemes. Moreover, the proposed scheme can have various advantageous features compared to newly used DSTATCOM. The proposed scheme can also prevent injection of triplen harmonics in to the line, which is injected by Y-TCR in the conventional scheme. An optimized switching function is adopted in the proposed scheme for reduction of additional injected harmonics by TCR. The optimized switching angles are computed offline using gravitational search algorithm and stored in the processor memory for online application. The viability of the proposed scheme is simulated using MATLAB/Simulink and verified by suitable experimental results on a practical system. [ABSTRACT FROM AUTHOR]

Adding the auxiliary switches to the conventional H-bridge inverter is an effective way to eliminate the leakage current for transformerless PV systems, such as H5, H6, etc. Inspired by the newly developed embedded-switch H6 topology, a novel embedded-switch inverter (ESI) is proposed in this paper for three-phase transformerless PV systems. First, the operation principle and characteristics of the proposed ESI are analyzed. Second, the common-mode model of the three-phase ESI is established, based on which the main factors that affect the leakage current are discussed. The finding reveals that the switching states with conventional modulation strategy result in high-frequency common-mode voltage, which is the source of leakage current. In order to solve the problem, a new modulation strategy is presented for ESI to eliminate the high-frequency leakage current. Finally, the time-domain simulation and the experimental tests are carried out. The results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper proposes an interleaved-stage ac–dc bidirectional power converter topology feasible to medium-voltage railway systems. It is based on an arrangement that uses input-series-output-parallel configuration with identical power modules. Each module consists of two interleaved legs employing coupled windings so that it is possible to connect a medium-frequency transformer. The topology conception is presented, followed by the adopted control and modulation technique. An estimation of semiconductor losses is also discussed, while a comparative analysis by means of simulation results validates the improved performance of the introduced approach if compared with similar solutions. The topology results are obtainedt through a medium-voltage high-power railway application, demonstrating the converter functionalities and performance under both steady-state and dynamic conditions. It is then possible to state that good performance in terms of efficiency is achieved even though the power stage presents higher component count if compared with the topology that presents the best result, thus making it suitable to high-power ac–dc machine drive applications. [ABSTRACT FROM AUTHOR]

In this paper, dual-buck structured single-stage buck–boost inverters that use power MOSFETs to achieve high efficiency are presented. The proposed inverters require fewer switches, and half of the switches have reduced current stresses. They have no shoot-through problem; therefore, high system reliability can be obtained. The dead-time in PWM signals can be minimized or eliminated, which improving the quality of the output ac voltages and increasing the efficiency. In the proposed inverters, MOSFETs can be used without reverse-recovery issues of their body diodes to boost the efficiency and increase the switching frequency. To further improve the efficiency and stability of the proposed single-phase inverter, PWM strategies combining high- and low-frequency modulation are presented. A hardware prototype of the single-phase inverter was built and tested using resistive, inductive, and nonlinear loads. Experimental results for a 300-W prototype inverter show a 97.4% peak efficiency with a 25 kHz switching frequency. [ABSTRACT FROM AUTHOR]

The parallel three-phase grid-connected converters sharing dc and ac bus can increase the system power level effectively. However, the zero sequence circulating current (ZSCC) will occur inevitably under space vector pulse width modulation or discontinuous pulse width modulation (DPWM). In this paper, the mechanism and the mathematical model of ZSCC are studied. Then, a hybrid PWM (HPWM) strategy is proposed to suppress the ZSCC based on the same zero sequence voltage injected, which is dependent on the common grid information. The dc voltage utilization of HPWM can be extended compared with sinusoidal PWM (SPWM). The number of parallel modules can be infinity theoretically by using HPWM. It is noted that there is no internal commutation among modules (expect the dq current reference). Finally, the feasibility and the effectiveness of the proposed method are verified by experiments. [ABSTRACT FROM AUTHOR]

Several applications such as power supplies for electric precipitators, ozone generation, partial discharge, etc., require ac superimposed dc (ACsDC) voltage supply. Most of such applications use intransigent systems for producing ACsDC voltages. In this paper, three different kinds of flexible power electronic converters are proposed for producing ACsDC voltages. These converters have two power conversion stages: input and output. In the input stage, two isolated dc voltages are obtained by using an isolated three-port dc–dc converter or two isolated two-port dc–dc converters. In the output stage, one of the input-stage dc voltages is used to generate an ac voltage and the obtained ac voltage is added to the remaining input-stage dc voltage to obtain an ACsDC voltage. Based on the converters used in the input stage, the proposed ACsDC converters are named as a dual active bridge (DAB) converter-based ACsDC converter (DAB-ACsDC), triple port active bridge (TAB) converter-based ACsDC converter (TAB-ACsDC), and dual transformer-based asymmetrical triple port active bridge (DT-ATAB) converter-based ACsDC converter (DTATAB-ACsDC). A detailed analysis of these ACsDC converters and their verifications using simulations and experimental studies are presented, which depict that the proposed converters can be used effectively for producing ACsDC voltages. [ABSTRACT FROM AUTHOR]

This paper proposes an isolated single-ended primary-inductor converter (SEPIC) dc–dc converter with ripple-free input current and lossless snubber. The proposed converter is based on a conventional isolated SEPIC converter to enable electrical isolation and high voltage gain using a coupled inductor. The input current ripple is significantly reduced by utilizing an auxiliary circuit that also functions as a lossless snubber circuit with an additional diode. Moreover, the maximum switch voltage stress is clamped to a low voltage by the snubber circuit. Therefore, a low voltage rating mosfet that has low $R_{{\rm{DS(on)}}}$ can be utilized as a main switch device. Hence, the total power efficiency is improved. Experimental results from a 100 W prototype, which are presented to verify the theoretic analysis and performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

In this paper, a power factor correction (PFC)-based switched reluctance motor (SRM) drive is proposed. Generally, the SRM drive is fed with a simple diode bridge rectifier followed by a bulky capacitor, which draws peaky current at low power factor and high-input-current total harmonic distortion (THD). Here, a dual output converter is proposed to control the SRM and to provide power quality improvement as well. This converter is a combination of Cuk and SEPIC converters, which produces two equal output voltages with neutral point N, to feed a midpoint converter of the SRM drive. The converter is designed to operate in discontinuous conduction mode of operation to obtain inherent PFC at supply side. The motor control is attained by regulating dc link voltage over a wide range. Test results on a prototype of the SRM drive demonstrate the excellent performance with high power factor and reduced input current THD. The observed power quality indices depict the improved power quality as per the standard IEC 61000-3-2. [ABSTRACT FROM PUBLISHER]

This paper proposes a new \boldsymbol n -port hybrid dc circuit breaker for offshore multiterminal HVDC grid application. The \boldsymbol n-port dc circuit breaker can substitute \boldsymbol n-1 hybrid dc circuit breakers at a dc bus with \boldsymbol n-1 adjacent dc transmission lines. The system-level behavior of the proposed multiport hybrid dc circuit breaker is similar to other hybrid dc circuit breakers. The operation principles of the proposed multiport dc circuit breaker are introduced, analyzed, and compared to the existing solution in this work. The components ratings are compared to the existing solution, and the functionality of the proposed device is verified by simulation. [ABSTRACT FROM PUBLISHER]

In this paper, a new type of matrix converter (MC) also called a single-phase high-frequency transformer isolated (HFTI) buck MC is proposed. The proposed converter can provide step-down operation of the input voltage with various types of output voltages such as in-phase and out-of-phase output voltages, rectified (or positive) output voltage, and output voltage with step-changed frequency. By incorporating HFT isolation, the proposed MC saves an extra bulky line frequency transformer, which is required for the conventional MCs to provide electrical isolation and safety, when used in application such as dynamic voltage restorers, etc. Two different circuit variations of the proposed HFTI MC are presented with and without continuous output currents, with the latter having less passive components. The safe-commutation strategy is also employed for the proposed HFTI MC to provide current path for the inductor during dead-time, which avoids switch voltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed MC are presented, and switching strategies are also developed to obtain various output voltages. Moreover, a prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output voltages, and output voltage with step-changed frequency. [ABSTRACT FROM PUBLISHER]

This paper presents a new buck–boost converter. Unlike the single-switch buck–boost converter, the proposed converter has low-voltage stresses on semiconductors. Moreover, although both the conventional two-switch buck–boost (TSBB) and the proposed converters have the same number of passive and active components, and the proposed converter can reduce the conduction loss as a result of having fewer conducting components. Therefore, the proposed converter obtained a higher efficiency than the TSBB converter. A 48-V output voltage and 150-W output power prototype was fabricated to verify the effectiveness of the proposed converter. [ABSTRACT FROM PUBLISHER]

The impedance-source network converter, utilizing a unique LC network and previously forbidden shoot-through states, provides the ability to buck and boost the input voltage in a single stage. However, the inrush shoot-through current (STC) in startup or transient process might cause undesired current stresses on converter devices. This paper focuses on the STC sensing for an effective inrush current limitation by the combined current sensing technique in the quasi-Z-source inverter. STC and phase currents for the inverter control strategy are obtained simultaneously. No extra hardware is needed and the effects of current sensor bandwidth and duty cycle on the sensing accuracy are analyzed mathematically. The voltage spike gets avoided by integrating the stray inductance into the impedance network. Finally, an STC control loop based on proposed method are embedded in the field-oriented control strategy. The inrush STC and the device current stress in the transient process get suppressed. Simulation and experimental results from a quasi-Z-source inverter validate the feasibility of the proposed methods. [ABSTRACT FROM PUBLISHER]

In modern radio communications, the envelope of radio frequency (RF) signal features with large peak-to-average power ratio. This necessitates the adoption of linear power amplifiers (PAs). In order to achieve a high efficiency for linear PAs, envelope-tracking (ET) technique is employed, which provides PAs with a supply voltage that tracks the envelope of the transmitted RF signal instead of a constant voltage. This paper focuses on the series-form switch-linear hybrid ET power supply, where the switching-mode converter uses a multilevel converter. The method to select the setting voltages under the premise of ensuring the linearity of output voltage is presented. In addition, the values and number of the voltage levels of the multilevel converter are optimized using a precise loss model based on the probability density function of the envelope signal. Besides, the pulse-blank method is proposed to improve the system efficiency further. Finally, a prototype is built aiming for tracking the envelope signal of wideband code division multiple access, with 5-MHz bandwidth, 12–27 V output voltage, 4 W average, and 10 W peak output power. The experimental results show that the output voltage of the ET power supply tracks the reference accurately and the system efficiency can reach 76%. [ABSTRACT FROM PUBLISHER]

This paper presents a new formulation of a finite control set model-predictive control (FCS-MPC) algorithm, allowing to determine the best commutation instant in order to optimize the converter current tracking. This algorithm, mixing properties of FCS-MPC method and time resolution related to pulse width modulation schemes, is illustrated in a parallel flying capacitor converter. The parallel association of classical commutation cells is a good solution for increasing the output current driven by the converters, while the standard semiconductor technology is used. The control strategy used with this type of connection must be able to ensure not only a good distribution of the output current among the different legs, but also the balancing of the floating capacitor voltages. [ABSTRACT FROM PUBLISHER]

Phase-shifted carrier modulation is an industry standard in its application to multilevel H-bridge converters. The major advantage of this scheme over level-shifted and space vector modulation schemes is its inherent ability to evenly distribute losses between semiconductor devices. However, phase-shifted schemes suffer from harmonic degradation when operated at the low carrier frequencies required in high-power high-level number applications. This paper develops a model predictive modulation (MPM) scheme that achieves superior harmonic performance, compared to phase-shifted modulation, while ensuring equal semiconductor loss distribution. With respect to complete-enumeration-based predictive techniques, the proposed modulation significantly reduces the number of times the system cost function is evaluated. Reducing the number of calculations by several orders of magnitude ensures computational feasibility. Simulation and experimental results are presented, which confirm correct operation of the modulation strategy. [ABSTRACT FROM PUBLISHER]

Conventional matrix converters (MCs) have limited voltage gain that is less than 0.866, whether for direct MC (DMC) or indirect MC (IMC). Existing Z-source (ZS)/discontinuous quasi-Z-source (qZS) DMCs and ZS IMCs achieved larger than 0.866 voltage gain; however, the former inherited the complex commutation from DMC, and the latter involved a ZS network in dc link and led to non-all-silicon solution. In this paper, ZS and discontinuous qZS networks of existing ZS/qZS DMCs are used for an IMC topology for simplifying commutation and having high voltage gain, but they require extra input filter to reduce current harmonics. A new continuous qZS IMC is proposed, where a qZS network integrates the filtering function of the grid side; hence, additional input filter is avoided in the proposed continuous qZS IMC. Three new IMCs are compared in detail, in terms of voltage gain, current ripple, voltage ripple, inductor current and capacitor voltage stresses, ZS/qZS switch current and voltage stresses, filtering function, input current total harmonic distortion (THD), output voltage THD, and efficiency. Their control and modulation methods are presented to achieve the desired performances. Experimental comparisons verify the theoretical analysis and that the proposed continuous qZS IMC is a promising topology. [ABSTRACT FROM PUBLISHER]

Affected by the equivalent series resistance (ESR) of the devices in the circuit, the voltage-conversion ratio of traditional boost converter is limited. Various topologies have been developed to provide a high step-up voltage gain. An inherent high voltage gain can be achieved in a dual-switch converter with the advantages of low voltage and current stress on the switches. However, this converter has a strict requirement of the parameters' consistency. This paper discusses the steady-state operation principle of the converter in detail under the condition that the parameters are inconsistent and then illustrates the solutions to balance the voltage on the switches and suppress the resonance with passive lossless clamping. Finally, a prototype has been established in the laboratory, and simulation and experimental results have been given to verify the analysis and the effectiveness of clamping method. [ABSTRACT FROM PUBLISHER]

A variable on-time (VOT) control strategy for a critical conduction mode (CRM) flyback power factor correction (PFC) converter with low total harmonic distortion (THD) and high power factor (PF) is proposed in this paper. By using input voltage and the voltage across the auxiliary winding of the flyback transformer to modulate the turn-on time of the switch of the CRM flyback PFC converter, the PF and THD of the converter can be improved. The operation principles of the traditional constant on-time (COT)-controlled CRM flyback PFC converter and VOT-controlled CRM flyback PFC converter are analyzed. The experimental results show that the PF and THD of the VOT-controlled CRM flyback PFC converter are better than those of the COT-controlled CRM flyback PFC converter. [ABSTRACT FROM PUBLISHER]

In this paper, a dedicated pulse width modulation (PWM) technique specifically designed for single-phase (or four wire three-phase) multilevel Cascaded H-Bridge Converters is presented. The aim of the proposed technique is to minimize the DC-Link voltage unbalance, independently from the amplitude of the DC-Link voltage reference, and compensate the switching device voltage drops and on-state resistances. Such compensation can be used to achieve an increase in the waveform quality of the converter. This is particularly useful in high-power low supply voltage applications where a low switching frequency is used. The DC-Link voltage balancing capability of the method removes the requirement for additional control loops to actively balance the DC-Link voltage on each H-Bridge, simplifying the control structure. The proposed modulation technique has been validated through the use of simulation and extensive experimental testing to confirm its effectiveness. [ABSTRACT FROM PUBLISHER]

In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation. [ABSTRACT FROM PUBLISHER]