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This paper briefly reviews the common-mode voltage (CMV) and neutral point (NP) voltage for neutral point clamped three-level inverter (NPC TLI). Then, the space vector pulsewidth modulation (SVPWM) and traditional virtual SVPWM (VSVPWM) are discussed in terms of these two issues, revealing the drawbacks in reducing CMV or eliminating NP voltage oscillation. A novel virtual space vector modulation, named as RCMV_VSVPWM, is proposed in this paper to reduce CMV and eliminate NP voltage oscillation for NPC TLI. By selecting vectors with lower CMVs, a set of novel virtual voltage vectors are generated. The highlight of the method is zero average NP current in one control cycle and lower CMV. Furthermore, the active NP voltage control suitable for RCMV_VSVPWM is presented and evaluated. The corresponding experimental results are given, which are well-consistent with theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

This paper improves the position sensorless drive by sensing actual machine phase voltages. A high-bandwidth phase voltage measurement is developed for pulsewidth modulation (PWM) voltage inverters. On the basis, the actual phase voltage is obtained based on the digital integration of PWM voltage using the capture modulator in existing drive microcontrollers (MCU's). Comparing to existing phase voltage measurement, no separated A/D converter and communication hardware are required because PWM pulses are directly measured using MCUs. However, for standard machines without neutral points, only line-to-line ac PWM voltages can be measured for the phase voltage reconstruction. Since the capture based on transistor-transistor logic (TTL) logics receives only digital signals, a preprocess circuit to convert ac PWM line voltages to equivalent digital signals is proposed. This paper clearly explains the voltage sensing hardware using MCU capture modulator. According to experimental results, a 150-MHz sampling rate for phase voltage measurement is achieved based on the proposed capture-based voltage measurement. Although the physical limitation of back electromotive force estimation still appears, the proposed phase voltage measurement substantially enhances the sensorless drive performance at low speed. [ABSTRACT FROM AUTHOR]

Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]

In a sensorless vector control method, at low speeds and self-commissioning for AC motors, it is necessary to model dead time, rise/fall time, parasitic capacitors, and semiconductors’ voltage drop accurately. In this paper, voltage drop in each phase due to the nonlinear behavior of the inverter from the control system's viewpoint is precisely modeled by using two lookup tables. These lookup tables make the proposed model robust against the dc-link voltage and carrier frequency variations in the entire current range. In conventional methods at standstill, the measured voltage in the dc current test contains the nonlinearity of two phases. Therefore, to obtain the nonlinear voltage of each inverter phase, it is assumed that the values of inverter nonlinearity voltage at both high current and low current are equal. This simplification leads to distortion in measured voltage in the low currents. However, in this paper, the voltage drop equation of each phase is solved by numerical method that is realizable in conventional processors. The results obtained in actual voltage measurement show the superiority of the proposed method over traditional methods in the low currents. The proposed method is verified by using a voltage source inverter feeding a 2.2-kW three-phase induction motor. [ABSTRACT FROM AUTHOR]

Impedance source inverters have experienced a fast evolution since the first release of the Z-source inverter in 2003. This evolution is not limited to improving the structure of the different topologies but also includes their modulation and control schemes in order to reinforce their performance from many perspectives. Accordingly, many modulation schemes have been proposed in different research activities, but the full differences among these modulation schemes, including their effect on the switching losses, are not clear yet to the researchers. Hence, this research activity is aimed at introducing a comprehensive review of these different modulation schemes employed for the three-phase impedance source inverters, which is enhanced with a comparative assessment. In this paper, different modulation schemes are classified and reviewed, introducing an important benchmark in order to identify the basic differences between these modulation schemes. In other words, from this paper, the concept of classifying the different modulation schemes and the mandatory equations to implement each scheme can easily be drawn. Moreover, this review is essential for the next part, i.e., Part II, in which a comparative assessment is introduced. [ABSTRACT FROM PUBLISHER]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

High dc voltage utilization is one of the important requirements in a three-phase inverter. Under some carrier-based pulse width modulations (PWMs), the dc voltage utilization can reach the same maximum as that under the space vector modulation. But the third harmonic component of common-mode voltage (CMV) will be increased markedly while using these carrier-based PWMs in inverters. To improve the situation, this paper proposes that a midpoint-fluctuation carrier (MFC) scheme should be used in the three-phase inverter. The MFC is formed by adding a midpoint-fluctuation signal on the standard symmetrical triangular carrier. By analyzing the linear modulation region of the midpoint-fluctuation signals, a minimum fluctuant signal in the linear modulation region is designed in the paper. Compared with the use of other conventional schemes in the three-phase inverter, the use of minimum MFC scheme has higher fundamental amplitude in the output line voltage and smaller magnitude of the third harmonic in the CMV. The feasibility and validity of the MFC are proved by experiment results in a three-phase inverter. [ABSTRACT FROM PUBLISHER]

A novel hybrid pulse width modulation (PWM) technique is proposed in this paper for two parallel interleaved, two-level, three-phase voltage source inverters (VSIs). The two parallel interleaved VSIs are analyzed as a three-level (3L) inverter. A 3L inverter provides minimum line current ripple when nearest three voltage vectors are applied. In this paper, a novel carrier-based PWM technique is developed that ensures the application of nearest voltage vectors, keeping average circulating current to zero over a switching period. For carrier-based implementation of the proposed PWM, generalized common-mode (CM) offsets are derived in terms of maximum and minimum values of reference signals. Each 3L space-vector sector is divided into seven subsectors. For each subsector, a CM offset is calculated, addition of which to reference signals ensures the minimum line current ripple and zero average circulating current. Simulation and experimental results are provided to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

The advancement in modulation strategies brings emergent solutions to suppress the leakage current in three-phase two-level transformerless grid-connected voltage source inverters (VSIs). However, most of the techniques are analyzed based on reduced common-mode voltage pulsewidth modulation (PWM) in motor drivers but fail to satisfy the specific requirement of grid-connected applications, such as wider power factor operation and lesser current distortion. To overcome such substantial drawbacks, this paper proposes a novel scalar PWM method for transformerless grid-connected VSIs. First, presented through a generalized scalar approach with unified zero-sequence voltage generation, the method is simple to implement and favored in practice. Besides, systematic and comprehensive mathematical analysis is illustrated to exhibit the validity of implemented method in reducing leakage current and shows its advantages over whole power factor range in terms of dc-link current harmonic, output current quality, and switching losses. Finally, simulations and experimental results are carried out to verify the effectiveness and superiority of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes the use of advanced bus clamping switching sequences to reduce the impedance network inductor current ripple of the three-phase Z-source inverter (ZSI). Proposed technique is named as ABC4_MCB. MCB denotes that the maximum constant boost control method is used for the voltage boosting. One of the conventional space vector pulsewidth modulation of ZSI, “ZSVM6,” is termed as ZSVM6_MCB under the maximum constant boost control method. The switching sequences of ABC4_MCB technique are designed in such a way that it offers around 34% reduction in the maximum instantaneous inductor current ripple as compared to the ZSVM6_MCB for the equal average switching frequency. The factor of percentage reduction in the inductor current ripple using the proposed technique is constant over the entire range of shoot through duty ratio (0–0.48). Theoretical findings have been verified using simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]

The control delay weakens the active damping (AD) performance of digitally controlled LCL/LLCL-type grid-connected inverters (GCIs). The equivalent virtual impedance paralleled with the filter branch explains the effect of the capacitor-current-feedback AD. However, the virtual impedance appears capacitive or even negative due to the delay, which significantly weakens the effectiveness of AD. This paper proposes a single-cycle-lag compensator (SCLC) to eliminate the adverse effects caused by the control delay. The method retains effectiveness in applications with high resonant frequency or large control delay. It keeps system a positive equivalent resistance with a high equivalent inductance. The positive equivalent resistance leads to positive damping effect, while the high equivalent inductance causing little resonant frequency deviation can be neglected. Moreover, the effect of the impedance variation that causes the resonant frequency deviation is analyzed and the restrictions of the proposed method are discussed. By optimizing the LCL/LLCL filter parameters, the adaptability of the SCLC to the grid impedance variation can be further improved. With the SCLC, the LCL/LLCL-type GCIs achieve better steady-state and dynamic performances. Finally, experimental results are presented to verify the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents an investigation on finite control set model predictive current control, validated experimentally with a rear axle electrical drive unit used in automotive applications. An improved problem formulation is suggested which lowers the computational turnaround time of the solver with approximately $\text{40}\%$ for an horizon length of $N=4$. Apart from the computational requirement aspects, the assessment focuses on inverter efficiency, phase current total demand distortion, and acoustic performance. The proposed solution is evaluated against a standard double proportional and integrator (PI) field-oriented current controller with pulsewidth modulation. It is shown that the proposed solution is feasible, the associated optimization problem at hand can be solved in real time, while exploiting the attractiveness of the proposed improvements. In summary, it is concluded that the inverter efficiency can be improved without deteriorating neither the phase current harmonics nor the acoustic performance. [ABSTRACT FROM AUTHOR]

A multilevel drive can be realized by using an open-ended machine, fed from dual two-level inverters. The topology supplied from isolated dc sources is suitable for transportation electrification. In vehicular systems, it is essential that the isolated dc sources, comprising of battery packs, should discharge uniformly and maintain balanced dc voltage at the dc-link terminal. A simple carrier-based pulsewidth modulation (PWM) technique is presented in this paper, which can effectively regulate the power drawn between the two two-level inverters while maintaining the multilevel operation of the drive. The modulation technique can balance the instantaneous state of charge of independent battery packs and dynamically equalize the power flow from the two inverters, based on drive requirement. This will enhance the reliability of the propulsion system in electric vehicles. The operation of the proposed PWM technique has been validated through detailed simulation and experimental tests. [ABSTRACT FROM AUTHOR]

This paper proposes an explicit predictive current control scheme implemented with a low carrier frequency pulsewidth modulation (PWM) on an induction machine fed by a three-level neutral point clamped inverter. The PWM carrier and the main current sampling frequency are both set to 1 kHz, resulting in a 500 Hz average switching frequency per device, which is very suitable for large drive applications. The explicit predictive control is introduced to optimize the available bandwidth provided by such a low sampling frequency, maximizing the dynamic performance. The strategy has been tested in a 2.2-kW induction motor experimental prototype. [ABSTRACT FROM AUTHOR]

Three-phase pulsewidth modulation inverter fed induction motor drive system is widely applied in high power drive applications. Sensor faults are very common in the drive system, which, once occur, might result in degraded system performance or even system shutdown. In order to rapidly and accurately diagnose the sensor faults, this paper proposes an intelligent time-adaptive data-driven method to identify the fault location and fault type of sensors in the drive system. An emerging machine learning technology named extreme learning machine (ELM) is applied to learn the sensor fault dataset; an ensemble ELM classifier is then designed to improve diagnostic accuracy, based on which a time-adaptive fault diagnosis process is proposed to achieve a high and balanced diagnostic accuracy and speed. As a data-driven method, the proposed method only employs the phase current, dc-link voltage, and speed signals as the inputs to the ensemble ELM classifiers and requires no additional sensors and other hardware. Simulated and experimental tests show that the proposed method can rapidly and accurately detect the fault sensor location and identify offset fault, stuck fault, and noise faults with an average diagnostic accuracy of 98% and the average decision time of 10 ms after the fault occurs. Moreover, such diagnosis method is robust to the fluctuation of catenary voltage and dc-link voltage, fault severity, and variation of model parameters, speed, and load. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

In this paper, a generalized switching modification method is proposed to reduce the root-mean-square (rms) current flowing into a dc-link capacitor in a dc–dc–ac structure consisting of a boost converter and a three-phase inverter. To analyze the current flowing into the capacitor, we analyze the currents at the respective converter and inverter sides. Based on this analysis, we derive an analytical method to find the modification time between the converter and inverter pulsewidth modulation (PWM) carriers through a Fourier series and approximation to facilitate real-time implementation. Real-time implementation of the modification time calculated by the derived method is described. To verify the validity of the proposed method, experimental results are presented based on a 1-kVA dc–dc–ac prototype. The proposed method has a better capacitor rms current reduction performance than the conventional method in various inverter power factors and PWM strategies. Especially, it has an excellent performance in mid-power factor level (0.95–0.1). [ABSTRACT FROM AUTHOR]

This paper provides robust $\mathcal {H}_{\infty }$ state feedback controllers suitable for implementation in three-phase grid-connected converters. This control strategy is known to provide optimal rejection of disturbances, but usually leads to high control gains, that may be difficult to be implemented in practice. To mitigate this problem, a linear matrix inequality condition based on slack variables is proposed, which allows to impose bounds on the control gains in a less conservative way than conventional quadratic stability. The performance is proven to be superior to similar $\mathcal {H}_{\infty }$ state feedback controllers in the literature, providing an upper bound for the converter output admittance and experimental grid currents complying with the IEEE Standard 1547. [ABSTRACT FROM AUTHOR]

In domestic induction heating applications, the modulation technique applied to the inverter has a high influence on the acoustic noise emissions. These noise emissions must be avoided, since they may be audible and annoying to the final user. This paper analyzes the acoustic noise emissions that appear when a series half-bridge resonant inverter is operated with a phase-accumulator-based modulator. This modulation technique has the advantage of operating in the frequency domain, and it is compared with the classical pulsewidth modulator regarding the audible noise generated. The frequencies of the tones in the acoustic noise spectrum are theoretically calculated from the parameters of the phase-accumulator-based modulator. The spectral flatness measure is used to quantify the number of cases in which tones are generated by the modulation. Two techniques are applied to the phase-accumulator-based modulator, and their effect is tested. Theoretical results are experimentally verified. [ABSTRACT FROM AUTHOR]

Repetitive control strategies have been commonly applied in pulse-width-modulated (PWM) voltage source inverters (VSIs) for many industrial applications. This paper presents a repetitive controller for voltage harmonic mitigation of VSI-based islanded microgrids. The phase delay in the overall control system, e.g., the delay caused by the digital duty cycle calculation, PWM generation, and repetitive controller, has to be compensated by elaborately designed phase lead filters in order to prevent control performance deterioration and system instability. Nevertheless, quantificational analysis and practical design of the time advance unit in such filters are hardly found in existing literature works. In view of this, this paper proposes an explicit analysis of the phase lead filters and a novel design method of the time advance unit in repetitive controllers to ensure system stability. Moreover, with the help of the proposed method, the overall system stability margin is predictable and improved controller performance is achieved as well. The proposed method is implemented experimentally to show the accurate stability margin calculation as well as the excellent steady state and dynamic performances of the repetitive control scheme. [ABSTRACT FROM PUBLISHER]

Two three-level inverters driving an open-end winding induction motor can generate equivalent voltage waveforms as a single five-level inverter-based drive. In addition, it can bring in benefits such as reduced dc-link voltage, less number of devices, and fault-tolerant capability, which is favored in high-power motor drive applications. The main challenge with this type of configuration is the appearance of large zero-sequence current circulating between the two inverters, which generates extra losses in the switching devices and the motor as well as affects the normal operation of the machine. Another challenge is to balance the dc-link neutral point voltage of the two three-level inverters. This paper has proposed a simplified decoupled space-vector pulsewidth-modulation (PWM) strategy to eliminate the averaged zero-sequence voltage in each switching cycle by the placement of redundant vectors of each individual inverter using a time shift. Neutral point voltage balance is further achieved by adjusting the time duration of the redundant vectors. In this paper, it is shown that it is possible to operate this kind of drive configuration with a single dc power supply and achieve averaged zero-sequence voltage elimination and neutral-point voltage balancing at the same time. Experimental results of a 5.5-kW dual three-level inverter drive using the proposed PWM strategy are presented, which validates the control method and drive configuration. [ABSTRACT FROM PUBLISHER]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

To reduce the common-mode voltage (CMV) and eliminate the CMV spikes for two-level voltage source inverters (2L-VSIs), an improved model predictive control (MPC) based CMV reduction method is proposed in this paper considering dead-time effects. First, an improved voltage vector (VV) preselection strategy is proposed to reduce the CMV spikes caused by the dead time. Second, a new hybrid VV preselection strategy based on a delay compensation strategy and a modified current sector division strategy is proposed to completely eliminate the CMV spikes. As the proposed hybrid VV preselection based MPC strategy makes full use of the six nonzero VVs of the 2L-VSI, the current total harmonic distortions and ripples are reduced. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Multilevel inverters are now-a-days being applied in electric vehicles (EV). Considering the dynamic operating conditions of an EV propelled by an induction motor, this paper proposes a flexible discontinuous modulation strategy for three-level neutral-point-clamped (NPC) inverter that can shift modulation pattern seamlessly from sinusoidal pulsewidth modulation (SPWM) to discontinuous PWM (DPWM). The modulation scheme is generalized at each degree of discontinuity to ensure minimum switching losses for variable load power factors. Additionally, a hybrid voltage balancing strategy, which comprises two sets of compensating offset signals with complementary features, has been introduced to mitigate voltage deviation problem at neutral point of the inverter. The unique feature of the proposed hybrid balancing approach is that it generates uniform compensating neutral current regardless of the level of discontinuity. This results in identical and predictable voltage balancing dynamics for the entire modulation transition covering SPWM and DPWM. It has been shown that the proposed hybrid balancing strategy does not lose its unbalance compensation strength even during transition from one modulation pattern to another. The effectiveness of the proposed scheme for wide variations in operating conditions is studied through extensive simulation, and validated in experimentation using a prototype NPC inverter with induction motor loads. [ABSTRACT FROM AUTHOR]

Variable frequency asymmetrical pulsewidth modulation (VFAPWM) is widely used in wireless power transfer (WPT) systems to control the amount of power transferred. This control scheme is also adopted in Qi, one of the world's most well-known wireless charging standards. Conventionally, the analysis of WPT systems is based on first harmonic approximation, which only considers the fundamental harmonic signals. This could be inaccurate for variable frequency asymmetrical pulsewidth-modulated WPT systems because VFAPWM inherently produces multiple harmonics. In this paper, a new analytical technique, called multiple harmonics analysis (MHA), is developed to analyze series–series-compensated WPT systems. The MHA technique is a comprehensive design foundation and provides a set of closed-form solutions to predict quantities, such as zero-voltage switching (ZVS) and voltage gain. New phenomena in ZVS and voltage gain are discovered. The accuracy of MHA is also confirmed by both simulation and experimental measurements. [ABSTRACT FROM AUTHOR]

In this paper, a novel integrated interleaved dual-mode time-sharing inverter (IIDMI) is proposed for grid-tied transformerless photovoltaic (PV) applications. While the dual-mode time-sharing conversion technique ensures minimum losses, the IIDMI also retains the advantages of interleaved topologies, such as low total harmonic distortion of the ac current with reduced filtering requirements, increased power density, and reduced current and thermal stresses of power devices. The leakage current problem, which is a main concern with the transformerless PV inverters, is solved by increasing the frequency of the main side band of the common-mode voltage above the resonance frequency of the common-mode impedance, while avoiding high switching losses. The current control, especially at transitions between the buck and the boost modes of operation, is highly improved by utilizing a fast-response deadbeat control scheme. The working principles of the IIDMI are explained in detail, and a 2.2-kW experimental prototype is implemented to confirm the theoretical achievements. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless line-interactive uninterruptible power supply (UPS) with low ground leakage current. A high-efficiency bidirectional inverter is suggested, which performs the line-interactive UPS functions with low ground leakage current. It has a full-bridge inverter and a bidirectional switch, which operate with the unipolar pulsewidth modulation. Because the bidirectional switch operates at the line-frequency, switching losses can be lower than the previous transformerless inverters. As the inverter operates, the parasitic capacitance between the inverter and the ac voltage ground is clamped to zero voltage for a positive line cycle and to the ac voltage for a negative line cycle, respectively. Thus, the parasitic capacitance can be prevented from being charged or discharged, which ensures the absence of the ground leakage current. The operation modes of the proposed system are described. The control schemes are presented to design the proposed inverter for the line-interactive UPS. Experimental results for a 2.0 kW prototype are discussed to verify the performance of the proposed system. [ABSTRACT FROM AUTHOR]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-sequence circulating current (ZSCC) control scheme for the multiparalleled three-level T-type inverters (3LT2Is). Based on the analysis with the proposed generalized model of multiparalleled 3LT2Is, it is seen that the ZSCC is influenced by the circuit parameters, duty cycles, and the circulating currents of the l th and first 3LT2I. To mitigate the circulating currents, a deadbeat control strategy for n-paralleled (n≥3) inverters is proposed, which is realized by adjusting the duty cycle of the small vectors in each PWM sampling period. Compared with the conventional PI control method, the ZSCC spike is mitigated with the proposed scheme, thus improving the quality of the output currents. Also, the reliability of the 3LT2Is system is improved because such a scheme only needs the information about the ZSCC and zero-sequence duty ratio in the l th and the first inverter. The proposed method can also be applied to the neutral-point-clamped converters. Simulation and experimental results verify the effectiveness of the theoretical analysis and the proposed method. [ABSTRACT FROM PUBLISHER]

This paper characterizes the sampling effect in digital sinusoidal pulse width modulation (SPWM) of voltage source inverter (VSI). The time-domain analysis presented in this paper establishes the relation between the fundamental frequency, carrier frequency, and the sampling frequency at different modulation indices of the SPWM. The analysis investigates the effect of sampling frequency of the digital controller on the output of the VSI. It is shown that the low-frequency harmonic components appear in the frequency spectrum of the VSI output voltage due to sampling. As a result, the output current of digitally controlled VSI is stepped in nature. The double Fourier integral solution of the switched waveform for inner and outer integral limits has been used to derive the expression. The integral solution is obtained using Jacobi-Anger expansions. The generalized results developed in this paper are useful to investigate the sampling effect in high switching frequency DSPWM. The proposed sampling effect has been analyzed for SPWM of single-phase H-bridge inverter. The analytical results are verified using simulation and experimental results. The experimental results have been obtained with the use of field-programmable gate array (FPGA) as a digital controller. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency—making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

In this paper, a single-stage solution for solar photovoltaic (PV) pumping system using a dual-inverter fed open-end winding induction motor drive is presented. The three-level dual-inverter requires a low PV bus voltage compared with its conventional three-level counterpart. This could avoid large string of PV modules and helps in reducing the voltage rating of the capacitors and semiconductor devices used in the system. This may further help in reduction of cost of the system. The proposed single-stage system is operated using an integrated control algorithm, which includes the maximum power point tracking (MPPT), the $V/f$ control, and the sample-averaged zero-sequence elimination (SAZE) pulsewidth modulation (PWM) technique. While the MPPT algorithm ensures the extraction of maximum power from the PV source, the $V/f$ control improves the motor pump performance. Furthermore, the zero-sequence current is avoided by the SAZE PWM algorithm. Thus, the integrated control algorithm improves the overall performance of the system. Furthermore, this paper also presents the details of system design and analysis of its dynamic behavior during transient environmental conditions. The performance of the system is verified using MATLAB simulation and hardware prototype. [ABSTRACT FROM PUBLISHER]

A four-level five-phase open-end winding (OeW) drive topology is introduced in this paper. The drive comprises a five-phase induction machine with open-end stator windings, supplied using two two-level voltage-source inverters with isolated and unequal dc-link voltages, in the ratio 2 : 1. The topology offers the advantages of a modular structure with fewer semiconductor components and has a greater potential for fault tolerance, as compared with an equivalent single-sided four-level drive. Due to the large number of switching states, development of a suitable space vector pulsewidth-modulation (PWM) method can be challenging. Hence, this paper examines the implementation of two-level-shifted carrier-based PWM methods. The effect of dead time on the drive performance is discussed, and it is shown that simultaneous PWM switching of both inverters can lead to degraded output phase voltage waveforms. Detailed analysis of this phenomenon is presented, a solution is proposed, and the modified modulation techniques are incorporated in an experimental setup, at first in conjunction with $V/f$ control. Once the proof of concept has been provided, full field-oriented control is implemented in this OeW drive topology for the first time; detailed experimental testing is conducted, and results are reported. [ABSTRACT FROM AUTHOR]

Multiphase variable-speed drives and generation systems (systems with more than three phases) have become one of the mainstream research areas during the last decade. The main driving forces are the specific applications, predominantly related to the green agenda, such as electric and hybrid electric vehicles (EVs), locomotive traction, ship propulsion, “more-electric” aircraft, remote offshore wind farms for electric energy generation, and general high-power industrial applications. As a result, produced body of significant work is substantial, making it impossible to review all the major developments in a single paper. This paper therefore surveys the recent progress in two specific areas associated with multiphase systems, namely power electronic supply control and innovative ways of using the additional degrees of freedom in multiphase machines for various nontraditional purposes. [ABSTRACT FROM AUTHOR]

This paper shows how the problem of estimating the initial rotor position in permanent-magnet sensorless drives can benefit from the availability of a direct measurement of motor phase voltages. Two different estimation methods are presented for this purpose. The first is a readjustment of a classic procedure based on the detection, by means of the injection of voltage test pulses, of inductance variations due to motor saliencies, from which it is then possible to infer the position of the rotor. Since the application of irregular test pulses may increase the estimation uncertainties, the available voltage measurement is exploited to implement a closed-loop amplitude control of the test pulses. The second method is introduced both to overcome an issue related to the digital measurement approach adopted in this paper and to allow position estimation even in a motor with no relevant saliency, a case for which the first method is inappropriate. The effectiveness of the proposed solutions is validated by several experimental tests, which are carried out on two motors with different saliency properties. [ABSTRACT FROM PUBLISHER]

This paper proposes a new method of dead-time effect compensation. The proposed solution is based on additional phase current measurements realized by analog-to-digital converters. These measurements are carried out at the time instants specified by a pulsewidth-modulation (PWM) strategy. This makes it possible to estimate inverter currents at the commutation instants and, finally, to estimate the voltage error caused by dead time. This voltage error is compensated during the next switching period by modification of a reference voltage. The proposed solution can be used to compensate the voltage error in multilevel multiphase voltage source inverters. The experimental research studies were carried out on three-phase two-level and three-level neutral-point-clamped inverters supplying 55- and 160-kW motors, respectively. The results of the experimental investigations are presented in this paper. [ABSTRACT FROM PUBLISHER]

Exploiting the rich switching redundancies of the dual inverter, new hybrid pulsewidth-modulation (PWM) switching methods are proposed in this paper using the degree of freedom of operating the individual inverters independently, in addition to exercising the degree of freedom of controlling the switching action of the individual legs independently. Two voltage entities, namely, common-mode voltage (CMV) and differential-mode voltage are identified in the dual inverter, and all hybrid PWMs are envisaged aimed at reducing and also eliminating the CMV in it. The effects of such attempts on motor shaft voltage and also the motor bearing currents are presented in detail. Furthermore, bearing current profiles of an open-end winding induction motor are also presented with both conventional and hybrid PWMs proposed in this paper. Electric discharge machining discharge currents are completely eliminated with the use of all hybrid PWM methods proposed in this paper. In addition, implications of completely eliminating the CMV are also presented in this paper. All hybrid PWMs proposed in this paper are first simulated using MATLAB and are experimentally verified on a dual two-level inverter feeding a 1.1-kW 415-V 3- $\phi$ open-end winding induction motor drive. [ABSTRACT FROM PUBLISHER]

A multilevel inverter topology for a four-pole induction-motor drive is presented in this paper, which is constructed using the induction-motor stator winding arrangement. A single dc source with a less magnitude when compared with conventional five-level inverter topologies is used in this topology. Therefore, power balancing issues (which are major challenges in conventional multilevel inverters) are minimized. As this configuration uses a single dc source, it provides a path for zero-sequence currents because of the zero-sequence voltages present in the output, which will flow through the motor phase winding and power electronic switches. To minimize these zero-sequence currents, sine–triangle pulsewidth modulation (SPWM) is used, which will shift the lower order harmonics near to switching frequency in the linear modulation region. However, in the case of overmodulation, harmonic voltages will be introduced close to the fundamental frequency. In this regard, a modified SPWM technique is proposed in this paper to operate the drive in the overmodulation region up to the modulation index of 2/\!\surd3. The proposed quad two-level inverter topology is experimentally verified with a laboratory prototype on a four-pole 5-hp induction motor. Experimental results show the effectiveness of the proposed topology in the complete linear modulation region and the overmodulation region. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

In this paper, a real-time implementation of selective harmonic elimination pulsewidth modulation (SHEPWM) using generalized Hopfield neural network (GHNN) as applied to the single-phase inverter is designed and discussed. Finding the location of the switching instants in the case of SHEPWM involves the solution of a set of nonlinear algebraic transcendental equations. The problem is redrafted as an optimization problem, and it is solved by using GHNN. Though, in principle, the $n$ number of harmonics can be eliminated using the presented methodology, this paper tries for the case of the elimination of the 5th-, 7th-, 11th-, and 13th-order harmonics while retaining the desired fundamental. An energy function is formulated for this problem and the set of ordinary differential equations (ODEs) describing the behavior of GHNN is obtained. A program in KEIL C was developed to solve these systems of ODEs by the Runge–Kutta fourth-order method to give the switching instants for continuously varying modulation indexes $(M)$. A MATLAB simulation was carried out, and an experimental setup was also constructed in order to validate the simulated results. The fast Fourier transform analysis of the simulated output voltage waveform and the experimental output voltage waveform confirms the effectiveness of the proposed method. Hence, the proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real-time applications. [ABSTRACT FROM PUBLISHER]

A two-motor drive, supplied by a five-leg inverter, is considered in this paper. The independent control of machines with full dc-bus voltage utilization is typically achieved using an existing pulsewidth modulation (PWM) technique in conjunction with field-oriented control, based on PI current control. However, model predictive control (MPC), based on a finite number of control inputs [finite-control-set MPC (FCS-MPC)], does not utilize a pulsewidth modulator. This paper introduces three FCS-MPC schemes for synchronous current control in this drive system. The first scheme uses all of the available switching states. The second and third schemes are aimed at reducing the computational burden and utilize a reduced set of voltage vectors and a duty ratio partitioning principle, respectively. Steady-state and transient performances are analyzed and compared both against each other and with respect to the field-oriented control based on PI controllers and PWM. All analyses are experimental and use the same experimental rig and test conditions. Comparison of the predictive schemes leads to the conclusion that the first two schemes have the fastest transient response. The third scheme has a much smaller current ripple while achieving perfect control decoupling between the machines and is of low computational complexity. Nevertheless, at approximately the same switching loss, the PI-PWM control yields the lowest current ripple but with slower electrical transient response. [ABSTRACT FROM PUBLISHER]

This paper presents a comparison of two modulation methods for the seven-level switched-capacitor (SC) inverter using series/parallel conversion (SCISPC). The SCISPC is a multilevel inverter which has the less number of switching devices than the conventional multilevel inverters. The level-shifted pulsewidth modulation (PWM) (LS-PWM) was applied to the seven-level SCISPC in the previous research. In this paper, the level- and phase-shifted PWM (LPS-PWM) and the LS-PWM are applied to the seven-level SCISPC, and LPS-PWM is compared with LS-PWM for the seven-level SCISPC. The LPS-PWM has both the characteristics of the phase-shifted PWM (PS-PWM) and the LS-PWM. The voltage reduction during the discharging term of the SCs is reduced by means of the shorter discharging period compared to LS-PWM. The voltage ripple of the capacitors is also reduced, which leads to higher power conversion efficiency. The difference of the two modulation methods is confirmed by the theoretical approach, simulation with PSIM, and circuit experiment. [ABSTRACT FROM PUBLISHER]

In constant-voltage constant-frequency (CVCF) pulsewidth modulation (PWM) dc–ac inverters, the lumped disturbance, including the parameter uncertainties, unmodeled dynamics, and nonlinear loads, will deteriorate the performance and cause high harmonic distortions, or even result in instability. Conventional disturbance observer (CDOB), in which a low-pass $Q$ filter is adopted to estimate the lumped disturbance, cannot completely eliminate the harmonics. While the conventional repetitive control (CRC) can attenuate the harmonics by using the error signal of previous period(s), that may result in slow transient response due to nonperiodic components in the tracking error during the transient state. In this paper, an internal model-based disturbance observer (IM-DOB) is proposed and has been applied in a CVCF PWM inverter to improve the control performance. In IM-DOB, a novel IM-based disturbance estimation observer is proposed to estimate the disturbance both in the low-frequency region and at harmonic frequencies, while compensation filters are introduced to enhance the robustness and stability. The IM-DOB scheme, which fuses the merit of CDOB and CRC, is actually a two-degree-of-freedom scheme. The stability analysis and a design case are also given. Comparative experiments are conducted to demonstrate the effectiveness of the proposed scheme. [ABSTRACT FROM PUBLISHER]

Impedance network inverters are the best alternatives for voltage-source and current-source inverters. The boosting capability and the shoot-through solution of such converters make them excellent solutions for various applications. Nevertheless, hard switching forces the converter to operate in low switching frequency, which results in a bulky impedance network. Moreover, the coupling between the shoot-through duty cycle and the inverter modulation index makes a tradeoff between the voltage gain and the modulation index (output voltage harmonics). This paper presents a novel dual switching frequency modulation to mitigate the switching losses of the converter, which results in a more compact impedance network. The proposed method combines a high-frequency pulse width modulation with a low-frequency sinusoidal pulse width modulation (SPWM). Therefore, the switching losses decrease considerably with respect to the conventional simple boost modulation. In addition, the impedance network design frequency remains high, and the network size decreases obviously. The proposed approach removes the interdependence between the shoot-through duty cycle and the inverter modulation index. A comparison between the proposed method and the conventional simple boost method is performed to show its advantages over the conventional method. Finally, experimental results are presented to validate the performance of the proposed method. [ABSTRACT FROM PUBLISHER]

In trasformerless grid-connected photovoltaic (PV) systems, common-mode voltage (CMV) fluctuations cause leakage current flow through the stray capacitance of the PV panels. Shoot-through states in a quasi-Z-source inverter (q-ZSI) increase the amplitude of high-order harmonics of CMV. In this paper, by using the modulation technique based on odd pulse width modulation and minor change in the Z network of the three-phase q-ZSI, the leakage current is blocked. No extra semiconductor element is added. By the proposed technique, CMV is kept nearly constant during switching cycles. The experimental results for CMV analysis in a \text1\;\textkW prototype are presented to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

Multilevel inverters (MLIs) have replaced conventional two-level inverters for medium-voltage high-power industrial applications. One of the best modulation techniques for MLIs is the space vector modulation (SVM). Although SVM has its own advantages, it has been overlooked for much simpler carrier-based modulation schemes in the industry. Nearest level modulation (NLM) is a simple alternative, which is functionally similar to SVM. In this paper, a new generalized SVM algorithm is presented, in which the SVM is achieved using the concept of NLM. A generalized switch matrix is introduced to derive gate pulses for the inverter, which further simplifies the algorithm. The algorithm is tested and verified for a three-phase, three-level, and five-level neutral-point-clamped inverters in both simulation and hardware. [ABSTRACT FROM PUBLISHER]