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A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

This paper develops a modulation based fault-tolerant (FT) strategy for restoring the operation of three-phase modular multilevel converters (MMCs) with faulty switches. This FT strategy is based on a proposed modified space vector modulation (SVM) technique that generates balanced line-to-line (line) voltages even in the case of a fault occurrence. In the postfault operation, the proposed strategy is able to restore the fundamental amplitude of the line to the neutral (load) voltages to that of the normal operation condition with a slightly increased voltage stress over the switches in the faulty phase. In this paper, first a brief background about MMCs and SVM technique is provided. Then, the proposed FT strategy and the modified SVM technique are presented. Finally, several simulation and experimental results are provided to validate operation of the proposed strategy. [ABSTRACT FROM AUTHOR]

Standard pulsewidth modulation (PWM) schemes for modular multilevel converters (MMC) have neglected deviations of the module voltages from the mean module voltage of an MMC arm as well as the dynamic change in the module voltages since their last measurement and during the switching period. This induces an output voltage error. Large output voltage errors disturb the higher level closed-loop control of the MMC, such that control targets cannot be met anymore. The output voltage error can be reduced using advanced PWM methods that predict and include the dynamic change of the individual module voltages during a switching period in the calculations for the duty cycle. This paper shows measurement results obtained from an experimental medium-voltage prototype, proving that advanced methods lead to much lower output voltage errors than the standard methods, but cannot fulfill the expectations raised by the simulations documented in the literature. In order to overcome the limitations of the old method, a new method that includes the semiconductor voltage drop and parasitic resistances is introduced and evaluated with measurements in this paper. Furthermore, simulation results showing the influence of the considered modulation methods on the closed-loop current control performance are presented. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

This paper presents an improved saliency-based position sensorless drive of an interior permanent-magnet synchronous machine (IPMSM) with a single current sensor, used for low cost applications. The phase current, reconstructed from a dc-link current, shows a reconstruction error resulted from the difference of the sampling point from that of a full current sensor drive. This reconstruction error results in degradation of the overall sensorless control performance. In this paper, we analyze the impact of the reconstruction error depending on the injection frequency for a high frequency voltage signal injection sensorless control. Based on this analysis, we propose an improved position sensorless drive that employs a new current reconstruction method. In order to minimize the reconstruction error, the proposed current reconstruction method predicts the dq-axis currents with the same sampling point as a full current sensor drive. Several experimental results are provided to verify the analysis of the reconstruction error and the proposed method's improved sensorless control performances. [ABSTRACT FROM PUBLISHER]

Digital current controllers have the key impact on the performance of grid-side converters and ac drives. The voltage disturbances are commonly suppressed by enhancing the controller with an inner active resistance feedback. In cases where the switching noise and parasitic oscillations introduce sampling errors, conventional sampling is replaced by the oversampling-based error-free feedback acquisition which derives the average of the measured currents over the past switching period. The time delay introduced into the feedback path creates difficulties in designing the current controller with the active resistance. In this paper, we introduce a novel structure of the current controller, which includes the error-free sampling and the active resistance feedback. Devised structure improves the disturbance rejection by extending the range of permissible values of the active resistance. Controller structure is based on the internal model principles, and it maintains the input step response unaffected. This paper comprises analytical design, the gain setting procedure, computer simulation, and experimental results obtained from an experimental setup with a three-phase inverter, digital controller, and a permanent-magnet synchronous motor. [ABSTRACT FROM PUBLISHER]

In this paper, an LLC type converter with two interleaved pulsewidth modulation (PWM) rectifiers is proposed. Compared with the conventional LLC converter, it achieves a wide voltage regulation range independent of load. In the proposed structure, each secondary-side PWM rectifier can operate individually. With the interleaving technique and shared primary-side switching network, the circuit secondary-side current stress is halved and the primary-side current stress is largely reduced. Besides, the filter capacitor requirement is reduced. Therefore, the proposed structure is a good option for medium/high power wide output range applications. The symmetrical LLC resonant tanks always operate at the resonant frequency, which marks the optimal operation point of the LLC resonant tank. Therefore, the conduction loss is effectively mitigated. In the proposed converter, zero-voltage turning-on (ZVS) of the primary-side MOSFETs can be ensured and is independent of the load. Moreover, the turning-off currents of the primary-side MOSFETs are small and are also load independent. This brings the benefits of minimized circulating current and negligible turning-off loss and no MOSFET turning-off voltage spike. The secondary-side auxiliary MOSFETs turn-on with ZVS and rectifying diodes turn-off with limited di/dt. Topological analysis and experimental results of a 1.3 kW/100 kHz prototype generating 230–440 V output from 390-V input are presented. The prototype demonstrates 97.31% peak efficiency and good performance over a wide output range. [ABSTRACT FROM AUTHOR]

Wide bandgap semiconductors with fast switching speed capability are becoming an enabler to achieve the higher power density design. However, the further increase of switching frequency cannot continuously improve the power quality of ac-side waveforms in dc–ac/ac–dc application. The main reason is the distortion of pulsewidth modulation (PWM) voltage at switching point under high switching frequency. In general, there are two contributors causing PWM voltage distortions in bridge-based topologies. One is the deadtime, which occupies higher ratio in the small duty cycle case under high switching frequency and induces the voltage errors. The other one is the turn-off transient in the small load current or around the zero-crossing point of the ac-side current, because the relatively slow rising slope of the drain–source voltage will affect the right duty cycle. To solve this issue, this paper proposes a closed-loop modulation scheme to compensate the duty cycle distortion of PWM voltage based on one-cycle control or charge control. Compared to the traditional feedforward type of compensation, the proposed scheme does not need online calculation and instantaneous inductor current sampling, and it shows potential to be a general scheme for variety of topologies and modulations. Simulations and experiments are carried out on a 400-kHz single-phase full-bridge inverter with 400-Hz fundamental frequency to demonstrate the performance of the proposed approach. [ABSTRACT FROM AUTHOR]

According to different clamping methods, nine modes (C_MODE1-9) of the traditional discontinuous pulsewidth modulation (DPWM) for neutral-point-clamped three-level converter have been revealed. Since traditional DPWM cannot balance neutral point (NP) voltage under the full range of modulation index (MI) and power factor (PF), two extended modes (E _MODEs) are proposed in this paper, which can balance NP voltage. The proposed extended discontinuous pulsewidth modulation (EDPWM) is characterized by using C_MODEs and E_MODEs alternately.Therefore, EDPWM can balance NP voltage under the full range of MI and PF. Since the switching numbers under C_MODE and E_MODE in one switching cycle are two and three, respectively, the switching loss under EDPWM is lower than that under other pulsewidth modulation (PWM) strategies. The performance of EDPWM is analyzed and compared with traditional DPWM, space vector PWM (SVPWM) and virtual SVPWM (VSVPWM) in terms of switching loss, waveform quality, and the ability of NP voltage control. Finally, the feasibility and superiority of the proposed method are verified by experiments. [ABSTRACT FROM AUTHOR]

The shunt regulator is a key part of the power conditioning unit, which is becoming more and more important in the spacecrafts. Due to the nonlinear link, the switch operating with hysteresis control, the shunt regulator is a nonlinear system; however, the stability analysis method for the system is still grounded on the approximate linearization method, which neglects some of the ac and dc characteristics. In this paper, a novel stability analysis method for the nonlinear systems is proposed based on the describing function, which can be used to model the nonlinear link in the shunt regulator system. Further, the different conclusion of the shunt regulator system stability are drawn, by the approximate linearization method and the stability analysis method proposed in this paper, respectively. Finally, the simulation and experimental results prove the correctness of the stability analysis method with describing function and discover the incompletion of the approximate linearization methods on the stability analysis. Therefore, this paper provides a new way to analyze the stability of the nonlinear systems. [ABSTRACT FROM PUBLISHER]

This paper proposes unified non-inverting and inverting ac–ac converter (UNI-AC) using pulse width modulation (PWM) for the utility voltage compensation. It offers four effective switching states to regulate the output voltage in bipolar manner, facilitating versatile modes of operation with different number of switching states being modulated. Each mode of the proposed UNI-AC is able to compensate both the grid voltage sag and swell problems due to its bipolar voltage gain. The operational principle and comparison for all these modes are investigated in details. Also, the UNI-AC is reversible and compatible with full range of power factor. Other technical merits offered by the proposed approach include the compact hardware installation, reduced switch voltage stress (also low dv/dt) and decreased control complexity. Detailed analysis and experimental verification are presented in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a sinusoidal pulsewidth modulation (SPWM) based direct digital control with average-voltage model (AVM) and division–summation process for paralleled three-phase three-wire (3φ3W) grid-connected converters to reduce circulating currents. With the direct digital control, plant of each single-phase converter can be derived directly, and a controller is then designed to cover the variation effects of filter inductance and grid voltage. Based on SPWM and AVM over a switching cycle, each 3φ3W converter can be decomposed into three single-phase converters and each converter is controlled individually to track its sinusoidal reference current tightly, reducing circulating currents significantly. Equal current sharing is therefore also achieved. The control laws for achieving grid connection are derived in detail. In the design and implementation, the inductances corresponding to various inductor currents are measured offline and stored in the controller for scheduling loop gain cycle by cycle. Experimental and simulated results from a three-converter system confirm the analysis and discussion of the proposed control approaches. [ABSTRACT FROM AUTHOR]

Model-predictive current control (MPCC) is a promising candidate for modular multilevel converter (MMC) control due to its advantages of direct modeling and fast dynamic response. The conventional MPCC, which obtains the optimal control input by evaluating a cost function for all the possible switching states, may make the MPCC impractical due to the exponentially increasing computation burden with the increasing number of submodules (SMs). On the other hand, the MPCC experiences high load current and circulating current tracking errors, since only one switching state is selected and applied during one control period. To address these issues, this paper proposes an MPCC with phase-shifted pulsewidth modulation (PS-PWM) for improving the steady-state control performance. The arm voltages are considered as a whole to implement the proposed MPCC. The optimal duty cycle is obtained based on the load and circulating current tracking error minimization and applied using the PS-PWM. As a result, the computation burden is unrelated to the number of SMs by avoiding the exhaustive evaluation process for all the possible switching states. A better steady-state performance with smaller tracking errors is achieved with the similar switching frequency, and the tedious tuning process of the weighting factor is eliminated. Experimental results are presented to demonstrate the effectiveness of the proposed MPCC. [ABSTRACT FROM AUTHOR]

This paper presents a five-phase dual random space vector pulsewidth modulation (FPDR-SVPWM) strategy with an optimized probability density function (PDF) for a five-phase voltage-source inverter, and its performance and evaluation are also analyzed. Based on the nearest four vectors modulation method, the FPDR-SVPWM strategy, combined with random switching frequency and random zero vector, is investigated to significantly reduce the amplitude of high-order harmonics near the switching frequency and its integer multiples. For the nonsinusoidal power supply, third harmonic injection is introduced in this modulation strategy as well. Considering the effect of random numbers on the performance, an optimized Beta distribution is studied in detail. In order to analyze harmonic dispersion degree qualitatively and quantitatively, the power spectral density and the harmonic spread factor are both employed to assess the performance of the FPDR-SVPWM strategy. A series of results of simulation in MATLAB and experiments based on field programmable gate array demonstrate that the proposed modulation strategy is correct and valid, and it distributes high-order harmonics into a wide range without affecting the fundamental wave and third harmonic. [ABSTRACT FROM AUTHOR]

To reduce the common-mode voltage (CMV) and eliminate the CMV spikes for two-level voltage source inverters (2L-VSIs), an improved model predictive control (MPC) based CMV reduction method is proposed in this paper considering dead-time effects. First, an improved voltage vector (VV) preselection strategy is proposed to reduce the CMV spikes caused by the dead time. Second, a new hybrid VV preselection strategy based on a delay compensation strategy and a modified current sector division strategy is proposed to completely eliminate the CMV spikes. As the proposed hybrid VV preselection based MPC strategy makes full use of the six nonzero VVs of the 2L-VSI, the current total harmonic distortions and ripples are reduced. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Discontinuous modulation applied to modular multilevel converters is an effective method for reducing the capacitor voltage ripples. In this paper, the discontinuous modulation is adapted and used in a motor drive application. For proper operation of the converter, a new energy controller is presented, which is suitable for operation with nonsinusoidal reference signals. Experimental results comparing the discontinuous modulation with other techniques operating at low motor speeds are shown. The results demonstrate the effectiveness of the discontinuous modulation on reducing capacitor voltage ripples and power losses. [ABSTRACT FROM AUTHOR]

This paper presents a modified modular multilevel converter with the three-terminal middle-cells inserted between arms and ac-side for medium voltage applications. It is intended to reduce the submodule capacitor voltage ripples by controlling the high-frequency powers flowing among arm branches for low-frequency output operations without common-mode voltage injected in ac-side. Due to the physical connection among the upper arm, the lower arm and ac-side, the middle-cell can be regarded as the excess degree of freedom to modify the dc-side and ac-side characteristics. Therefore, the common-mode voltage in ac-side can be eliminated by the inverse common-mode voltage produced by the middle-cell in ac-side. Moreover, owing to the unique structure of the middle-cell, the middle-cell capacitor voltage also results in a small ripple due to the high-frequency current flowing into it by proper control. The operation principle and control strategy of the middle-cell has been proposed in detail. Simulation and experimental results have verified the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

Single-stage power-factor-corrected (S2PFC) power supplies usually suffer from high voltage stress, due to lack of control on the intermediate bus capacitor voltage. In the past, analysis of such voltage stress was mostly based on steady-state condition without providing sufficient explanation during the transient circuit operation. This paper revisits the problem at circuit level and reports that the root cause is due to the inherent negative current feedback property of the output inductor or the transformer operating in continuous conduction mode (CCM). Based on the finding, this paper further proposes a new approach to reducing the voltage stress by adding an auxiliary circuit branch to existing S2PFC converters. The additional circuit branch limits the effect of negative current feedback by suppressing the change of output current slope due to change of load. This assists the pulsewidth modulation controller to track the change of load better such that the bus capacitor voltage range is reduced through duty cycle control. The auxiliary circuit branch also reduces reverse-recovery-related losses of the converter under CCM operation. A laboratory prototype using the popular boost PFC converter combined flyback dc/dc converter was built and tested to confirm the analysis and effectiveness of the approach. [ABSTRACT FROM AUTHOR]

Exploiting the rich switching redundancies of the dual inverter, new hybrid pulsewidth-modulation (PWM) switching methods are proposed in this paper using the degree of freedom of operating the individual inverters independently, in addition to exercising the degree of freedom of controlling the switching action of the individual legs independently. Two voltage entities, namely, common-mode voltage (CMV) and differential-mode voltage are identified in the dual inverter, and all hybrid PWMs are envisaged aimed at reducing and also eliminating the CMV in it. The effects of such attempts on motor shaft voltage and also the motor bearing currents are presented in detail. Furthermore, bearing current profiles of an open-end winding induction motor are also presented with both conventional and hybrid PWMs proposed in this paper. Electric discharge machining discharge currents are completely eliminated with the use of all hybrid PWM methods proposed in this paper. In addition, implications of completely eliminating the CMV are also presented in this paper. All hybrid PWMs proposed in this paper are first simulated using MATLAB and are experimentally verified on a dual two-level inverter feeding a 1.1-kW 415-V 3- $\phi$ open-end winding induction motor drive. [ABSTRACT FROM PUBLISHER]

A two-motor drive, supplied by a five-leg inverter, is considered in this paper. The independent control of machines with full dc-bus voltage utilization is typically achieved using an existing pulsewidth modulation (PWM) technique in conjunction with field-oriented control, based on PI current control. However, model predictive control (MPC), based on a finite number of control inputs [finite-control-set MPC (FCS-MPC)], does not utilize a pulsewidth modulator. This paper introduces three FCS-MPC schemes for synchronous current control in this drive system. The first scheme uses all of the available switching states. The second and third schemes are aimed at reducing the computational burden and utilize a reduced set of voltage vectors and a duty ratio partitioning principle, respectively. Steady-state and transient performances are analyzed and compared both against each other and with respect to the field-oriented control based on PI controllers and PWM. All analyses are experimental and use the same experimental rig and test conditions. Comparison of the predictive schemes leads to the conclusion that the first two schemes have the fastest transient response. The third scheme has a much smaller current ripple while achieving perfect control decoupling between the machines and is of low computational complexity. Nevertheless, at approximately the same switching loss, the PI-PWM control yields the lowest current ripple but with slower electrical transient response. [ABSTRACT FROM PUBLISHER]

Conventional zero-voltage and zero-current-switching (ZVZCS) full-bridge converters are widely used because they can realize zero-voltage switching (ZVS) for the leading leg and zero-current switching (ZCS) for the lagging leg. However, the large turn-off loss of the leading leg is still unacceptable in high-voltage high-power applications where insulated-gate bipolar transistors (IGBTs) with current tailing are employed. Hence, it is preferable to achieve ZCS for all IGBTs of full-bridge converters. This paper analyzes the ZCS conditions for pulsewidth modulated (PWM) full-bridge converters and proposes a general strategy for achieving ZCS for main switches, including the control strategy and design method of the topology. Based on this theory, a novel ZCS PWM full-bridge converter with simple auxiliary circuit is derived and tested. It can achieve ZCS not only for the main switches of full-bridge converter, but for the auxiliary switch as well, and obtain high efficiency. The operation principle of the proposed ZCS PWM full-bridge converter and the design procedure are presented. The experimental results of a 600 V/2.5 kW prototype are also included to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

This paper extends the trans-Z-source concept to ac–ac power conversion and proposes a novel single-phase trans-Z-source ac–ac converter. The proposed converter retains the advantages of its existing Z-source/quasi-Z-source counterparts in which the output voltage can be boosted and in-phase with the input voltage or bucked/boosted and out-of-phase with the input voltage. Meanwhile, a coupled inductor is introduced into the proposed converter, and the turns ratio of the coupled inductor become another control variable beside the duty cycle to obtain extreme voltage gain. Importantly, the input voltage and output voltage share the same ground, and the input current could be continuous, which is a benefit for reducing input current harmonics. Most important of all, the safe-commutation strategy for the proposed converter is deep developed, and analytic expression between the switches state and loop circuit voltage/current condition is derived out. Hence, the current/voltage ripple can be avoided without a loss snubber circuit, which benefits a reduced cost and enhanced reliability. The performance analysis is discussed in consideration of parasitic resistance, and system parameter design is optimized based on theoretic calculation. A laboratory prototype is fabricated, and experiments are performed to verify the validation of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper aims to investigate a disturbance-rejection-based model predictive control (MPC) with two flexible modes (i.e., unconstrained mode and constrained mode) for three-phase inverters with an $LC$ filter. A disturbance observer (DOB) is designed to both simplify the prediction model and achieve the robustness against uncertain parameters. First, the unconstrained mode is designed with a simple horizon-one MPC control law to precisely regulate the output voltage in the steady state. Next, the constrained mode is designed with long-horizon MPC to quickly drive the system to the unconstrained mode by further optimizing the modulation stage. Also, the proposed MPC ensures the robustness and optimality in all operating modes. Especially, the overall closed-loop stability with DOB dynamics is proven by using Lyapunov function. Unlike other MPC methods, the long-horizon MPC in the constrained mode is specialized by finite switching sequences of the sector-based space vector modulation. Comparative studies with the conventional linear quadratic regulator are conducted on a prototype test bed with a TI TMS320F28335 DSP. Then, the proposed MPC method verifies fast dynamic response and advanced voltage regulation (i.e., small steady-state errors and low total harmonic distortion) under various load conditions and uncertain parameters. [ABSTRACT FROM AUTHOR]

Compared with multilevel space vector modulation, level-shifted multicarrier sinusoidal pulsewidth modulation (SPWM) for nested neutral point-clamped (NNPC) inverters requires much less calculations and implementation efforts, but the existing conventional SPWM cannot suppress the severe flying-capacitor (FC) voltage ripples under low output-frequency conditions. In order to solve this problem, a multicarrier-based PWM strategy with complete voltage balance control (VBC) capacity is proposed in this paper. For NNPC inverters operating under low output-frequency conditions, two preprocessing steps, the zero-sequence injection and the modulation-signal rearrangement, are proposed before the comparisons between level-shifted carriers and modulating signals. These preprocessing steps make the average currents flowing through FCs zero, which is beneficial to greatly reduce the FC voltage ripples under low output-frequency conditions. Together with additional VBC, the proposed modulation can assure the FC voltages balanced under the entire output-frequency conditions. Principles and implementation processes of proposed modulation techniques and VBC methodsare elaborated in detail and compared with conventional modulation methods. Both simulation results from a 5-MVA system and experimental results based on a 5-kVA platform are presented to verify the effectiveness. [ABSTRACT FROM AUTHOR]

The parallel three-phase grid-connected converters sharing dc and ac bus can increase the system power level effectively. However, the circulating current will occur inevitably. The existing studies primarily focus on dc, fundamental, and low-frequency circulating current. The high-frequency circulating current (HFCC) caused by asynchronous carriers is studied emphatically in this paper, which is based on the analysis of the change of circulating current in one control cycle. A novel method to suppress HFCC caused by asynchronous carriers of modules is proposed. In this method, the carrier period of slave module is adjustable and the carrier period of the master module is constant. When a large phase shift between modules occurs, an adjusting cycle is inserted to carrier of slave module to realize resynchronizing with master module. It is noted that there is no other commutation between the two modules (expect the dq current reference), such as the carrier information. Finally, the feasibility and effectiveness of the proposed method are verified by experiments. [ABSTRACT FROM PUBLISHER]

A fixed-frequency pulse width modulation (PWM) controlled bidirectional current-fed series-resonant converter is proposed in this paper. The proposed bidirectional resonant converter is derived based on integration of a bidirectional boost/buck converter and a dual-active-bridge series-resonant converter. The most attractive feature of the proposed bidirectional resonant converter is that its voltage gain is only determined by the duty cycle of primary-side switches and has nothing to do with the transferred power. Therefore, the direction and amplitude of the transferred power can be easily regulated continuously and smoothly. In addition, with the help of an auxiliary inductor, zero voltage switching can be achieved for all the active switches on both primary and secondary sides within the entire operation range. Furthermore, the converter is suitable for wide voltage applications because its voltage gain can be regulated in a wide range. The operational principles and characteristics of the proposed bidirectional resonant converter are analyzed in detail. The feasibility and effectiveness of the proposed converter are fully verified by the experimental results from a 1.6 kW prototype. [ABSTRACT FROM AUTHOR]

Neutral-point (NP)-clamped three-level inverter, which is a widely used topology of multilevel converters, suffers from the NP voltage drift as its main technical drawback. The nearest-three-virtual-vector (\NTV^2) modulation method can control the NP voltage balance for any load over the full range of inverter output voltage. However, compared with the nearest-three-vector (NTV) modulation method, \NTV^2 increases the switching frequency. This paper combines \NTV^2 with NTV, and the two methods are used alternately in a fundamental cycle. The duty-cycle coefficients of the redundant small vectors are analyzed to explore the intervals where NTV can control the NP voltage balance in a fundamental cycle. The proportional parameter, which represents the combination of the two methods in hybrid space vector pulsewidth modulation, can be selected to achieve a high-performance NP balance control and low switching frequency. The steady- and transient-state behaviors of the proposed strategy are analyzed in this paper. The experimental results verify the validity of the proposed strategy. [ABSTRACT FROM PUBLISHER]

This paper presents a modulation strategy for the modular multilevel converter (MMC) which provides the voltage balancing of the capacitors of different submodules comprising the converter. Not only is this modulation applicable to MMCs constructed with classic two level (2L) submodules, but it is also effective for arrangements with different submodule concepts, for instance, topologies like neutral point clamped (NPC), flying capacitors (FCs), neutral point piloted (NPP), etc. Therefore, firstly, the general modulation philosophy is explained applied to the two level (2L) submodule concept, and secondly, the extension to 3L-NPC and 3L-FC submodule topologies is analyzed. After that, the validation of the studied modulation strategy is carried out by means of successful simulation results, at different switching frequencies and number of submodules. The corresponding experimental results are shown in Part II of this paper after having implemented the aforementioned modulation strategy in a real test bench. In addition to this, a comparison based on thermal analysis and sizing of elements among the four studied submodule topologies is also included. [ABSTRACT FROM PUBLISHER]

In recent years, high photovoltaic array voltage up to 1000 V and transformerless grid-tied inverter have been increasingly researched and applied to elevate the inverter and the dc power collection efficiency. With the same reasons, a three-level neutral point clamped (3L-NPC) inverter featuring low power device voltage stress and low leakage current becomes increasingly attractive. In this paper, the operation and the features of a novel grid-tied 3L-NPC are presented. The proposed topology is a derivative of the three-level stacked neutral point clamped (3L-SNPC) structure. However, compared with the conventional 3L-SNPC and its pulse width modulation (PWM) strategy, the new topology with novel PWM strategy features completely inactive intrinsic body diodes. Furthermore, only two outer power devices are working with switching frequency, while the other four Insulated Gate Bipolar Transistors (IGBTs) are actually with the grid frequency. Therefore, the relatively high switching frequency is selected to reduce the inverter output filter inductance. A hybrid CoolMosfet and IGBT power module configuration is also proposed based on the new PWM strategy. The calculation shows that the total power device losses are reduced. The experimental results are illustrated in this paper to confirm the operation of the proposed topology and controller. [ABSTRACT FROM PUBLISHER]

In this paper, an immune algorithm (IA) is developed for optimization of the harmonic performance of a three-phase inverter under the space-vector pulsewidth-modulation (SVPWM) control strategy. The presented algorithm employs the immune approach as the search method for finding the best optimal control vectors and action time of the three-phase inverter. As a result, the optimal control vectors and action time are calculated to minimize the objective function of the weighted total harmonic distortion of the output voltage waveforms. In addition, an experimental platform based on DSP and field-programmable gate array is built. This paper provides a detailed performance analysis of the method with comparison to the conventional SVPWM. The simulation and experimental results verify the superiority of the best control sequences generated by IA compared with the existing conventional control strategies. [ABSTRACT FROM PUBLISHER]

A new pulse width modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is developed and presented in this paper. The proposed PWM scheme not only takes advantage of the special properties available in NPC inverters, but also reduces the switching loss of the inverter along with an inherent neutral point (NP) voltage control. Based on a circuit-level decoupling concept, the NPC inverter can be decoupled into two three-level Buck converters in every defined operating section, and thereby the controller design can be simplified. The salient features of the proposed scheme, as compared with the existing carrier-based DPWM strategies, are: 1) its reduced computational processing time, 2) its capability to balance the dc-link voltage without any additional control, and 3) its reduced complexity, e.g., only one carrier wave needed for pulse width modulating. Same as a space-vector modulation, the maximum modulation index, 1.1547, can be attainable by the proposed scheme. Moreover, compared to conventional continuous sinusoidal PWM, using this technique proposed here, the switching losses of the devices can be reduced by one third. In order to explain the operation of this topology properly, the decoupling principle including the driving signal synthesis and the NP potential variation are analyzed in detail in this paper. Finally, the viability and performance of the proposed modulation scheme are shown through simulation and experimental results in a laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a new active capacitor voltage balancing control method for the flying capacitor multicell (FCM) converters which is fully implemented using logic-form equations. The proposed active capacitor voltage balancing control technique, measures output current and flying capacitor (FC) voltages to generate the switching states in order to produce the required output voltage level and to balance FCs’ voltages at their reference values. Output voltage of the FCM converter controlled with proposed active capacitor voltage balancing method can be modulated with any pulse width modulation (PWM) technique such as the phase-shifted-carrier PWM or level-shifted-carrier PWM. An advantage of the proposed active capacitor voltage balancing control method is its simplicity as it does not require any complex computations and tedious optimization calculations. Simulation results and experimental measurements of a three-cell four-level and four-cell five-level FCM converters are presented to verify the performance of the proposed active capacitor voltage balancing control technique. [ABSTRACT FROM AUTHOR]

This paper proposes a novel active capacitor voltage balancing technique for stacked multicell (SM) converters. The proposed active capacitor voltage balancing control method detects the direction of the load current and measures the voltage of flying capacitors (FCs) to generate a proper switching state in order to form the required output voltage level and regulate the FC voltages at their desired reference levels. The proposed active capacitor voltage balancing control technique can modulate the output voltage through any of the pulse-width-modulation (PWM) techniques such as the phase-shifted carrier PWM or the level-shifted-carrier PWM. The foremost advantage of the proposed active control technique is that it does not demand any complex computations because it is not based on the optimization of the FC voltage-deviation cost functions. A thorough set of simulation results and experimental measurements for the five-level and seven-level SM converters are provided to validate the proposed active capacitor voltage balancing control method. [ABSTRACT FROM AUTHOR]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

This paper presents a new multicell topology based on flying capacitor (FC) structure suitable for multilevel converters. The proposed topology employs the concept of phase-shifted carrier pulse width modulation (PWM) with modified modulating signals to generate appropriate PWM signals. The modulation strategy along with all possible switching states are explained. The implementation of the proposed PWM technique is shown by the help of illustrating waveforms. To show the advantages of the proposed structure, different performance criteria are compared with other FC multicell (FCM) structures. Simulation results are used to further evaluate the potential merits of the proposed topology. It is shown that the proposed structure is superior to other FCM-based structures from different standpoints. Specifically, it reduces the number of high-frequency switches, the number of FCs, and at the same time improves the quality of output voltage. A laboratory-type experimental setup is used to validate the modulation strategy and other theoretical findings. [ABSTRACT FROM AUTHOR]

In grid-connected inverters, a feedforward controller accurately compensates for a large number of the harmonic components of the injected current. This controller is fast and directly tackles the grid dynamic voltage disturbances without doing any further harmonic analysis. A feedforward controller was introduced to a three-phase grid connection with a wye configuration; however, for the widespread delta connections, such a scheme is less established. Moreover, the nonsinusoidal profile of the grid voltage waveform makes the online conversion of line-to-line values into phase values impossible. In this paper, implicit zero-sequence discontinuous pulse width modulation (IZDPWM) based feedforward control is implemented on the two-level grid-connected inverter. Regardless of the grid topology, the IZDPWM-based controller ensures sinusoidal current injection to the grid under balanced, unbalanced, and distorted conditions. [ABSTRACT FROM PUBLISHER]

Compensation of nonlinear effects generated by dead-time and semiconductors voltage drop has been widely studied in the literature about two-level converters. This paper takes a closer look at those analyses for multilevel converters, specifically for a cascaded H-bridge (CHB) converter modulated with phase-shifted pulse width modulation. The interaction between the cells is analyzed for a generic $n$ -cell converter, from which a general expression for the distortion generated by the nonlinearities has been obtained. Based on this expression, a compensation signal for the overall converter is calculated on each sample time, which is a fraction of the triangular carrier used to modulate each cell, thus significantly improving the quality of the output voltage signals. Experimental validation of the proposed compensation method is presented using a three-phase four-cell CHB converter prototype of 5.5 kW. [ABSTRACT FROM AUTHOR]

In this paper, an improved model predictive control (MPC) of the modular multilevel converter (MMC) with reduced computational burden is proposed. A mathematical model of the MMC system based on the sum and difference of arm voltages are derived. Instead of determining the switching state of individual submodule (SM), the voltage levels of MMC are considered as control options based on the assumption that the SM capacitor voltages are well balanced. The further reduction of calculation effort is realized by using the tolerance band of capacitor voltages. The proposed MPC has a hierarchical structure. The cost function taking into account the ac-side current control, circulating current elimination and arm energy balancing is presented. The optimal voltage level, selected by the cost function, provides the voltage reference for the pulse width modulation modulator. The SM capacitor voltage balancing is done using a separate control loop. The proposed control strategy is investigated using an MMC high-voltage direct current system with 200 SMs in each arm in real-time simulation and hardware-in-the-loop tests. The performance of proposed method is verified by both steady-state and transient-state operations. [ABSTRACT FROM PUBLISHER]

This paper presents a review of the most popular control and modulation strategies studied for matrix converters (MCs) in the last decade. The purpose of most of these methods is to generate sinusoidal current on the input and output sides. These methods are compared considering theoretical complexity and performance. This paper concludes that the control strategy has a significant impact on the resonance of the MC input filter. [ABSTRACT FROM AUTHOR]

This paper proposes a unified PWM method for matrix converters so as to establish a common platform which can generate various types of PWM methods in real time by adjusting the free parameters in the modulation algorithm. As a foundation for unification, the general form of the modulation functions for matrix converters is derived using geometric transformation approach. All eligible direct modulation matrices are shown to be of indirect form and are expressed in terms of instantaneous phase quantities. This paper also presents a new viewpoint to consider a matrix converter as a generalized three-level inverter and to apply the double-carrier-based dipolar modulation technique of the three-level inverter to the matrix converter. Several concepts of the two-level PWM inverters are then generalized to the matrix converters for better visualization and understanding of the modulation process. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

AC–DC–AC converter-fed induction motor (IM) drive is mainly realized by back-to-back three-phase converters. However, fault in a single semiconductor switch will make it inoperative. To enable continued controllable operation in case of the faults occurring in the converter, the five-leg converter with a shared leg between the grid and load sides is a possible solution. However, this topology poses an inherent two-objective control problem, because its grid and load sides should be controlled simultaneously. More importantly, the potential increase of the shared-leg current may destroy the converters. In this paper, a new control scheme based on the FCS-MPC combined with intrinsic characteristic of the five-leg converter is proposed for independent control of the rectifier and inverter subsystem with the shared-leg overcurrent constraint. The condition for independent control is analyzed. In order to give a complete evaluation of the proposed control scheme, the conventional pulsewidth modulation (PWM) control scheme is conducted for comparison. Experimental results are provided to validate the effectiveness of the proposed scheme. [ABSTRACT FROM PUBLISHER]

Semiactive quadrupler rectifiers (SAQRs) are proposed in this paper to serve as the secondary rectification circuits, which make the secondary-side voltages to be controllable and help reduce current stress and conduction losses. An interleaved isolated boost converter is developed based on the proposed SAQRs. By utilizing the pulse-width modulation (PWM) plus phase-shift (PPS) control strategy, the primary- and secondary-side voltages are well matched to reduce the current values and circulating conduction losses. With the proposed SAQRs, the voltage gain is extended and the voltage stresses on power devices and passive components used in rectification circuits are reduced to the half of the high output voltage. Hence, the efficiency is improved by using a transformer with a smaller turns ratio and reduced parasitic parameters, and by employing low-voltage rating devices with better switching and conduction performance. With optimal design, lower voltage, and current stresses on the primary-side switches, minimized input current ripple can be realized. Moreover, the zero-voltage turn on switching of the active switches and the zero-current turn off switching of the diodes can be achieved over a wide load and voltage range by the proposed SAQR-based converter and the control strategy. Meanwhile, the higher voltage gain, the lower voltage, and the current stresses on power devices can be obtained with the proposed SAQR-based converter compared with passive quadrupler rectifier-based converter. The feasibility and effectiveness of the proposed SAQRs and the derived converter are verified by a 380-V output prototype. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

It is known that the ripple-based control of a switching dc–dc converter benefits from a faster transient response than a conventional pulse width modulation (PWM) control switching dc–dc converter. However, ripple-based control switching dc–dc converters may suffer from fast-scale oscillation. In order to achieve fast transient response and ensure the stable operation of a switching dc–dc converter over a wide load range, based on a conventional pulse train (PT) control technique, a peak capacitor current PT (PCC-PT) control technique is proposed in this paper. With a buck converter as an example, the operating modes, steady-state performance, and transient respond performance of a PCC-PT controlled buck converter are presented and assessed. To eliminate fast-scale oscillation, circuit and control parameter design considerations are given. An accurate discrete iteration model of a PCC-PT controlled buck converter is established, based on which the effects of circuit parameters on the stability of the converter operating in a discontinuous current mode (DCM), mixed DCM-continuous conduction mode (CCM), and CCM are studied. Simulation and experimental results are presented to verify the analysis results. [ABSTRACT FROM PUBLISHER]

Carrier-based pulsewidth-modulation (CBPWM) techniques are popular due to their simplicity, and have been widely researched for various three-phase inverter configurations. In this paper, two CBPWM techniques are proposed to reduce the common-mode (CM) voltage generated by the five-phase inverter. The five-phase inverters have more flexibility in reducing the CM voltage than their three-phase counterparts because they have more phase legs, hence finer control over the star-point voltage of the load. Two methods are proposed for the conventional two-level five-phase inverter to reduce the CM voltage; one utilizing adjacent modulating waveforms and the other utilizing nonadjacent modulating waveforms. The coupled inductor inverter (CII) uses coupled inductors to generate multilevel outputs. As the volt-second balance must be maintained across each coupled inductor, direct application of the proposed methods on the CII inverter will result in overcurrents in the coupled inductors. Hence, the proposed methods are further improved to ensure the volt-second integral over each switching period is zero. Moreover, the two proposed methods are designed to reduce switching events and prevent unexpected states occurring during the switching transitions. The performance and the switching strategy of both methods are verified by both simulations and experiments on a prototype of five-phase CII. [ABSTRACT FROM AUTHOR]

A novel complementary phase disposition pulsewidth modulation method for the modular multilevel converter (MMC) with a limited number of submodules is proposed in this paper. Compared with the previous works, more practical issues have been considered, and the corresponding solutions have been provided. First, a new preset PWM signal mapping sequence and an improved virtual loop mapping (VLM) are used in the modulation. This method not only achieves a favorable capacitor voltage balance in the symmetry system but lowers the switching frequency of MMC's devices. Second, to further reduce the switching frequency, the unbalance margin of capacitor voltages is adopted to achieve the switching between the VLM and the selective VLM (SVLM). Moreover, the system robustness has been improved by considering the situation of symmetry losing, like cell fails; in these cases, the capacitor voltages of the upper and lower arms are balanced through the collaboration of the SVLM and the reconfigurable VLM. Finally, the effectiveness of the proposed method has been verified with simulation and experimental studies. [ABSTRACT FROM AUTHOR]