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This paper presents two improved double line voltage synthesis strategies for matrix converters. Both strategies redistribute the on-time intervals of the switches to reduce the output voltage error caused by the limit of minimum safe pulsewidth during commutation process. The first strategy reconstructs the modulation law according to the relationship between the input and the output voltages. The second strategy takes the current relationship into account, and the on-time intervals are calculated using the instantaneous output currents. Without increasing the commutation times and switching losses, the proposed strategies can decrease the number of pulses whose duty cycles are less than the minimum limit and improve the output voltage waveform. Moreover, the second one can also enhance the input current quality. Numerical simulations and experiments with a 10-kW prototype are carried out. The results are given to verify the feasibility and effectiveness of the proposed strategies. [ABSTRACT FROM PUBLISHER]

Commutation torque ripple of brushless DC motor (BLDCM) is caused by the different current slew rates between switching-in phase and switching-out phase. If the slew rates were equal, commutation torque ripple could be eliminated. A simple full speed range method was presented in this paper to eliminate commutation torque ripple by dividing each pulsewidth modulation (PWM) period into three segments during commutation time. By selecting proper proportions of these three segments, the average current slew rate of switching-in phase can be kept equal with the average rate of switching-out phase in each PWM period. Because the commutation time is controllable in the presented method, commutation process which is bad for the operation of BLDCM can be finished in its highest speed. The theoretical derivation is given, the experimental results show that the commutation torque ripple can be eliminated in the minimum commutation time, and output power of BLDCM under rated load can be improved. [ABSTRACT FROM PUBLISHER]

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable controller, and fault detection scheme. For experimental tests, the control and the fault detection and reconfiguration schemes are implemented on a single field-programmable gate array (FPGA) chip. Experimental and simulation results show the effectiveness of the proposed fault-tolerant topology and its FPGA-based control. [ABSTRACT FROM PUBLISHER]

This paper presents a new soft-switching dc/dc converter for high-input-voltage applications. Two half-bridge converters connected in series with interleaved asymmetric pulsewidth modulation (PWM) are adopted to limit the voltage stress of each power switch at one-half of the input dc bus voltage. In each half-bridge converter, two asymmetrical dc/dc circuits with the same active switches are connected in parallel at the output side to share the load current and reduce the current stresses of the secondary windings and rectifier diodes. Since two half-bridge converters are operated with interleaved PWM, the output ripple currents partially cancel each other so that the resultant ripple current at the output side is reduced. Active switches in the proposed circuit can be turned on at zero-voltage switching during the transition interval due to the resonant behavior by the output capacitance of MOSFETs and the leakage inductance of transformers. Experiments based on a laboratory prototype with 960-W rated power are provided to demonstrate the performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

In high current applications, paralleling three-phase voltage sourced inverters represents a modular solution for improving the system power conversion quality. Single-phase output reactors are often inserted between the output terminals of the two inverters that supply the same phase output. One function of these inductors is to limit circulating currents between the two inverters. These currents are produced by common-mode voltage differences between the three-phase output terminals of the two inverters. Since standard interleaved pulse width modulation (PWM) techniques naturally produce high-frequency common-mode voltage differences between parallel connected inverters, this paper describes a modified discontinuous PWM scheme that eliminates these voltage differences. As a result, a three-phase parallel inverter system can be operated using a single three-limb coupled inductor, significantly improving the system power conversion density as a result. An experimental 3 kW prototype system is used to compare the operation of the resultant inverter against one using separate single-phase coupled inductors. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point (NP)-clamped (ANPC) converter is a newly emerging topology which can overcome the drawbacks of traditional NP-clamped and flying-capacitor multilevel converters. This paper presents a comprehensive theoretical analysis of the NP potential balancing issue and demonstrates that the NP potential can be naturally balanced under ideal and steady conditions. An NP potential balancing method based on zero-sequence voltage injection is presented. By calculating the average NP currents of all key zero-sequence voltages, the most appropriate zero-sequence voltage is selected to generate the demanded NP current, which can also limit the switching frequency of the series-connected insulated-gate bipolar transistors to the fundamental frequency. A three-phase five-level ANPC inverter prototype is built up, and both steady and dynamic experimental results are presented to verify the validity of this method. [ABSTRACT FROM PUBLISHER]

This paper presents a novel pulsewidth modulation (PWM) strategy for n-level three-leg semiconductor-clamped dc–ac converters in the overmodulation region, with dc-link capacitor voltage balance in every switching cycle. The strategy is based on the virtual-vector concept. Suitable reference vector trajectories are selected to obtain low weighted total harmonic distortion and a simple algorithm. A hexagonal-boundary compression factor is introduced to guarantee, at any operating point, dc-link capacitor voltage regulation capabilities in every switching cycle and avoid narrow gate pulses. The detailed PWM algorithm for an easy implementation in a digital control platform is also presented. The good performance of the strategy is verified through both simulation and experiments in a three-level three-phase neutral-point clamped converter. [ABSTRACT FROM PUBLISHER]

The three-phase four-leg inverter is very suitable for the high-power uninterruptible power supply application, and the load neutral point voltage (LNPV) should meet the requirement. In this paper, two factors influencing the LNPV were revealed first, which are the switching states and the ratio of the neutral inductance to the phase inductance (k). Then, the 16 switching states can be classified into four groups, and the ones in the first and the second group come to the minimum amplitude of LNPV with a specific ratio k respectively. Third, three methods to mitigate the LNPV were proposed based on the analysis of LNPV. In the first method, switching states in the first group are just utilized, and the LNPV can be eliminated with the ratio k of unity. In the second method, the switching states in the fourth class are avoided, and the LNPV can be reduced. Common mode filter is used in the third method and the LNPV can be mitigated effectively with the ratio k of unity. Furthermore, the power losses in the first and the second method were estimated and were compared with the original situation. Finally, the proposed methods were verified by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 \mu \F dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach. [ABSTRACT FROM PUBLISHER]

Improved pulse regulation (IPR) control, a novel control technique for switching dc–dc converters, is proposed and studied in this paper. According to the output voltage and load current of the switching dc–dc converter, IPR control technique achieves output voltage regulation by generating control pulse train made up of some preset control pulses with different duty ratios. IPR control needs only comparators, triggers, and some simple logic devices, without error amplifier and the corresponding compensation circuit of pulse width modulation control scheme, thus IPR control scheme is easy to realize, benefits with excellent transient performance and stability. The principle and operation of IPR control scheme are introduced and illustrated with buck converter operating in discontinuous conduction mode as an example. Simulation and experimental results are presented to show that IPR-controlled converter has much lower output voltage ripple and more accurate output voltage regulation than PR converter. [ABSTRACT FROM PUBLISHER]

This paper discusses two overmodulation controls, namely, square wave and trapezoidal, in the indirect matrix converter (IMC) for motor drive application. The differences between these two modulations are analyzed based on the output–input voltage transfer ratio (VTR), the efficiency, and the current total harmonic distortions under two load conditions. Moreover, the performance is then improved by implementing four-step commutation methods in the primary side of the IMC. The validity of the proposed methods will be demonstrated through simulation and experimentally. The experimental results show that the VTR can be improved from 0.866 to 0.97 in the square wave modulation and 0.92 for the trapezoidal wave modulation in an induction motor drive system. [ABSTRACT FROM PUBLISHER]

Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance is highly superior to that of conventional two-level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages. However, it has some disadvantages such as increased number of components, complex pulsewidth modulation control method, and voltage-balancing problem. In this paper, a new topology with a reversing-voltage component is proposed to improve the multilevel performance by compensating the disadvantages mentioned. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels. Finally, a prototype of the seven-level proposed topology is built and tested to show the performance of the inverter by experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes a three-phase current reconstruction technique with an online current offset compensation function for three-phase inverter applications utilizing only a single current sensor. In the proposed current sensing method, a phase current and a branch current are simultaneously measured twice in a switching period by using a single current sensor. After that, the current reconstruction algorithm is applied to obtain the three-phase current information. Compared to previous single current sensor strategies, in the proposed method, the sensor output is regularly sampled, and the dead zone is located near the boundary of the voltage vector space instead of near the origin and the borders of each sector. This boundary-neighbored dead zone makes the proposed method more attractive in extremely low modulation index cases because it avoids periodical dead zones which have been an issue in the existing methods. Moreover, the online compensation method for a current measurement offset makes it possible to achieve purely balanced three-phase current control without an offset component. The effectiveness of the proposed method has been verified through simulations and experiments by measuring and reconstructing three-phase currents under various conditions. [ABSTRACT FROM PUBLISHER]

A three-level inverter produces six active vectors, each of normalized magnitudes 1, 0.866, and 0.5, besides a zero vector. The vectors of relative length 0.5 are termed pivot vectors. The three nearest voltage vectors are usually used to synthesize the reference vector. In most continuous pulsewidth-modulation (PWM) schemes, the switching sequence begins from a pivot vector and ends with the same pivot vector. Thus, the pivot vector is applied twice in a subcycle or half-carrier cycle. This paper proposes and investigates alternative switching sequences, which use the pivot vector only once but employ one of the other two vectors twice within the subcycle. The total harmonic distortion (THD) in the fundamental line current pertaining to these novel sequences is studied theoretically as well as experimentally over the whole range of modulation. Compared with centered space vector PWM, two of the proposed sequences lead to reduced THD at high modulation indices at a given average switching frequency. [ABSTRACT FROM PUBLISHER]

A simple current sharing control technique for the switching power supply is presented herein, whose basic concept is that the control effort created from the voltage loop is finely tuned by the control effort created from the current sharing loop based on the proposed phase link so as not only to obtain the desired output voltage but also to make the load current distributed among phases as evenly as possible. Such a control method is not only without any current sharing bus as compared with the traditional current sharing methods, but also suitable for multiple phases under the condition that any one phase among multiple phases fails. Moreover, based on phase link, there is no divider used, as compared with the traditional average current method, and hence, the number of logic elements in the field-programmable gate array (FPGA) can be reduced. In this paper, the detailed basic operating principles, together with new mathematical deductions based on the superposition concept, are firstly described, and secondly some experimental results, based on the FPGA to realize the fully digitalized control of the overall system using one-comparator counter-based sampling without any analog-to-digital converter (ADC), are provided to verify the effectiveness of proposed control strategy. [ABSTRACT FROM PUBLISHER]

This paper extends the Z-source concept to matrix converters and explores a family of Z-source matrix converters. Their principles and characteristics are analyzed, and a simplified voltage-fed Z-source matrix converter is used as an example to demonstrate its operation, voltage gain versus modulation index, PWM method, boost control, and implementation of the control. Both simulation and experimental results verify operation of the proposed Z-source matrix converter, analytical results, and control method. The Z-source converters can achieve buck and boost operation with reduced number of switches needed, therefore achieving low cost, high efficiency, and reliability, compared to the traditional matrix converters. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is responsible for overvoltage stress to the winding insulation and bearing damage of an ac motor. High dv/dt of CMV raises leakage currents, which can cause serious problems such as motor damage and electromagnetic noise to the equipment installed near the converter. This paper proposes two modulation strategies for indirect matrix converters that substantially eliminate CMV. The first method is developed by using the suitable couple of nonzero space vectors instead of zero space vectors in the inverter stage. The maximum voltage transfer ratio of this method is unaffected and remains 0.866. The second one, which is useful for low-voltage operation, is approached by choosing the medium and the lowest positive line-to-line input voltages in the rectifier stage to generate the dc-link voltage and by placing suitable zero space vectors in the inverter stage. In the second method, the maximum voltage transfer ratio is 0.5. Both methods can mitigate the peak value to 42%. In addition, while the first method provides the same performance to the conventional method, the second method can reduce significantly the harmonic components of line-to-line output voltage. Simulation and experimental results are shown to verify the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

This paper proposes a real-time DSP- and FPGA-based implementation method of a space vector modulation (SVM) algorithm for an indirect matrix converter (IMC). Therefore, low-cost and compact control platform is built using a 32-bit fixed-point DSP (TMS320F2812) operating at 150 MHz and a SPARTAN 3E FPGA operating at 50 MHz. The method consists in using the event-manager modules of the DSP to build specified pulses at its PWM output peripherals, which are fed to the digital input ports of a FPGA. Moreover, a simple logical processing and delay times are thereafter implemented in the FPGA so as to synthesize the suitable gate pulse patterns for the semiconductor-controlled devices. It is shown that the proposed implementation method enables high switching frequency operation with high pulse resolution as well as a negligible propagation time for the generation of the gating pulses. Experimental results from an IMC prototype confirm the practical feasibility of the proposed technique. [ABSTRACT FROM PUBLISHER]

This paper presents first an overview of the well-known voltage and current dc-link converter topologies used to implement a three-phase PWM ac–ac converter system. Starting from the voltage source inverter and the current source rectifier, the basics of space vector modulation are summarized. Based on that, the topology of the indirect matrix converter (IMC) and its modulation are gradually developed from a voltage dc-link back-to-back converter by omitting the dc-link capacitor. In the next step, the topology of the conventional (direct) matrix converter (CMC) is introduced, and the relationship between the IMC and the CMCs is discussed in a figurative manner by investigating the switching states. Subsequently, three-phase ac–ac buck-type chopper circuits are considered as a special case of matrix converters (MCs), and a summary of extended MC topologies is provided, including three-level and hybrid MCs. Therewith, a common knowledge basis of the individual converter topologies is established. [ABSTRACT FROM PUBLISHER]

Instead of directly sampling the phase currents, a technique that adopts a single current sensor in the dc link to reconstruct three-phase currents has arisen. Through this approach, the cost of servo systems can be reduced and the reliability can be improved. However, the duration of an effective vector may be so short that the phase current cannot be measured reliably by the conventional space-vector pulsewidth modulation (PWM) algorithm. In this paper, a new phase-current reconstruction method, switching-state phase shift (SSPS), is proposed based on the PWM pattern modification. The modification is performed by applying phase shifts to the switching-state waveforms of the inverter. The algorithm can realize high-quality reconstruction to the phase current with less impacts on the output current ripples and switching losses. Moreover, it can maximize the linear-modulation region by saturation handling. Measurements on the permanent-magnet synchronous motor servo drives show that the SSPS can offer an attractive performance during both steady-state and dynamic operations in the phase-current reconstruction and regulation. [ABSTRACT FROM PUBLISHER]

This paper presents a comparison between two stabilizing average output feedback controllers implemented on a field programmable gate array (FPGA) facility. A generalized proportional integral (GPI) controller and a proportional integral derivative (PID) controller are implemented using an FPGA, and their respective performances are duly compared. The GPI controller is found to present a better dynamic response than the PID controller in terms of the settling time while exhibiting a greater degree of robustness regarding disturbance rejection represented by severe changes in static and dynamic loads. The average controllers and their corresponding pulsewidth modulation actuators are implemented using a Spartan 3E1600 FPGA. [ABSTRACT FROM PUBLISHER]

In this paper, two space-vector-based pulsewidth modulation (PWM) (SVPWM) strategies named equal- and proportional-duty SVPWMs are described, which are used to synthesize a four-level waveform from an open-end winding configuration of an induction motor. Two isolated dc-link voltages, which are in the ratio of 2 : 1, are employed to achieve this objective. Both of these PWM strategies achieve the avoidance of overcharging of the dc-link capacitor of an inverter operating with lower dc-link voltage by its counterpart with higher dc-link voltage. Implementation of these PWM strategies requires only the instantaneous three-phase reference voltages, eliminating the need of sector identification or lookup tables. The numbers of samples per cycle for individual inverters are selected in such a way that the quarter-wave, half-wave, and three-phase symmetries are achieved for the dual-inverter drive despite unequal dc-link voltages for the constituent inverters. It is also shown that one of the two PWM techniques, called the proportional-duty SVPWM, results in a better spectral performance and lower switching power loss in the overall dual-inverter system compared to the equal-duty SVPWM. [ABSTRACT FROM PUBLISHER]

This paper presents a control strategy for a doubly fed induction generator (DFIG) using an indirect matrix converter, which consists of an input side matrix converter and an output side voltage source converter (VSC). The capability of the input converter to generate different “virtual dc link” voltage levels is exploited. The commutation of the VSI with reduced voltage is illustrated for operating points where the output voltage demand is low without any deterioration of the current control performance. The proposed method leads to a reduction in the commutation losses in the output converter and reduced common-mode voltage. For the input converter, soft switching commutation is obtained by synchronizing the input and output converter pulsewidth-modulation patterns. This modulation strategy is particularly applicable in DFIG applications because the required rotor voltage decreases when the DFIG speed is close to the synchronous speed. The complete control strategy is experimentally validated using a 2-kW rig. [ABSTRACT FROM AUTHOR]

A five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter is an arrangement of a three-level ANPC converter and a two-level cell. In this paper, a control strategy is proposed to regulate the voltage across the FCs at their respective reference voltage levels by swapping the switching patterns of the switches based on the polarity of the output current, the polarity of the FC voltage, and the polarity of the fundamental line-to-neutral voltage under selective harmonic elimination pulsewidth modulation. The voltage across the FCs and the dc-link capacitors are simultaneously controlled at their reference voltage levels. The proposed control strategy is applied using power system computer aided design/electromagnetic transients including dc on a static synchronous compensator operating under a power-factor-correction mode to verify its performance. Experimental results are also presented for low and high number of angles per quarter period using a low-power laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, a new three-level (3L) converter is presented. It is called 3L Vienna neutral-point-clamped (3L-VNPC) converter and consists of two stacked high-frequency (HF) commutation cells working with a shared power device. The HF cells are connected to a single-phase switched bridge controlled at low frequency. The 3L-VNPC topology is extended to 3L active VNPC (3L-AVNPC) concept, which is generalized for five levels (5L) and N odd voltage levels (N \L). The proposed multilevel converters can be seen as two cascaded voltage stages. The high-voltage stage is specific to the single-phase switched bridge, while the low-voltage (LV) stage corresponds to the stacked HF cells with shared power devices. The new concept AVNPC is a useful and suitable solution for medium-voltage applications, where small modulation index (M) is as crucial as large M. The analyses of the new converters are verified by simulations both for 3L and for 5L topologies, and their features are generalized for N\L. Experimental results for single-phase 3L-AVNPC converter on an LV test bench are also provided to validate the proper operation of the new concept. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to analyze carrier-based discontinuous pulse width modulation (DPWM) method for multilevel inverters. The separation of the offset into the main and additional components shows the use for analyzing PWM control characteristics of multilevel inverters. The results are then applied to propose a novel minimized loss DPWM method by varying the offset depending on peak values of three-phase load currents. As results of avoiding commutations at high currents, the switching loss can be reduced. The proposed method is theoretically analyzed and verified by experimental results. [ABSTRACT FROM AUTHOR]

This paper presents direct digital technique-generalized discontinuous pulse width modulation (PWM)—a new implementation method for an optimal discontinuous PWM (DPWM) in terms of switching losses of the inverter on an embedded system. At each sampling period, an optimal choice is done in order to clamp one of the three half-bridges. Its advantages compared to classic ones (DPWM) are as follows: needless to know the load power factor, operational under steady-state and dynamic operating conditions, and low computation time. The proposed algorithm is then verified by simulation. Experimental results, based on a resistance–inductance load and a starter-generator application, are provided to show its effectiveness. [ABSTRACT FROM AUTHOR]

With regard to a five-level inverter comprising flying-capacitor asymmetric H-bridge, the impact on the capacitor voltage under conventional modulation approach is analyzed. Since it is sensitive to the fundamental period and the load current, it may introduce undesired low-order harmonics into the output voltage and may even break down the power switches due to the considerable fluctuation of the flying-capacitor voltage. Thus, this paper proposes a novel pulsewidth-modulation scheme with the positive and negative cross carriers, which controls the flying-capacitor voltage by utilizing the redundant switching states of the output voltages. Three modes of precharging the flying capacitor without extra equipments are presented. Moreover, the capacitance of the flying capacitor and the switching frequency of the power switches can be chosen according to the allowable fluctuation of the flying-capacitor voltage and the load current. In order to remove the overlapping of the level layers, the optimization of the line-to-line voltage waveform is proposed to synthesize the reference vector with the “nearest three-vector” approach. The theory is supported by the experimental results from the prototype. [ABSTRACT FROM AUTHOR]

The multilevel multiphase technology combines the benefits of multilevel converters and multiphase machines. Recently, a new multilevel multiphase space vector pulsewidth modulation algorithm that is valid for any number of levels and phases was developed. In this paper, a generic digital VHDL module for such an algorithm is presented. This module is parameterizable in relation to the number of levels, the number of phases, and the number of bits of fractional part of the reference vector. It is also technology independent, reusable, and modular. This circuit has been tested by implementation in a field-programmable gate array, with the goal of a balance of speed and area optimization. It was tested by using a five-level five-phase inverter feeding an induction motor. [ABSTRACT FROM AUTHOR]

Multilevel inverters introduce harmonics to the network besides their remarkable advantages. Total harmonic distortion (THD) is one of the most important indexes to evaluate the harmonic contents of waveforms. The conventional method of line-voltage THD calculation gives approximate answers, because high-order harmonics are ignored. In this paper, an analytical algebraic method based on formulating the line-voltage THD of multilevel inverters with unequal dc sources is presented. This method, which is general and applicable to each number of switching angles, is implemented to a five-level inverter with staircase waveform as a case study. The implementing process of this method can be easily repeated for each number of levels. The accuracy of the proposed method is illustrated in comparison with the approximate method. Some advantages of the extracted formulas of line-voltage THD are simplicity and rapidity in calculations, considering all harmonics and the possibility of finding optimal switching angles analytically. Experimental results are presented to validate the theory. [ABSTRACT FROM PUBLISHER]

This paper presents a flyback switch-mode rectifier (SMR) with spread harmonic spectrum. The SMR switching control is conducted by a charge-regulated pulsewidth modulation (PWM) scheme with constant turn-on period. The inherently stable discontinuous conduction mode operation is preserved to yield good line drawn power quality. In voltage loop, a quantitatively designed PI feedback controller is augmented with a robust error cancellation control scheme. Further improved dc output voltage regulation and input power quality performances are achieved under varied operating conditions. In spread harmonic spectrum control, the harmonic spectral properties of the developed flyback SMR are first analyzed. Then, the dedicated random switching scheme is developed to let its switch current harmonic spectrum be dispersedly distributed. In the proposed random switching scheme, the PWM turn-off period is modulated using 1-b binary sequence, pseudo random binary sequence, and 4-b binary sequences. Under randomized harmonic spectrum, the SMR control performances are not sacrificed. [ABSTRACT FROM PUBLISHER]

This paper presents a pulsewidth modulation (PWM) algorithm for a three-phase ac–dc rectifier, where the third and fifth harmonics are indicated in the input phase voltages. A mathematical analysis, which includes this voltage harmonic's components, shows that the unity input displacement factor (IDF) can be reached by appropriate evaluation of duty-cycle functions. A PWM algorithm is proposed based on this developed theoretical achievement. This approach enables current sensorless unity IDF rectification. The PWM algorithm is investigated theoretically and verified by simulations and experiment. [ABSTRACT FROM PUBLISHER]

The operation of switch-mode converters results in electromagnetic noise propagating throughout the power electronic system. Pulsewidth modulation (PWM) strategies with fixed switching frequency generate harmonics in the spectra of converter voltages and currents. Random PWM techniques allow the elimination of the harmonics, resulting in a continuous spectrum of noise, i.e., a spectrum retaining all frequency components. As a next step in advanced spectral shaping, a method presented in this paper produces spectral nulls at selected frequencies. This allows the carving of communication channels in the noise and the removal of spectral power at frequencies potentially harmful for the system. The theoretical analysis, computer simulations, implementation details, and experimental results are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase seven-level inverter for grid-connected photovoltaic systems, with a novel pulsewidth-modulated (PWM) control scheme. Three reference signals that are identical to each other with an offset that is equivalent to the amplitude of the triangular carrier signal were used to generate the PWM signals. The inverter is capable of producing seven levels of output-voltage levels (Vdc, 2Vdc/3, Vdc/3, 0, -Vdc, -2Vdc/3, -Vdc/3) from the dc supply voltage. A digital proportional–integral current-control algorithm was implemented in a TMS320F2812 DSP to keep the current injected into the grid sinusoidal. The proposed system was verified through simulation and implemented in a prototype. [ABSTRACT FROM AUTHOR]

In this paper, a novel three-phase soft-switching inverter is presented. The inverter-switch turn on and turn off are performed under zero-voltage switching condition. This inverter has only one auxiliary switch, which is also soft switched. Having one auxiliary switch simplifies the control circuit considerably. The proposed inverter is analyzed, and its operating modes are explained in details. The design considerations of the proposed inverter are presented. The experimental results of the prototype inverter confirm the theoretical analysis. [ABSTRACT FROM AUTHOR]

Motivated by the method to analyze the impact of dead time in hard-switching converters, this paper, for the first time, analyzes the impact of zero-voltage notches on the outputs of soft-switching pulsewidth modulation (PWM) converters. It proves that the output distortion of soft-switching converters due to their deviation voltage is independent of the direction of their output current. Hence, their compensation strategies require no sensor to detect the current's direction, which is required by dead-time compensation methods in hard-switching converters. A simple yet effective compensation algorithm is presented for soft-switching converters. The analysis result and effectiveness of the proposed algorithm are experimentally verified via a three-phase inverter that represents an important class of converters. [ABSTRACT FROM AUTHOR]

Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]

This paper proposes a family of spread-spectrum schemes, several of which are new, for conducted-noise reduction in dc–dc converters. The schemes use three randomized parameters to generate the switching signals: carrier frequency, duty ratio, and pulse position. The increasing performance and cost reduction of field-programmable gate array (FPGA) technology have made the application of these schemes possible in this field. A theoretical framework for a general representative scheme is provided. Then, the proposed schemes are designed and implemented using an FPGA-based controller. Furthermore, the effect of using the proposed controller on common-mode, differential-mode, and total conducted-noise characteristics of the dc–dc converter is experimentally investigated. In addition, the three randomization parameters are swept to determine the values that best achieve the conducted-noise spectrum spread. All studied cases are designed, implemented, and experimentally investigated. Then, the conducted-noise spectra are compared. The experimental results show that the use of the proposed controller with the determined randomization values significantly improves the conducted-noise spectrum and effectively reduces the noise peaks at both high- and low-frequency ranges. [ABSTRACT FROM AUTHOR]

Multilevel cascaded H-bridge converters have found industrial application in the medium-voltage high-power range. In this paper, a generalized modulation technique for this type of converter based on a multidimensional control region is presented. Using the multidimensional control region, it is shown that all previous modulation techniques are particularized versions of the proposed method. Several possible solutions to develop a specific implementation of the modulation method are addressed in order to show the potential possibilities and the flexibility of the proposed technique. In addition, a feedforward version of this technique is also introduced to determine the switching sequence and the switching times, avoiding low harmonic distortion with unbalanced dc voltages. Experimental results are shown in order to validate the proposed concepts. [ABSTRACT FROM AUTHOR]

The focus of this paper is the study of direct alternating-current (ac)–ac converters, beginning by buck, half-bridge, full-bridge, and push–pull converters. From the basic converters, we apply a simple methodology to make the use of switches in commercial configurations possible. Following that, eight voltage restorers supplied either on the line side or on the load side are proposed. A comparative evaluation of these topologies concerning implementation, complexity, and component effort is presented. It is notable that some of the studied topologies are known in the literature and others are new. For one of the presented topologies, the design of a 3-kVA voltage restorer is developed, and experimental results are shown, certifying the correct operation of the drive strategy used. [ABSTRACT FROM AUTHOR]

In this paper, a three-level three-leg ac–dc–ac converter for single-phase applications is investigated. The operating principles and control strategies for the topology are presented. It is shown that dc-link voltage balancing and its reduction are important objectives in the system design. The proposed pulsewidth modulation (PWM) strategy permits the dc-link capacitor voltage balance and also its reduction. The three-level converter is compared to the two-level converter in terms of rms switch currents, harmonic distortion, losses, and costs. Experimental and simulation results are presented to validate the theoretical studies. [ABSTRACT FROM PUBLISHER]

Half-cycle symmetry selective-harmonic-elimination pulsewidth-modulation (SHE-PWM) problems may have a large number of valid solutions, which are beneficial to the optimization design. This paper proposes a novel generalized formulation of half-cycle symmetry SHE-PWM problems for multilevel inverters. The advantages of the proposed formulation include simplicity in format, flexibility in PWMwaveforms, and a broad solution space. A method to obtain initial values for the SHE-PWM equations according to the reference modulation index M and the initial phase angle of output fundamental voltage is proposed and investigated thoroughly. Take a five-level inverter with M = 0.75 as an example; six sets of solutions for two typical initial phase angles of 0°? and 90°? are presented. Simulations and experiments are carried out. It is demonstrated that the experimental results agree well with simulated ones, which proves the validity and practicability of the new method proposed. [ABSTRACT FROM AUTHOR]