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In this work, a multilevel 42-sided polygonal space vector structure for suppression of lower order harmonics for open-end induction motor (OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an OEIM from either side. The main inverter fed with a single dc-link providing active power for motoring operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the dc-link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures, are combined with multilevel inverter topology. This offers various advantages like multilevel operation with low inverter switching for the main power delivery inverter and harmonic suppression throughout the modulation range. The low switching frequency primary inverter generates harmonics of the order $6*k \pm 1$ , where $k = 1, 2, 3,{\ldots }$. The harmonics are suppressed by the capacitor-fed secondary inverter, which supplies only reactive power for suppression of lower order harmonics in motor phase voltage. Use of a single dc-link facilitates four-quadrant operation of the inverter. The proposed scheme is validated for steady-state and dynamic performance by experimental results. [ABSTRACT FROM AUTHOR]

Conventional two-level as well as multilevel voltage-source-inverter topologies with a hexagonal voltage-space vector structure generate low-order harmonics in the machine terminal voltages when operated beyond the linear modulation range in variable speed drive application. Progressing from hexagonal to a higher sided polygonal voltage-space-vector structure (VSVS) suppresses significant low-order harmonics throughout the modulation range. In addition, the linear modulation range will also be enhanced very near to the base speed. In this paper, for the first time, the generation of a multilevel 24-sided VSVS using a single dc source for induction-motor drives is proposed. A cascaded topology with a dc-source-fed flying-capacitor inverter and two low-voltage capacitor-fed H-bridge cells forms the power circuit. The features and advantages of the proposed scheme are validated through experimental results and discussions. [ABSTRACT FROM AUTHOR]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency—making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values ( $v_\alpha$ and $v_\beta$) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth- and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept. [ABSTRACT FROM PUBLISHER]

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high $6n\pm 1$, n = \odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress $6n\pm 1$, n = \odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. [ABSTRACT FROM PUBLISHER]

In this article, a multilevel inverter scheme to generate a 30-sided space vector structure (SVS) with congruent triangles is proposed. The 30-sided SVS eliminates all the lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The proposed scheme is implemented using a single dc-link on an open-end induction motor (OEIM). The OEIM is fed with primary inverter from one end and secondary inverter from the other end. Primary inverter is fed from an active dc-link and supplies all the required active power for the scheme. Secondary inverter is a capacitor fed inverter, which acts as the switched capacitive filter. In this work, a simple algorithm is proposed, which calculates the timings required for a 2-level 30-sided SVS from sampled reference voltages. The algorithm requires only simple operations such as addition, multiplication, and comparisons. From the obtained timing values, the space vector location of three nearest multilevel 30-sided vectors and its time duration can be identified. The feasibility of the proposed scheme is proved by experimental results. [ABSTRACT FROM AUTHOR]

This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme. [ABSTRACT FROM AUTHOR]

In this work, a ten-level inverter scheme is presented to extend the linear modulation range (LMR) by using a unique space vector pulsewidth modulation (SVPWM) technique, such that no lower order harmonics (such as 5th, 7th, 11th, and 13th, etc.) are present in the phase voltage as compared to six-step mode operation. The proposed scheme can increase the peak phase fundamental voltage of the inverter from 0.577 to $0.637 V_{dc}$ (maximum possible peak phase fundamental voltage of a conventional hexagonal space vector structure (SVS) voltage source inverters while operating in six-step mode), irrespective of the load power factor (p.f), where $V_{dc}$ is the dc link voltage of the inverter. The ten-level inverter structure is formed using a two-level inverter and an H-bridge (HB) in cascade from one end and a floating capacitor-based two-level inverter cascaded with an HB from the other end to drive an open-end winding induction motor (OEWIM). All the HB capacitor voltages are balanced by using space vector redundancy. The claim of balancing the capacitor voltages throughout the whole modulation range is verified experimentally in this article. Experimental results at different steady-state and transient conditions are shown to validate the proposed inverter scheme’s efficacy in increasing the LMR. [ABSTRACT FROM AUTHOR]

A voltage source inverter generating a polygonal voltage space vector structure (SVS) having 117- concentric 30-sided polygons of different radii are proposed. Modulation using a 30-sided SVS eliminates lower order harmonics till 25th order from motor phase voltage. The proposed scheme combines the advantages of a 30-sided SVS with that of a multilevel inverter. The topology consists of two cascaded five-level inverters feeding from either end of the open-end induction motor stator windings. One of the cascaded five-level inverter is connected to an active dc source and delivers the required active power for the scheme, while the other is capacitor fed and acts as a switched capacitive filter. In this article, nonaligned 30-sided polygons, i.e., regular 30-sided polygons that are not symmetric with respect to $\alpha$ and $\beta$ axis are also considered for inverter operation. The harmonic analysis of such nonaligned 30-sided polygons is investigated in this article. Nearest level switching is employed throughout the modulation range, enabling further reduction of switching loss in the system. Extensive hardware experimentations are carried out to validate the proposed scheme and the results are included in the article. [ABSTRACT FROM AUTHOR]

In this article, a method is proposed for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor drive. A five-level inverter with a single dc source is used for the proposed scheme. Using this method, linear pulsewidth modulation (PWM) operation of the inverter can be achieved till peak phase fundamental voltage of 0.637 Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed five-level inverter scheme is realized by cascading a two-level inverter with a capacitor fed H-bridge, feeding open-end induction motor drive from one end and a capacitor fed two-level inverter from the other end. The proposed scheme uses space vector redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal five-level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme [ABSTRACT FROM AUTHOR]

A multilevel dodecagonal voltage space vector generation scheme for variable-speed drive applications with single-dc-link operation requires a large value of capacitance for cascaded H-bridge (CHB) filters, when operated at lower speeds. In existing schemes, the multilevel dodecagonal structure is obtained by cascading a flying capacitor inverter with a CHB. In this paper, a new scheme has been proposed to minimize the capacitance requirement for full speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimize the selection of vector redundancies among the CHBs in order to minimize the voltage ripple of the floating capacitors. The proposed algorithm considers instantaneous capacitor voltages and phase currents for optimal selection of vector redundancies. A mathematical model for capacitor voltage deviation is presented, and the effectiveness of the proposed algorithm is verified in both the simulation and the experiment. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique. [ABSTRACT FROM PUBLISHER]