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Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach. [ABSTRACT FROM AUTHOR]

Three-phase voltage-source inverters typically feature a significant amount of dc energy storage to maintain a stiff dc bus. In these cases, the dc-link capacitor is sized to store enough energy to maintain several tens of cycles of ac output at the rated power. In this paper, we propose to reduce the size of the dc-link capacitor dramatically to store enough energy to provide just one high-frequency switching cycle of the ac output power. The dc bus is no longer stiff, and hence, classical sinusoidal pulse-width modulation cannot be used. However, the stored energy modulation (SEM) proposed herein synthesizes high-quality sinusoidal output voltage waveforms, even with such tiny dc-link capacitors. In SEM, the switching intervals of the interconnecting switches are carefully determined nonlinear functions of various operating parameters such as reactive component sizing, switching frequency, load levels, etc. This paper presents the analytical and detailed design development of the SEM approach along with circuit simulation, experimental results, and comparative evaluation of a dc-to-three-phase system example. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper reports an elegant approach to address two major challenges of transformerless grid-connected microinverters, common-mode earth leakage current and double-frequency power pulsation across the photovoltaic (PV) terminal. The proposed solution uses an embedded decoupling capacitor in a doubly grounded boost–buck ( $\acute{\mathrm{C}}$ uk) derived topology. An intelligent switching scheme ensures that a large swing of the decoupling capacitor voltage is easily accommodated. Thus, film capacitors can be used instead of electrolytic capacitors, which helps increase equipment lifetime. Details of circuit operation are provided along with dynamic modeling and controller design for close-loop operation. Simulation and experimental results are presented for performance validation of the microinverter. [ABSTRACT FROM AUTHOR]

This paper proposes a new high-gain soft-switching dc–dc topology based on a switched inductor boost converter (SIBC). A conventional SIBC as a high gain boost topology has the issues of high conduction loss in switching diodes and high switching loss in the main switches. Also, it has severe electromagnetic interference (EMI) issue due to high-frequency ringing formed by parasitic inductance and diode junction capacitors. The new topology is derived with the objective of achieving zero voltage switching (ZVS) turn on of the main switch. Instead of adding extra active clamp zero voltage transition (ZVT) path at the switching node, the proposed topology augments the auxiliary ZVT path to the switching diode path. This is achieved by replacing the switching diodes with synchronous switches. The new topology can achieve soft switching for all the switches and alleviate the EMI issue. All the diodes achieve zero current switching (ZCS) turn off without reverse recovery. Auxiliary switches have ZCS turn on and ZVS turn off, and the main switches have ZVS turn on. The soft-switching SIBC also reduces the conduction loss in the switching diodes. A numerical simulation in PLECS and a prototype hardware are built corresponding to a micro-inverter application with 100 kHz switching frequency. Peak power conversion efficiency of 94.76% is achieved in the hardware prototype with Si devices. [ABSTRACT FROM PUBLISHER]

This paper proposes a new nine-level inverter for medium- and high-power applications. The proposed topology comprises of a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line frequency are appended across the dc link of the 3L ANPC structure. Compared with conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of the resulting root mean square output voltage. This amelioration is achieved while preserving the standard 3L ANPC and H-bridge structures with minimum topological modification. A simple logic-gate-based voltage balancing scheme is developed to regulate the FC voltage. The proposed voltage balancing method is independent of load power factor, inverter modulation index, and can balance the voltage across FC instantaneously. The step-by-step formulation of logical expressions for the generation of gating pulses is deliberated in detail and can be generalized for any $n$-level inverter. Further, simulation results as well as the experimental measurements obtained from the laboratory prototype are presented to validate the effectiveness and practicability of the proposed configuration. Finally, the notable merits of the proposed inverter over the prior art topologies is established through a comprehensive comparative study. [ABSTRACT FROM PUBLISHER]

Transformer-less grid-connected photovoltaic (PV) systems face the challenge of keeping low leakage current due to their nonisolation configurations. To better attenuate the leakage current in the single-phase systems, a few neutral-point-clamped (NPC) topologies have been proposed. This paper further proposes an active NPC method by only employing one additional switch to connect the midpoint dc link and the freewheeling circuit of traditional single-phase PV inverters. After exploring the operational principles of freewheeling circuits, the construction method and the implementation of active NPC circuits in transformer-less single-phase inverters are elaborated in detail. Since only the leakage current flows through the additional NPC switch, the presented single-phase NPC inverters could still maintain the high operational efficiency with the further attenuated leakage current. The experimental results verified the theoretical findings. [ABSTRACT FROM PUBLISHER]

In order to increase the output voltage levels and reduce the isolated dc sources, a symmetrical hybrid nine-level inverter for high-speed motor drive applications is presented in this paper. Each phase of this inverter is composed of a five-level dc/dc converter cell and an H-bridge cell. The dc/dc converter is operated at high frequency with low-voltage devices and the H-bridge is operated at fundamental frequency with high-voltage devices. The three phases are connected to a common dc-link and each drives an isolated winding of an open-winding motor. The operating principles and modulation method are introduced. A detailed analysis of the average currents through the flying capacitor and neutral point of the dc-link is presented and a capacitor voltage balancing method based on phase-shifted pulse-width modulation is proposed. Simulation and experimental results are presented to demonstrate the feasibility of this topology and control method. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology for a \text3-\phi three-level inverter with complete elimination of common-mode voltage (CMV). The proposed multilevel inverter (MLI) configuration is realized by modifying a T-structure \text3-\phi inverter. The proposed configuration is an optimized solution with respect to the pulse-width modulation strategy used for CMV elimination. The given three-level inverter structure uses only 16 power semiconductor switches, which is much lower than the existing configurations. A reduced number of power semiconductor devices results in a diminished number of driver circuits, less installation space, and low cost. Further, due to the complete elimination of CMV, the proposed MLI is free from issues such as electromagnetic interference and leakage current with a reduction in filter requirement. The presented topology is also compared with other existing topologies to prove its advantage. It is an optimized solution with respect to the dc bus voltage requirement and the total voltage rating of the devices or the components used in the system. Simulation and experimental results are presented to confirm the capability of the proposed MLI. [ABSTRACT FROM AUTHOR]

Three-phase inverters in uninterrupted power supply, electric vehicles, and hybrid electric vehicles use an intermediate dc-link electrolytic capacitor, which has reliability issues and is one prominent cause of inverter failure and limited life. The large volume of an electrolytic capacitor increases the size and cost of the system. Recent research on electrolytic capacitorless inverters using six-pulse modulation technique along with high-frequency power conversion has attempted to address this issue. However, closed-loop operation and control has some issues due to capacitorless dc-link. In this paper, closed-loop operation, design, and implementation of an electrolytic capacitorless inverter is presented. A proof-of-concept 1-kW hardware prototype has been built and tested in a laboratory under different loading conditions. In total, 98% rated efficiency of the inverter is obtained with total harmonic distortion within 2%. Transient results during start-up and load change are smooth, demonstrating safe operation of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a novel multilevel dc–ac inverter is proposed. The proposed multilevel inverter generates seven-level ac output voltage with the appropriate gate signals’ design. Also, the low-pass filter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multilevel inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. Finally, a laboratory prototype multilevel inverter with 400-V input voltage and output 220\ \textV\text{rms}/2\,{\text{kW}} is implemented. The multilevel inverter is controlled with sinusoidal pulse-width modulation (SPWM) by TMS320LF2407 digital signal processor (DSP). Experimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped converter is a recently introduced topology that offers low harmonic distortion and a high output voltage. In addition to a neutral point potential in the dc link, this topology features, in each phase, a flying phase capacitor. Balancing these four internal converter voltages around their references while providing fast torque and/or current control for the machine is an intrinsically challenging control problem. Model predictive direct torque control (DTC) (MPDTC) is an ideal control methodology to address this problem. It is shown, in this paper, how MPDTC, originally developed for three-level inverters, can be adapted to this new five-level topology. Compared to DTC, the performance results of MPDTC are very promising—for the same switching frequency, the harmonic distortions of the stator currents and the torque can be more than halved. At the same time, the very fast torque response of DTC is maintained. [ABSTRACT FROM PUBLISHER]