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A multi-level boost topology based on a flying capacitor is compared in this work with the hybrid, multi-level, partial power processing topology already presented in the literature for use as a highly efficient and compact dc/dc stage in 1500-V, two-stage, grid-connected PV systems. Different variations of the resonant stage of the hybrid topology are analyzed and compared in terms of losses, volume and complexity. Full multivariable optimization is conducted for the multi-level boost topology with different number of levels and for all the analyzed variations of the resonant stage of the hybrid topology. Appropriately rated new classes of 650-V and 900-V WBG devices are included in the optimization algorithm. It is concluded that due to the dominant conduction losses and gap in the voltage rating of the commercially available WBG devices between 650V and 200V, increase of the number of levels over 4 leads to the deteriorated loss and volume performances. All the analysis related to the resonant stage of the hybrid topology is confirmed by detailed and comprehensive measurements of two prototypes of 4kW of nominal and 7kW of maximal power. Additionally, all the loss models applied in the optimization algorithms presented in this paper are confirmed by detailed measurements, thermal calibration and finite element thermal simulations of the wide bandgap devices and inductor designs employed in this work. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique. [ABSTRACT FROM AUTHOR]

This paper deals with a multilevel ac–ac double conversion system that uses the intercell transformer (ICT) for applications which include generating systems and the interfacing of renewable energy sources with the utility grids. Each phase of the proposed configuration is formed through the ICT interleaving operation of two multilevel 5-level E-type legs to achieve the 3-phase 5-level back-to-back E-type converter (3Φ5L BTB E-type converter). The analytical procedure to select the inductance and capacitance values of both the input and output filters is described in the paper. Furthermore, the design and implementation of the input/output ICTs and inductors is discussed. The simulation and the experimental results on the 20-kVA interleaved 3Φ5L BTB E-type converter prototype are presented to validate the proposed analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a soft-switched modulation technique with synchronous rectification for an isolated single-stage single-phase matrix-type dc–ac converter. The dc side consists of a full bridge inverter, and the ac side is a 2×2 matrix converter-based cycloconverter. The proposed unipolar modulation strategy provides zero current switching/zero voltage switching (ZVS) for the ac side devices and ZVS-on for the dc side devices. It also allows natural commutation of the current flowing through the secondary side leakage inductor of the isolation transformer and the grid inductor during unity power factor (UPF) condition, thus eliminates the requirement of snubber circuit. An improved soft-switched flyback-based regenerative snubber circuit is also presented for non-UPF operation. Proposed snubber circuit recycles the energy stored in the snubber capacitors in every switching cycle. A guideline to design snubber circuit along with a comparative study is discussed in this paper. Performance of the proposed hybrid modulation technique is evaluated in an SiC mosfet based 1.2-kW dc–ac converter prototype. A detailed analysis of the converter performance has been presented in this paper considering the circuit non-idealities. [ABSTRACT FROM AUTHOR]

The number of applicable carrier-based pulsewidth modulation (PWM) patterns increases with the growth of output levels in scalable multilevel topologies, such as active-neutral-point-clamped (ANPC) converters. Therefore, it is hard to optimize PWM for such topology, especially with large output levels. In this paper, a simplified and modular carrier-based PWM design approach for multilevel ANPC converters is proposed. Inspired by the decomposition theory, the topology decomposition is introduced in this paper to decompose an N-level ANPC converter into low-level subtopologies. Then, the complete set of applicable PWM patterns is derived based on ANPC operation principles, which makes it possible to optimize the performance based on the various requirements in applications. Meanwhile, the carrier-based PWM is implemented through the utilization of subtopologies with low-level modulation schemes, such that the design process of carrier-based PWM is greatly simplified and modularly realized. Both the complete PWM patterns and PWM design examples with experimental results of several ANPC converters are provided to show the feasibility and modularity of the proposed method. [ABSTRACT FROM AUTHOR]

The use of electronic equipment and other dc-compatible appliances in homes and offices is increasing at a very fast rate, as well as the distributed generation of energy. These two statements will most likely trigger, in a near future, the adoption of district-scale dc grids, connecting dc microgeneration plants and consumers, in an effort to cut the number of conversion steps required to deliver power to dc appliances. DC–DC converters will be fundamental in these systems, allowing the establishment of several voltage levels. The reliability of these converters plays a critical role, ensuring service continuity of the loads connected to them. With the increment of reliability in mind, this paper proposes a simple yet effective open-circuit fault diagnostic method suitable for interleaved dc–dc boost converters, but equally functional for other dc–dc converter topologies. The improvements introduced in this paper greatly simplify the diagnostic action, while making the correct diagnostic of faults independent of the switching duty cycle. Moreover, an alternative reconfiguration scheme is proposed to mitigate the adverse impacts of such faults. To prove the effectiveness of these strategies, a three-phase interleaved boost converter prototype was used in the experiments. [ABSTRACT FROM AUTHOR]

Multioutput converters with single input source are currently studied as an alternative to conventional dc–dc topologies in order to improve power density in low-power multiload applications. This paper reviews three different ways in which a boost topology can be customized to supply multiple outputs. The first way uses a charge-sharing approach using individual switches to distribute inductor energy to different capacitors. The second method of creating a multiport converter (MPC) combines two converters with similar front end to generate two outputs using only one controlled switch. Using this method, a boost converter can be combined with single–ended primary–inductor converter (SEPIC), Cuk, and current source converter topologies. The third method uses time multiplexing of switches to produce two regulated ports and is referred to as switched-boost action. This method uses relatively less number of switches and allows regulation and control of all the outputs. Practical utility of switched-boost action based MPC is reported in this paper. This switched-boost MPC is applied to a renewable power converter system to interface a solar panel, a battery, and home loads to produce a 12-V and a 48-V bus. The 12-V bus is interfaced to battery and capable of optimally charging the battery in constant current–constant voltage (CC-CV) mode. The converter is demonstrated to operate with solar panel as it supplies a 12-V battery and a 48-V load bus. When the solar power is not available, the converter automatically goes into a mode in which the 12-V battery supplies the loads on the 48-V bus. [ABSTRACT FROM AUTHOR]

This paper proposes a medium-frequency (MF) solid-state transformer (SST) based grid interface for high-power multipulse rectifiers. In the proposed approach, the low-frequency ac (grid) voltage is transformed to MF voltage via front-end converters. The three single-phase MF outputs from these converters are fed to the primary side of a three-phase, five-limb multiwinding isolation transformer (or alternately three one-phase transformers). The secondary side windings from the transformer are configured in a certain “zig-zag” arrangement, which are connected to the inputs of three-phase diode rectifier modules as in a typical multipulse system. The proposed topology can better than double the power density by reducing volume (or weight) of the required front-end isolation transformer while maintaining the same input current quality as a conventional low-frequency transformer based approach. Usage of an open-loop square wave pulse width modulation for the front-end converters makes this approach simple to implement. This paper explains the proposed concept taking an adjustable speed drive application's perspective using modeling, simulation, and experimental results from a scaled down laboratory prototype. [ABSTRACT FROM AUTHOR]

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

Finite state model predictive control (MPC) has been recently applied to several converter topologies, as it can provide many advantages over other MPC techniques. The advantages of MPC include fast dynamics, multitarget control capability, and relatively easy implementation on digital control platforms. However, its inherent variable switching frequency and lower steady-state waveform quality with respect to standard control, which includes an appropriate modulation technique, represent a limitation to its applicability. Modulated model predictive control (M2 PC) combines all the advantages of MPC with the fixed switching frequency characteristic of pulse-width modulation algorithms. The work presented in this paper focuses on the indirect matrix converter (IMC), where the tight coupling between rectifier stage and inverter stage has to be taken into account in the M2PC design. This paper proposes an M2PC solution, suitable for IMC, with a switching pattern that emulates the desired waveform quality features of space vector modulation for matrix converters. The switching sequences of the rectifier stage and inverter stage are rearranged in order to always achieve zero-current switching on the rectifier stage, thus simplifying the current commutation strategy. [ABSTRACT FROM AUTHOR]

In this paper, it is described how the circulating current flows between inverters that have isolated dc link such as cascaded H-bridge (CHB) topology when they are operating in parallel. In this case, zero sequence circulating current, which normally flows through shared dc link, cannot flow between inverters in parallel. However, circulating current is provoked by asynchronous switching instant of devices, difference of dc-link voltages of parallel inverters, and unbalanced impedance. The circulating current should be suppressed by a sharing inductor that is inserted between inverters. Generally, all of the inverters should synthesize the same output voltage reference for load current control to minimize the size of this sharing reactor. However, this conventional method cannot guarantee diminishing circulating current in the transient state and even in the steady state. In this paper, in order to reduce sharing reactance, after deriving circulating current model from general case of n-parallel operation, circulating current control method is devised based on the model. This proposed algorithm is applied to active front end five-level-CHB inverter system for medium voltage drive. Simulation and experimental results are provided to verify the effectiveness of the proposed control scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a new inverter topology based on the active neutral-point-clamped (ANPC) converter with capability to integrate one energy storage system (ESS) per inverter leg with an independent state of charge control, so that each inverter leg has two dc ports and one ac port. The primary dc port is common to all inverter legs and it is connected to the main power source. The secondary dc port is suitable for ESS connection because of its two-quadrant operation, with bidirectional current capability, so that the ESS can be charged and discharged with regulated current. Integration of a secondary dc port with independent control also allows the use of different ESS technologies for each inverter leg to compose a hybrid ESS. Redundant switching states of the proposed structure are used to balance the energy exchanged between the secondary dc port and the dc bus capacitors. Theoretical propositions were experimentally validated through a 1-kW single-phase inverter with a secondary dc port connected to a 230-V ESS and ac port connected to an LC filter feeding a linear load. Low total harmonic distortion (THD) sinusoidal current is generated at the ac port while charging or discharging the ESS with a constant current. [ABSTRACT FROM AUTHOR]

Transformerless inverters are getting popular in distributed photovoltaic power generation (PVPG) system due to its light weight, low cost, and higher efficiency in power conversion. However, the production of leakage current leads to severe electromagnetic interference and operational insecurity, which declines the reliability and efficiency of the overall system. Besides that many of the topologies have been addressed with real power injection capabilities in the literature. Therefore, in this paper, an improved hybrid-bridge (IH-B) inverter for transformerless PVPG system is proposed with 1) reduced leakage current by abolishing the fluctuations in common-mode voltage (CMV) due to switch junction capacitances and 2) reactive power capability with a modified sinusoidal pulsewidth modulation technique. This topology is constructed with the combination of bidirectional clamping branch and hybrid-bridge (H-B) inverter topology to maintain CMV at half of the dc-link voltage and ensure better quality of output waveforms at different power factors of the grid. Further, MATLAB simulation results of the IH-B and H-B topologies are presented and compared to prove the potential benefits of the proposed topology. Finally, a 500W prototype model is built and tested to validate the effectiveness of the IH-B topology in reduction of leakage current and reactive power capability. [ABSTRACT FROM AUTHOR]

Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

This paper introduces a new zero current switching topology for parallel balancing of serially connected batteries string. The main advantage of the balancing concept in this study is that energy is transferred only when the cells are unbalanced. As a result, the power losses are significantly reduced since no current circulates through the system when balanced. This has been enabled by a modification of an isolated series-resonant converter operating in a discontinuous conduction mode. A single transformer for two cells is used, as opposed to conventional isolated topologies that require a transformer per cell. The realization is simple and sensorless. Experimental results have been obtained by a prototype of two modules balancing four series-connected batteries. [ABSTRACT FROM AUTHOR]

The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies. [ABSTRACT FROM AUTHOR]

Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach. [ABSTRACT FROM AUTHOR]

One of the recent trends in power electronics field is to achieve high efficiency and compact size by using wide bandgap power devices such as silicon carbide (SiC) or gallium nitride switches. This paper compares the efficiency, the motor terminal voltage quality (dv/dt), and the common mode current of the SiC-based variable frequency drives (VFDs) according to the inverter topologies with and without the output filters. For this purpose, both the 2-level (2L) and 3-level (3L) topologies with SiC devices are built and tested. Here, the well-known 2L half-bridge inverter is compared with the well-known 3L T-type neutral point clamped inverter. A dv/dt filter and a sine wave filter have been discussed to satisfy the National Electrical Manufacturers Association standards as well. The experiments have been carried out with a 380-V/60-Hz, 3.7-kW induction motor and the custom designed power stages. Additionally, the experiments with both a 3-m and a 50-m cable length between the VFD and the induction motor are performed and reported. [ABSTRACT FROM AUTHOR]

An improved bridgeless (BL) Cuk converter-based electric vehicle (EV) battery charger with high power factor and increased efficiency is designed and developed in this paper. It provides low cost and high-power-density-based charging solution for the EV. This charger incorporates less number of devices operating over one switching cycle, which reduces the additional conduction loss incurred by a diode bridge rectifier of the conventional charger. Hence, it improves the charger's efficiency. The added advantage of the proposed topology is that the unwanted capacitive coupling loop is removed, as well as the unwanted conduction through the body diode of the inactive switch in the previously developed BL Cuk converter is avoided. This significantly improves the charger's efficiency. For the constant current and constant voltage charging, the commands are synchronized by a flyback converter. The proposed charger draws a sinusoidal current from ac mains and the total harmonic distortion in the supply current is reduced to the limits specified by the IEC 61000-3-2 guidelines. The improved efficiency and power quality indices of the proposed charger are investigated to demonstrate its satisfactory charging operation at all operating conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a novel open-winding brushless doubly-fed reluctance generator (OW-BDFRG) with dual two-level converters in order to reduce the converter rating and switching frequency for large-scale wind turbine applications. The new converter topology is equivalent to a three-level converter directly connected to the control winding of typical BDFRG. The OW-BDFRG system with this topology structure requires lower converter rating and switching frequency, and has a more flexible control mode, better operation performance, and fault redundancy capability. For the OW-BDFRG, this paper also proposes a new control scheme combining direct power control (DPC) with sliding mode variable structure (SMVS) control to implement the power tracking. The voltage-vector switching table of DPC is redesigned according to the error signals of active and reactive powers of the power winding, as well as the sector location of control winding flux. The active and reactive powers of the OW-BDFRG can be directly decoupled and independently controlled by properly selecting the switching voltage vectors. The novelty of this paper lies in an OW-BDFRG topology driven by dual two-level converters to improve the system characteristics, and the use of SMVS control to improve the DPC accuracy and robustness to parameter variations. Finally, the effectiveness of the proposed system is verified through simulation and experimental studies. [ABSTRACT FROM AUTHOR]

The hybrid modular multilevel converter with cascaded full bridges (HMMC-CFB) is a recently proposed dc fault tolerant converter topology for high-power applications. It has a director part (DP) consisting of a series of connected half-bridge submodules, and a wave-shaping part (WSP) composed of a series of connected full-bridge submodules (FBSMs). The submodules in DP avoid high voltage stresses and improve synchronization between DP and WSP by slowing down the change rate of DP output voltage. This slowdown is achieved by using a trapezoidal reference signal for DP. The WSP attenuates the voltage harmonics produced by DP. However, the energy exchanged by WSP changes with modulation index, which may cause improper voltage regulation of the submodule capacitors. This paper proposes a new control technique to regulate the energy exchanged by WSP, which uses a variable slope trapezoidal reference signal of DP. To obtain this slope, the feedforward and feedback controllers are used. The feedforward controller gives the value of slope depending on the modulation index (mv) to keep the energy exchanged by WSP nearly equal to zero, whereas the losses and nonideality of the converter are taken care of by the feedback controller. This technique guarantees proper voltage regulation of the submodule capacitors for all modulation indices. The efficacy of the proposed technique is confirmed using simulations and experimentations. This paper also presents a circulating current suppressing controller for HMMC-CFB. The proposed control schemes and dc fault tolerant capability of HMMC-CFB are tested on a grid-connected model built in PSCAD. [ABSTRACT FROM AUTHOR]

Three-phase voltage-source inverters typically feature a significant amount of dc energy storage to maintain a stiff dc bus. In these cases, the dc-link capacitor is sized to store enough energy to maintain several tens of cycles of ac output at the rated power. In this paper, we propose to reduce the size of the dc-link capacitor dramatically to store enough energy to provide just one high-frequency switching cycle of the ac output power. The dc bus is no longer stiff, and hence, classical sinusoidal pulse-width modulation cannot be used. However, the stored energy modulation (SEM) proposed herein synthesizes high-quality sinusoidal output voltage waveforms, even with such tiny dc-link capacitors. In SEM, the switching intervals of the interconnecting switches are carefully determined nonlinear functions of various operating parameters such as reactive component sizing, switching frequency, load levels, etc. This paper presents the analytical and detailed design development of the SEM approach along with circuit simulation, experimental results, and comparative evaluation of a dc-to-three-phase system example. [ABSTRACT FROM PUBLISHER]

This paper proposes a multilevel series compensator (MSC) to deal with voltage sags/swells, harmonic compensation, or reactive power compensation. Such a device can be considered as a dynamic voltage restorer or a series active power filter (Series-APF). The MSC can improve the power quality of loads located in stiff systems. The configuration is based on three-phase bridge (TPB) converters connected by means of cascaded single-phase transformers. This arrangement permits the use of a single dc-link. A generalization for $K$ -stages in which $K$ -transformers are coupled with $K$-TPB converters is presented. The topology permits generating a high number of levels in the voltage waveforms with a low number of power switches in comparison with a classic topology. The multilevel waveforms are generated by the converters through a suitable pulsewidth modulation (PWM) strategy that takes into consideration the transformer turns ratios. Modularity and simple maintenance make the proposed MSC an attractive solution compared with some conventional configurations. Model, PWM strategy, and overall control are discussed in this paper. Simulation and experimental results are presented as well. [ABSTRACT FROM PUBLISHER]

This paper presents an isolated auxiliary power supply for medium-voltage power electronics systems. The proposed converter comprises two stages: a non-isolated ac/dc stage that connects directly to the medium-voltage line, and an isolated dc/dc stage that provides 100-W output power at 24 V, with 10 kV isolation. The proposed modular ac/dc stage uses just one active semiconductor device per module, features an internal capacitor voltage balancing, and achieves power factor correction by employing predictive current control. High switching frequency operation of both converter stages enable a reduction in system size and weight when compared to traditional low-frequency transformer-based approach. The proposed converter is simulated and its operation is validated experimentally on a 100-W prototype. [ABSTRACT FROM AUTHOR]

Paralleled inverters have the merits of high power rating, improved reliability, and convenient maintenance. However, zero-sequence circulating current (ZSCC) will occur and lead to current distortion and system loss. The ZSCC control is more complicated when three-level topology is utilized and paralleled number is increased. Therefore, this paper proposes a simplified ZSCC suppression scheme for multi-paralleled three-level T-type inverters (3LT2Is). A novel equivalent model is developed and the ZSCC controller based on the new model is easier to implement. Thus, the number of paralleled inverters can be increased without complicating the control scheme and the inverters could be switched on or off optionally. Besides, Feed-Forward (FF) strategy is adopted to eliminate the ZSCC spikes caused by symmetrical three-level space vector modulation. The effectiveness of the proposed control scheme is verified by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents design of an isolated high-step-down dc–dc converter based on a class-DE power stage, operating at a 10-MHz switching frequency using enhancement-mode gallium nitride transistors. The converter operating principles are discussed, and the power stage design rated for 20 W is presented for a step down from 200–300 V input to 0–28 V output. Commercially available magnetic materials were explored and the high-frequency resonant inductor and transformer designs using a low-loss Fair-Rite type 67 material are presented. Finite-element simulations have been performed to estimate the parameters of magnetics at 10-MHz. Experimental results are presented at 12 W, 254 V input to 22 V output and 5 W, 254 V input to 14 V output on a laboratory prototype operating at 10-MHz. At 20 W, the experimental prototype achieved an efficiency of 85.2%. [ABSTRACT FROM AUTHOR]

This paper presents the development, analysis, and performance evaluation of a new topology for an isolated dc power electronic converter (PEC). The proposed topology (called the reverse flyback dc PEC) is developed to process a discontinuous input voltage and produce a continuous output voltage. The reverse flyback dc PEC is operated based on charging the inductive element in the high-frequency transformer, while discharging the energy to the output side through on–off actions of the switching element, which is located on the secondary side of the high-frequency transformer. A prototype for the proposed reverse flyback dc PEC is constructed to evaluate its performance under different operating conditions. Performance results show that the reverse flyback dc PEC is capable of processing discontinuous input voltages with different duty ratios and maintaining continuous output voltages with a minor sensitivity to the load type of ratings. [ABSTRACT FROM AUTHOR]

This paper proposes a high-frequency isolated dc/dc converter, whose switching frequency is 20 MHz. Meanwhile, the switch voltage stress is reduced based on optimal switch impedance. In the proposed converter, the switch can operate in ZVS condition, which can help to reduce the switching loss. A mathematical model of the proposed high frequency converter is built, which provides an effective design method for the system parameters. Meanwhile, the design method for PCB air-core transformer has been proposed and depicted. To verify the feasibility of the proposed converter and mathematic model, a 10 W prototype is built. [ABSTRACT FROM AUTHOR]

In this paper, a highly reliable back-to-back (BTB) power converter is proposed for doubly fed induction generator-based wind turbines (DFIG-WTs). When a power switch open-circuit fault is encountered in either the grid-side converter (GSC) or the rotor-side converter (RSC), a four-switch three-phase (FSTP) topology is formed to avoid using redundant bridge arms, which reduces the power circuit complexity and minimizes the conduction and switching losses. A simplified space vector pulsewidth modulation technique is used to eliminate sector identification and complex trigonometric calculations. In addition, the influence of dc-bus capacitor voltage unbalance on the electromagnetic torque is analyzed in detail. The offset current components are calculated, and they are deducted from the reference values in the modified control strategies to suppress the dc-bus voltage deviation. Moreover, the power loss model of a BTB converter is analyzed in detail, and the efficiency study is performed in various post-fault situations. Simulations in MATLAB/Simulink are carried out to verify the performance of a DFIG-WT based on a FSTP BTB converter. Furthermore, the control hardware-in-the-loop setup with RSC and GSC separately simulated in a digital real-time simulator is applied for experimental verification of the proposed control strategy. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-sequence current suppression control strategy for the five-phase open-winding fault-tolerant fractional-slot concentrated-winding interior-permanent-magnet (FTFSCW-IPM) motor drive system with a common dc bus is proposed. By unequal distribution of the zero voltage vector, the proposed method can well suppress the zero-sequence current caused by the dead-time effect that the conventional eliminating method cannot be achieved. First, the dead-time effect to the zero-sequence current is discussed. Then the zero-axis controller is designed to obtain the reference common-mode voltage. Last, according to the principle of the unequal zero voltage vector distribution, the switching sequence of the two inverters can be calculated, and the maximum modulation index is also first deduced in detail. The proposed method is proved by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Three three-phase unidirectional open-end topologies with reduced active switch count are investigated in this paper. These configurations arise from the replacement of controlled switches by diodes, in order to reduce the system complexity. Furthermore, the costs are also reduced once less driver circuitry is needed. The proposed topologies make the ac–dc conversion of the power delivered by a permanent magnet synchronous machine operating at unity power factor. Each configuration is made out of two converters in which at least one is derived from the substitution of active switches in two-level legs or three-level neutral-point clamped legs. The proposed configurations have less switches, making it possible to obtain the same number of voltage levels (in relation with the conventional configurations) with half or quarter of the number of active switches. Also, the topologies are compared in terms of semiconductor power losses and harmonic distortion. The control strategy of the systems as well as a detailed model, simulation, and experimental results are presented. [ABSTRACT FROM AUTHOR]

Low-voltage dc distribution systems have gained significant attention over the last years, since they provide simpler and more efficient integration of distributed generators and storage devices, establishing a pathway to net zero energy buildings. In low-power units, transformerless utility interface is preferred to reduce footprint and losses. However, the lack of galvanic isolation introduces a common-mode (CM) path between the dc distribution bus and the utility service grounding, leading to the presence of high CM voltages at the dc bus feeders. The attenuation of the CM voltage reduces the touch voltage amplitude and leakage current, contributing to a safer environment. In this paper, a feed-forward active compensation of the CM voltage is proposed. It relies on utility voltage parameters, estimated by a phase locked loop, to generate a counter CM voltage; hence, it does not require previous knowledge of the system CM path model or the addition of voltage sensors. Experimental results show that this technique can attenuate the CM voltage to non-dangerous magnitudes without interfering with the microgrid differential mode behavior. [ABSTRACT FROM AUTHOR]

A switching-capacitor-based buck–boost converter (with common ground) for point of load applications is proposed in this paper. It is capable of operating in stand-alone buck or boost mode in addition to its primary operation of performing the buck–boost conversion. The striking feature of the proposed converter is low source current ripple content irrespective of its mode of operation (buck–boost, buck, or boost). First, feasible pulsewidth modulation schemes for the proposed converter are identified and thereafter the corresponding circuit performance analysis, steady-state analysis, and state-space modelling is established. Through steady-state analysis, voltage gain expressions are formulated and equations defining L-C components are derived in terms of their ripple quantities. The state-space models are used to formulate small-signal analysis and to obtain the relevant transfer functions required in the controller design. A voltage-mode/current-mode controller is designed, with a tradeoff in bandwidth, to control the proposed converter and transit it from buck to boost mode or vice versa seamlessly. A 30–55 W, 100 kHz, prototype point of load converter with 36-V input dc source is built to supply power at constant load voltage of either 48 or 28 V. The proposed converters’ effectiveness is demonstrated experimentally in terms of reduced source current ripple along with seamless transition from buck to boost mode and vice versa. [ABSTRACT FROM AUTHOR]

In this paper, three generalized configurations of three-phase pulsewidth modulated (PWM) rectifiers are presented. They are composed of cascaded cells, each formed by a three-phase bridge of switching devices and a three-phase transformer to cascade the cells and isolate the load from the power source. One configuration is bidirectional, whereas the other two are unidirectional alternatives that replace power switches for diodes in some legs. The turns ratios of transformers from each cell are designed in order to provide the required gain and number of levels in the inverted multilevel voltage, enhancing power quality while attending requirements for proper operation in each case. Configurations with two and three cells are compared by means of simulations between themselves and with three conventional three-phase PWM rectifiers: the two-level insulated gate bipolar transistor bridge and the multilevel neutral point clamped (NPC) bridge and NPC H-bridge. Many degrees of asymmetry between the transformers in each cell, determined by the turns ratios, are considered to evaluate their impact on the topologies with relation to performance and cost. It is shown that proposed multilevel rectifiers present lower harmonic distortion, semiconductor losses, and switching stress, and some options with intermediate asymmetry are considered as good alternatives to the most asymmetrical cases. Experimental results are also provided for configurations with two cells, to demonstrate their lower harmonic distortion and power losses compared to the conventional isolated two-level PWM rectifier. [ABSTRACT FROM AUTHOR]

In this paper, in response to the open-circuit fault scenario in the grid-side converter (GSC) of doubly fed induction generator-based wind turbines (DFIG-WTs), a fault-tolerant four-switch three-phase (FSTP) topology-based GSC is studied. Compared with other switch-level fault-tolerant converter topologies, fewer switches, less switching and conduction losses, and simpler converter structure are derived. A simplified space vector pulse width modulation (SVPWM) technique is proposed to improve the output current quality and reduce the computational complexity in the control process. Unified expressions of duty ratios for the two remaining healthy bridge arms are obtained. In addition, the three-phase unbalance phenomenon caused by the capacitive impedance in the faulty phase is analyzed from the ac point of view, and a current distortion compensation scheme is illustrated. Furthermore, a dc-bus voltage deviation suppression strategy is proposed to maximize the dc-bus voltage utilization rate and mitigate the damage to the dc-link capacitors. Simulations are carried out in MATLAB/Simulink2017a to demonstrate the validity of the proposed SVPWM technique and compensation schemes in FSTP GSC for a 1.5-MW grid-connected DFIG-WT when different working conditions are considered. [ABSTRACT FROM AUTHOR]

Many of the renewable energy resources, like offshore wind, utility PV farms, are located far away from the load centers, which requires dc power transmission system to efficiently deliver power. Voltage-source converter solution is required in many applications due to the stability and compensation requirement. This paper presents a new voltage source converter topology for medium to high voltage dc application, named modular embedded multilevel converter (MEMC). MEMC is based on a three-level topology structure and consists of series-connected insulated-gate bipolar transistor (IGBT) bridge stacks, like the popular modular multilevel converter (MMC) and series-connected thyristor or press-pack high voltage integrated gate-commutated thyristor or IGBT stacks. The basic operation principle, control solutions, and the methods to commutate the thyristors are explained in detail. Due to the three-level structure, the total number of IGBT stacks are reduced by half compared with MMC, leading to much lower energy storage, weight, volume, and system complexity. Also by replacing part of the IGBT stack in MMC with thyristor stack, both of the system conduction loss and switching loss can be further reduced. There are other topology variations of MEMC with a similar operational principle but different characteristics. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

This paper investigates ac–dc–ac multilevel topologies for three-phase four-wire applications obtained from an interconnection of three-leg voltage-source converters. The topologies can be applied in line voltage regulators, universal active power filters, and uninterrupted power supplies. Operating principles, a pulsewidth modulation (PWM) technique, and an overall control strategy are developed. The PWM and control strategies are suitable to regulate the dc-link voltages and to reduce the harmonic distortion, switching stress, and power losses. Simulation results are used to compare the proposed configurations with a conventional solution in terms of harmonic distortion, semiconductor losses, and others characteristics. Experimental results are presented to validate the theoretical considerations and were obtained by using insulated-gate bipolar transistors with dedicated drives and a digital signal processor with appropriated plug-in boards and sensors. [ABSTRACT FROM AUTHOR]

In this paper, a fifth-order boost point-of-load converter is developed by cascading a modified fourth-order boost converter with a combination of L–C and diode. This topology has the following salient features: Single-switch topology, common ground between source and load, low-voltage stress across intermediate capacitors, and voltage gain same as other reported fifth-order boost converters with no common ground. Steady-state and dynamic analyses demonstrate the proposed converter's boosting feature and dynamic performance, respectively. A contoured robust Bode plot methodology is employed to design the robust voltage-mode controller to ensure load voltage regulation in the presence of uncertainties. The necessary and sufficient conditions under which the designed controller guarantees the load voltage regulation and robust stability are obtained. A step-by-step robust controller design procedure is outlined. The salient features of the proposed converter and its robust performance are studied analytically, using the MATLAB platform, and validated experimentally on a 60-W prototype module. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint. [ABSTRACT FROM AUTHOR]

Current commutation from the load current path to the commutation path is the precondition to interrupt current successfully for hybrid direct current circuit breakers (DCCB). With remarkable current commutation performance, current commutation drive circuit (CCDC), mainly consisting of air-core transformer, fast-closing switch (FCS), and precharged capacitor, is proposed by us. In this paper, to eliminate the operating losses of CCDC and to avoid unrecoverable damage of FCS, CCDC used in hybrid DCCB for current commutation has been improved. Different submodules (SM) of commutation path in hybrid DCCB are analyzed, and experiments have been carried out on a hybrid DCCB prototype. Theoretical analysis and experiment results have shown that no matter which kind of SM is used, improved CCDC can ensure reliable current commutation in hybrid DCCB. In the end, by taking total cost of CCDC into consideration, a novel optimization method is proposed to design the parameters of CCDC. With this optimization method, CCDC for hybrid DCCBs with different rated voltage and current can be designed individually and its cost could be reduced significantly. [ABSTRACT FROM AUTHOR]

Parallel ac-link universal power converters are a relatively new class of power converters that can be configured as dc–dc, dc–ac, ac–dc, and ac–ac. These converters are extensions of a buck–boost converter in which the current of the inductor is alternating and the input and output can have any number of phases with any forms, voltage amplitude, or frequency. By placing a small capacitor in parallel with the link inductor, all the switches can benefit from soft switching. The main limitation of the parallel ac-link universal power converter is its large number of switches. A three-phase ac–ac configuration requires 24 unidirectional switches. This paper proposes two topologies based on the parallel ac-link universal power converters that significantly reduce the number of switches. One of the proposed topologies reduces the number of switches in a three-phase ac–ac configuration to 16. The other topology reduces the number of switches to 10. The latter can offer galvanic isolation with only a single-phase high-frequency transformer. This paper presents the principles of the operation of the proposed topologies and evaluates them through simulation and experiments. [ABSTRACT FROM AUTHOR]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

Multilevel converters are a proven solution for medium-voltage and high-power applications, including renewable energy conversion. Developing 6.6-kV converters is a key goal for the wind turbines industry. Considering the voltage rating of commercially available semiconductors, five-level converters are necessary to reach 6.6 kV. The five-level active neutral-point-clamped converter (5L-ANPC) is one of the most advantageous topologies among five-level multilevel converters. This paper presents a new 5L-ANPC topology that overcomes the features of the previously employed 5L-ANPC topology. Along this paper, the properties and working principle of this new 5L-ANPC are explained. Finally, the validity of the new converter is validated via simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a new T-type inverter topology based on multistate switching cell is proposed. The topology presents five-level voltage before the output $LC$ filter, providing high-order harmonics that are easily filtered. In this topology, the output filter ripple frequency is twice the switching frequency, therefore reducing the magnetic weight and volume. Other characteristics of the inverter are current sharing through the devices, facilitating its losses' dissipation, due to increased contact area and few involved components in the current flow path. In order to verify its feasibility, a design example, as well as experimental results, for a 5-kW prototype is presented in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a new compact three-phase cascaded multilevel inverter (CMLI) topology with reduced device count and high-frequency magnetic link. The proposed topology overcomes the predominant limitation of separate dc power supplies, which CMLI always require. The high-frequency magnetic link also provides a galvanic isolation between the input and output sides of the inverter, which is essential for various grid-connected applications. The proposed topology utilizes an asymmetric inverter configuration that consists of cascaded H-bridge cells and a conventional three-phase two-level inverter. A toroidal core is employed for the high-frequency magnetic link to ensure compact size and high-power density. Compared with counterpart CMLI topologies available in literature, the proposed inverter has the advantage of utilizing the least number of power electronic components without compromising the overall performance, particularly when a high number of output voltage levels is required. The feasibility of the proposed inverter is confirmed through extensive simulation and experimentally validated studies. [ABSTRACT FROM AUTHOR]

This paper presents a high-power-density high-power-factor GaN-based two-stage electrolytic-free offline LED driver. The LED driver achieves high power density through the use of a hybrid film–ceramic stacked switched capacitor (SSC) energy buffer, and a comprehensive optimization methodology that evaluates various converter topologies and designs and minimizes overall system volume while maintaining high efficiency. Based on this optimization approach, a totem-pole bridgeless boost power factor correction (PFC) converter is selected for the first stage, while a stacked-input isolated LLC dc–dc converter is selected for the second stage. The optimization procedure also minimizes the passive volume of the SSC energy buffer incorporating the volumetric energy density of commercially available capacitors. The optimized SSC energy buffer utilized in the proposed LED driver has 50% less passive volume than a capacitor-only solution. A 600-W prototype LED driver designed using the proposed approach for universal input voltage ${{(90}}-{ 305 \ \text{V}}_{{\text{rms}}})$ and 24-V output voltage is built and tested. The PFC stage achieves a peak efficiency of 98% while the LLC stage achieves a peak efficiency of 95%. The prototyped LED driver achieves a power density of 28 W/in3. [ABSTRACT FROM AUTHOR]