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This paper presents a novel control strategy to significantly reduce the high-frequency transformer loss in a modular solid-state transformer (SST) based converter system. The modular SST design is based on an ac–dc power-electronic building block comprised of an H-bridge at the ac input and a bidirectional soft-switching isolated dc–dc converter with a medium-voltage insulated high-frequency transformer. The ac terminals of input H-bridges are connected in series and directly coupled to the medium-voltage ac line, while the output dc terminals are all connected in parallel at a low voltage. The key innovation described in this paper, without sacrificing the output performance, is the control scheme that reduces core and winding losses associated with the dc–dc resonant stage by turning off the selected dc–dc converters in synchronism with the line voltage. The prototype for the test described in this paper is based on a modular SST where each module is rated at 50 kVA, with a 200 kHz transformer using 1.7 kV silicon carbide discrete mosfets, but the described control concepts are more broadly applicable to similar topologies. [ABSTRACT FROM AUTHOR]

The number of applicable carrier-based pulsewidth modulation (PWM) patterns increases with the growth of output levels in scalable multilevel topologies, such as active-neutral-point-clamped (ANPC) converters. Therefore, it is hard to optimize PWM for such topology, especially with large output levels. In this paper, a simplified and modular carrier-based PWM design approach for multilevel ANPC converters is proposed. Inspired by the decomposition theory, the topology decomposition is introduced in this paper to decompose an N-level ANPC converter into low-level subtopologies. Then, the complete set of applicable PWM patterns is derived based on ANPC operation principles, which makes it possible to optimize the performance based on the various requirements in applications. Meanwhile, the carrier-based PWM is implemented through the utilization of subtopologies with low-level modulation schemes, such that the design process of carrier-based PWM is greatly simplified and modularly realized. Both the complete PWM patterns and PWM design examples with experimental results of several ANPC converters are provided to show the feasibility and modularity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, the pulsewidth modulation switch method was used to investigate the effect of the transformer leakage inductance on the small-signal model in isolated full-bridge converter. A galvanic isolated hard-switching full-bridge converter that operates in constant-current mode is analyzed, confirming that leakage inductance significantly affects the small-signal model, and the influence of leakage inductance can be equivalent to a resistance in series with the converter's output LC filter just as that in phase-shifted full-bridge converter. However, the same leakage inductance in these both converters will lead to different equivalent resistance due to different operating principles. Results of the modified model, simulations, and the experiments are compared to verify the correctness of the model. Moreover, this paper also shows that the Norton equivalent circuit of the charger operates in constant current mode, which can be used to estimate the dynamic behavior of the system. [ABSTRACT FROM AUTHOR]

Dual-comparison one-cycle control for the bidirectional power flow in single-phase grid-connected converters is proposed in this paper. Advantages of dual-comparison one-cycle control when compared to conventional one-cycle control is that it does not give any steady-state dc offset, no light-load instability, and implements unipolar pulsewidth modulation without having to sense the grid voltage. Addition of a fictitious current term, which is generated from the gating signal of one of the active devices, using a bandpass filter, enables the bidirectional power flow. The quality factor of the bandpass filter is shown to impact the total harmonic distortion in current, fundamental displacement angle, and steady-state dc offset. The optimal value of a quality factor, obtained with aid of simulations, gives a superior performance. The current drawn or injected into the grid is seen to lag the grid voltage. The reason for a nonunity displacement power factor is analyzed and a compensation to achieve a unity displacement power factor is also proposed in this paper. Detailed simulation and experimental studies are carried out to validate the proposed control and the high performance that can be obtained. [ABSTRACT FROM AUTHOR]

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, the characteristics of ripple current of a multimegawatt drive system fed by a pulse-width modulation (PWM) inverter are investigated. Based on the investigation, a novel PWM scheme is devised to reduce the switching loss of the inverter under an identical amount of torque ripple of a motor. The proposed PWM is composed of two parts. The first is minimum torque ripple PWM (MTRPWM), which is optimized in terms of the minimum torque ripple in high modulation index (MI). The second determines the minimum switching frequency while holding the average torque ripple less than the allowable value under various operating conditions. It is termed reduced switching frequency PWM (RSFPWM). Consequently, by simply changing the PWM method from conventional fixed switching frequency continuous PWM to the proposed PWM, MTRPWM and RSFPWM, simulation results show that the switching loss of the inverter driving a 3.5 MW induction motor is reduced to 51.6% while keeping the torque ripple in the allowable boundary, where MI is 1.12. This approach is applied to small-scale experimental sets consisting of an interior permanent magnet synchronous machine (IPMSM) motor-generator set, and an induction machine MG set in an effort to verify the validity and feasibility of the proposed method. Based on these experimental results, the cost indexes of the IPMSM and the induction machine, as defined in this paper, decrease by up to 66% and 77%, respectively, when the proposed method is applied when MI is 1.12 compared with the outcome with the conventional PWM. [ABSTRACT FROM AUTHOR]

Neutral-point-clamped (NPC) multilevel inverter fed high power drives operating at low switching frequency are prone to low-order torque pulsations. For a case of N switching angles per quarter, apart from maintaining the fundamental component, (N-1) voltage harmonics can be eliminated. Consequently, \fracN-12 or lower number of torque harmonics could be eliminated. This paper proposes an optimal pulse-width modulation (PWM), which minimizes the combined root mean square (RMS) value (\tau RMS ) of torque harmonics of order lower than $6N$ at any modulation index (M$) for an induction motor drive fed from an NPC three-level inverter. This paper considers cases of two, three, and four switching angles per quarter cycle of the pole voltage. Compared with synchronized sine-triangle PWM and selective harmonic elimination (SHE) PWM, the proposed PWM reduces the first (N-1$ ) torque harmonics (i.e., \tau _6 ) over a wide speed range. Simulation and experimental results are presented on a 3.7-kW open-loop constant volts-per-Hertz induction motor drive. [ABSTRACT FROM PUBLISHER]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a novel single source fed isolated gate driver circuit based on the dual-forward converter topology. The two forward converters are paralleled at the secondary side to achieve 0%–100 $\%$ duty cycle range together with galvanic isolation. The gate driver switching frequency is independent of the main pulse-width modulation frequency (PWM). As a result, the gate driver switching devices and magnetics are designed for high frequencies independent of the main PWM frequency. At high frequencies, problems of resonance due to parasitics become significant. This paper discusses this problem and proposes a novel solution to mitigate it. In addition, this paper also presents a novel solution and circuit to produce negative gate pulse for miller clamp. The proposed circuit can be used for any application, irrespective of switching frequency, thus making it a wide band generalized gate driver. The circuit is analyzed and verified experimentally. [ABSTRACT FROM PUBLISHER]

Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

This paper proposes a new grid current controller for a photovoltaic (PV) module integrated buck inverter using a single pulsewidth modulation switch and an unfolding H-bridge, which significantly reduces switching losses. To achieve this, an internal grid current loop with active damping is presented with an LCL filter to connect it to the utility grid. The problem of the filter natural resonance is solved by means of a virtual impedance (active damping), demanding no additional sensor. Experimental results obtained from a 200-W prototype achieved a European efficiency of 96.27% with a current total harmonic distortion of 3.7%. [ABSTRACT FROM AUTHOR]

In this paper, the zero sequence circulating current in open winding permanent magnet synchronous machine (OW-PMSM) drives with common dc bus is systematically analyzed for the first time. It is revealed that the zero sequence circulating current is affected by zero sequence back-electromotive force, cross coupling voltages in zero sequence from the machine side, pulse-width modulation induced zero sequence voltage, and inverter nonlinearity from the inverter side. Particularly, the influences from the cross coupling voltages in zero sequence and parasitic effect of inverter nonlinearity are investigated for the first time in this paper. Then, the synthetic model of the equivalent zero sequence circuit is proposed as well. Each cause is studied independently via analytical modeling, finite element analysis, and experiments. Meanwhile, to tackle this issue, the relevant suppression strategy using frequency adaptive proportional resonant controller is presented and tested on the 3 kW OW-PMSM platform. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel series compensator (MSC) to deal with voltage sags/swells, harmonic compensation, or reactive power compensation. Such a device can be considered as a dynamic voltage restorer or a series active power filter (Series-APF). The MSC can improve the power quality of loads located in stiff systems. The configuration is based on three-phase bridge (TPB) converters connected by means of cascaded single-phase transformers. This arrangement permits the use of a single dc-link. A generalization for $K$ -stages in which $K$ -transformers are coupled with $K$-TPB converters is presented. The topology permits generating a high number of levels in the voltage waveforms with a low number of power switches in comparison with a classic topology. The multilevel waveforms are generated by the converters through a suitable pulsewidth modulation (PWM) strategy that takes into consideration the transformer turns ratios. Modularity and simple maintenance make the proposed MSC an attractive solution compared with some conventional configurations. Model, PWM strategy, and overall control are discussed in this paper. Simulation and experimental results are presented as well. [ABSTRACT FROM PUBLISHER]

The control of an ultracapacitor (UC)-based dc–dc power supply is crucial to provide reliable energy backup to critical loads in the case of momentary power main failures. In this regard, smooth and seamless transition between charging and discharging controls of UC stack is of paramount importance. For ride-through applications where charging and discharging times are critical, provision of different control structures for charging and discharging subsystems is crucial. The conventional control techniques, though ensure seamless mode transition, does not allow different control structures for both the subsystems. This paper proposes an independent switch control strategy, which ensures seamless transition between charging and discharging control modes. The proposed control is based on pulse-width modulation blocking and is shown to ensure the fastest mode transition between control modes. The proposed control also elucidates an accurate method for identification of control modes, which is important to independent switch control. The advantages of the proposed control compared with conventional controls is presented in this paper. The proposed control strategy has been verified in simulations and experimentation, and the mode identification algorithm is found to work well. [ABSTRACT FROM PUBLISHER]

This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfets. [ABSTRACT FROM AUTHOR]

Three-level neutral-point-clamped (NPC) inverters are being widely adopted in low-voltage low-power applications. For an intended application, the modulation strategy and the operating conditions are the two key factors that highly influence the major performance indices of the NPC inverter, such as efficiency, harmonic distortion, and voltage oscillations at neutral point (NP). Considering dynamic loading applications where the operating point varies significantly, this paper proposes an improved adjustable pulsewidth modulation (PWM) strategy for a three-level NPC inverter that can alter its modulation pattern to meet desired performance objectives for the full operation range. It has been shown that by varying two control parameters namely discontinuity control parameter and bias control parameter, the proposed modulation strategy changes its pattern between the most efficient generalized discontinuous PWM to NP oscillations-free partial dipolar PWM strategy. Additionally, to obtain a tradeoff between the performance parameters—efficiency, NP oscillations, and waveform quality—The proposed strategy has the ability to settle at the intermediate modulation patterns by transforming into a hybrid modulation signal. Furthermore, considering NP voltage unbalance mitigation as major technical challenge in adjustable modulation strategy, a voltage unbalance compensator that exhibits satisfactory balancing performance for the entire variations of modulation patterns and operating conditions has also been presented. The performance of the proposed modulation strategy in conjunction with voltage unbalance compensator has been evaluated in simulation by widely varying the speed and load of induction motor, and verified in experimentation. [ABSTRACT FROM AUTHOR]

Three-phase voltage source pulsewidth modulation (PWM) rectifiers can achieve constant dc voltage and sinusoidal grid currents under ideal grid voltages. However, under unbalanced grid voltage conditions, there are ripples at twice the grid frequency in the dc voltage, and the grid currents become highly distorted. To address the aforementioned problems, control methods developed under ideal grid voltage conditions should be modified. Various techniques have been proposed in the literature to calculate the new current reference or power reference. However, most methods use conventional pq theory and only consider the grid-side power control. Hence, the dc voltage ripples are not completely eliminated. Furthermore, the derived mathematical expressions for reference calculations are usually very complicated. In contrast to current methods, this paper proposes a very simple yet effective direct power control (DPC) method based on extended pq theory. By analyzing the instantaneous extended power of the line inductance, a simple and concise power compensation is analytically derived and added to the original power references. As a result, the dc voltage ripples are significantly reduced, and the grid currents remain sinusoidal even under unbalanced grid voltage conditions. The proposed method is compared to conventional DPC methods, and its effectiveness is confirmed by the presented experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a highly reliable back-to-back (BTB) power converter is proposed for doubly fed induction generator-based wind turbines (DFIG-WTs). When a power switch open-circuit fault is encountered in either the grid-side converter (GSC) or the rotor-side converter (RSC), a four-switch three-phase (FSTP) topology is formed to avoid using redundant bridge arms, which reduces the power circuit complexity and minimizes the conduction and switching losses. A simplified space vector pulsewidth modulation technique is used to eliminate sector identification and complex trigonometric calculations. In addition, the influence of dc-bus capacitor voltage unbalance on the electromagnetic torque is analyzed in detail. The offset current components are calculated, and they are deducted from the reference values in the modified control strategies to suppress the dc-bus voltage deviation. Moreover, the power loss model of a BTB converter is analyzed in detail, and the efficiency study is performed in various post-fault situations. Simulations in MATLAB/Simulink are carried out to verify the performance of a DFIG-WT based on a FSTP BTB converter. Furthermore, the control hardware-in-the-loop setup with RSC and GSC separately simulated in a digital real-time simulator is applied for experimental verification of the proposed control strategy. [ABSTRACT FROM AUTHOR]

A switching-capacitor-based buck–boost converter (with common ground) for point of load applications is proposed in this paper. It is capable of operating in stand-alone buck or boost mode in addition to its primary operation of performing the buck–boost conversion. The striking feature of the proposed converter is low source current ripple content irrespective of its mode of operation (buck–boost, buck, or boost). First, feasible pulsewidth modulation schemes for the proposed converter are identified and thereafter the corresponding circuit performance analysis, steady-state analysis, and state-space modelling is established. Through steady-state analysis, voltage gain expressions are formulated and equations defining L-C components are derived in terms of their ripple quantities. The state-space models are used to formulate small-signal analysis and to obtain the relevant transfer functions required in the controller design. A voltage-mode/current-mode controller is designed, with a tradeoff in bandwidth, to control the proposed converter and transit it from buck to boost mode or vice versa seamlessly. A 30–55 W, 100 kHz, prototype point of load converter with 36-V input dc source is built to supply power at constant load voltage of either 48 or 28 V. The proposed converters’ effectiveness is demonstrated experimentally in terms of reduced source current ripple along with seamless transition from buck to boost mode and vice versa. [ABSTRACT FROM AUTHOR]

In this paper, three generalized configurations of three-phase pulsewidth modulated (PWM) rectifiers are presented. They are composed of cascaded cells, each formed by a three-phase bridge of switching devices and a three-phase transformer to cascade the cells and isolate the load from the power source. One configuration is bidirectional, whereas the other two are unidirectional alternatives that replace power switches for diodes in some legs. The turns ratios of transformers from each cell are designed in order to provide the required gain and number of levels in the inverted multilevel voltage, enhancing power quality while attending requirements for proper operation in each case. Configurations with two and three cells are compared by means of simulations between themselves and with three conventional three-phase PWM rectifiers: the two-level insulated gate bipolar transistor bridge and the multilevel neutral point clamped (NPC) bridge and NPC H-bridge. Many degrees of asymmetry between the transformers in each cell, determined by the turns ratios, are considered to evaluate their impact on the topologies with relation to performance and cost. It is shown that proposed multilevel rectifiers present lower harmonic distortion, semiconductor losses, and switching stress, and some options with intermediate asymmetry are considered as good alternatives to the most asymmetrical cases. Experimental results are also provided for configurations with two cells, to demonstrate their lower harmonic distortion and power losses compared to the conventional isolated two-level PWM rectifier. [ABSTRACT FROM AUTHOR]

A discontinuous pulsewidth modulation (DPWM) strategy for three-level neutral-point-clamped (NPC) traction inverter drive for electric vehicles (EVs) with minimum switching loss for the full power factor (PF) range is developed and presented in this paper. Considering the dynamic loading conditions in an EV propelled by an induction motor (IM), the discontinuous modulation strategy is generalized to obtain minimum switching loss for a wide variations in load PF and modulation depth. The dynamic operating conditions in EV may render frequent unbalances in dc-link capacitor voltages in NPC inverter. It is demonstrated that the addition of an appropriate offset signal with the reference discontinuous signals generates compensating neutral current in the right direction, which can be used to mitigate existing unbalance in two dc-link capacitor voltages. Minimum switching loss at variable PF is attained by positioning the nonswitching clamped regions of the reference auxiliary signals according to the load PF. The effectiveness of the proposed scheme for a wide range of torque/speed variations is studied through simulation by developing a MATLAB/SIMULINK model of an IM traction inverter drive with field-oriented control strategy for closed loop control. Finally, the modulation scheme is validated through experimentation in a small-scale prototype NPC inverter with motor loads. [ABSTRACT FROM AUTHOR]

In this paper, in response to the open-circuit fault scenario in the grid-side converter (GSC) of doubly fed induction generator-based wind turbines (DFIG-WTs), a fault-tolerant four-switch three-phase (FSTP) topology-based GSC is studied. Compared with other switch-level fault-tolerant converter topologies, fewer switches, less switching and conduction losses, and simpler converter structure are derived. A simplified space vector pulse width modulation (SVPWM) technique is proposed to improve the output current quality and reduce the computational complexity in the control process. Unified expressions of duty ratios for the two remaining healthy bridge arms are obtained. In addition, the three-phase unbalance phenomenon caused by the capacitive impedance in the faulty phase is analyzed from the ac point of view, and a current distortion compensation scheme is illustrated. Furthermore, a dc-bus voltage deviation suppression strategy is proposed to maximize the dc-bus voltage utilization rate and mitigate the damage to the dc-link capacitors. Simulations are carried out in MATLAB/Simulink2017a to demonstrate the validity of the proposed SVPWM technique and compensation schemes in FSTP GSC for a 1.5-MW grid-connected DFIG-WT when different working conditions are considered. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

This paper presents an improved analytical model for estimating the high-frequency current ripple of interior permanent magnet synchronous machines due to pulsewidth modulation (PWM) switching. The proposed model accounts for the impact of slotting effect, magnetic saturation, and cross-coupling between the $d$ - and $q$ -axis. The model is subsequently used to investigate several factors that influence the PWM-induced current ripple. These include the PWM switching frequency, fundamental frequency (i.e., machine speed), dc-bus voltage, current control angle (i.e., γ angle), and the excitation current amplitude (i.e., saturation level). Experiments have been conducted to verify the analytical prediction results. These results show that the analytical model can predict the PWM-induced current ripple waveshape very well for many operating conditions and accurately estimate its rms value over a complete fundamental period. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

An optimal current control strategy for asymmetrical hybrid multilevel inverters (MLIs) is proposed in this paper enabling their use on motor drives, static synchronous compensators, and photovoltaic and wind generators, where a fast and precise current regulation is required. A key feature of these highly efficient converters is that an ac machine (motor or transformer) operates according to an open-end winding configuration, connected on one side to a main MLI and, on the other side, to an auxiliary two-level inverter (TLI). The first efficiently controls the main power stream operating at a low switching frequency, while the TLI acts as an active power filter, exploiting a conventional high-frequency two-level pulsewidth modulation (PWM) technique. The proposed control scheme optimally exploits the key features of the two inverters by suitably sharing the control task. In fact, a predictive current control is assigned to the MLI, which can be accomplished by low switching frequency operations, while the high switching frequency of the PWM-operated TLI is exploited to accomplish a fast and precise closed-loop current control, processing only a part of the power stream flowing through the system, thus producing low power losses. Simulations and experimental results confirm the consistency of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

In order to prevent the power switching devices (e.g., an insulated-gate bipolar transistor, IGBT) from shoot-through in voltage-source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in pulse width modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as “dead-time harmonics” hereafter) have to be compensated in order to achieve a satisfactory current quality, as required by standards. In this paper, the emission mechanism of dead-time harmonics in single-phase PWM inverters is, thus, presented considering the modulation schemes in detail. More importantly, a repetitive controller has been adopted to eliminate the dead-time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional-resonant-based fundamental-frequency current controller so as to mitigate the dead-time harmonics and also to maintain the control of the fundamental-frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead-time harmonics and other low-order distortions, and also, it is a simple method without hardware modifications. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid pulse width modulation-based discontinuous modulation (D-HPWM) strategy with dc-link voltage balancing for a three-level neutral-point-clamped (NPC) traction inverter drive. The results are then compared with continuous-hybrid-PWM (C-HPWM) to check the performance improvement. The HPWM strategy uses both the advantages of carrier- and space-vector-based PWM strategies. The duty cycles are generated using the carrier-based strategy to reduce the computational time and complexity of the system and redundant vector states are used to keep the two dc-link capacitor voltages balanced. As discontinuous PWM (DPWM) reduces the switching losses considerably compared to the continuous PWM, the DPWM strategy is developed in this paper for the HPWM-based strategy. Detailed comparison studies are then carried out in MATLAB/Simulink and PLECS to show the conduction and switching loss distribution with change in modulation index for different power switches. A 54.0-kW surface permanent magnet synchronous machine (PMSM) is used for this simulation studies. Moreover, the total inverter loss and losses in each insulated gate bipolar transistor (IGBT) are also compared. Detailed experimental performance analysis is also carried out with a scaled down prototype of a 6.0-kW surface PMSM, NPC inverter, and real-time emulator DSpace, to show the capacitor voltage deviation with both control strategies. [ABSTRACT FROM PUBLISHER]

A low-order harmonic pulsating torque is a major concern in high-power drives, high-speed drives, and motor drives operating in an overmodulation region. This paper attempts to minimize the low-order harmonic torques in induction motor drives, operated at a low pulse number (i.e., a low ratio of switching frequency to fundamental frequency), through a frequency- domain (FD) approach as well as a synchronous reference frame (SRF) based approach. This paper first investigates FD-based approximate elimination of harmonic torque as suggested by classical works. This is then extended into a procedure for minimization of low-order pulsating torque components in the FD, which is independent of machine parameters and mechanical load. Furthermore, an SRF-based optimal pulsewidth modulation (PWM) method is proposed to minimize the low-order harmonic torques, considering the motor parameters and load torque. The two optimal methods are evaluated and compared with sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experimental studies on a 3.7-kW induction motor drive. The SRF-based optimal PWM results in marginally better performance than the FD-based one. However, the selection of optimal switching angle for any modulation index $(M)$ takes much longer in case of SRF than in case of the FD-based approach. The FD-based optimal solutions can be used as good starting solutions and/or to reasonably restrict the search space for optimal solutions in the SRF-based approach. Both of the FD-based and SRF-based optimal PWM methods reduce the low-order pulsating torque significantly, compared to ST PWM and SHE PWM, as shown by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper proposes a space vector modulation (SVM) strategy for asymmetrical cascaded multilevel converters operating under fault conditions on the power cells. During each switching interval, one voltage vector is chosen to be implemented by the high voltage cells. It is then subtracted from the reference, resulting in a new reference for the low voltage cells. However, under fault conditions, if the high voltage vectors are not properly chosen, the converter may saturate. This paper presents a comparison between the choice of the high voltage vector as the nearest one to the reference, and as the one whose domain encompasses it. It is shown that the second choice is better, as it avoids saturation of the converter as much as possible. The proposed SVM is performed in the output line-to-line voltages coordinate system, in which the converter voltage vectors have only integer entries. The algorithm is presented considering as an example a converter with two cells per phase: one of 1 pu that switches with PWM, and one of 2 pu, switching at the fundamental frequency, respectively called low-voltage-high-frequency and high-voltage-low-frequency cells. Finally, experimental results are given to demonstrate and validate the good performance of the proposed SVM. [ABSTRACT FROM AUTHOR]

This paper presents the voltage- and current-limited operation of an interior permanent magnet synchronous machine (IPMSM) using deadbeat direct torque and flux control (DB-DTFC). A commanded air-gap torque and stator flux can be achieved by the end of each pulsewidth modulation (PWM) period using DB-DTFC. However, it may take several PWM periods to achieve a desired air-gap torque that is physically infeasible in one step due to voltage limits. In that case, the torque and flux command trajectories operating over multiple periods can be developed to achieve deadbeat torque and flux response for every PWM period. The torque and flux command trajectories can be developed in different shapes depending on desired objectives. In this paper, a minimum-time ramp trajectory method is proposed to achieve both simple real-time implementation and fast and stable transient dynamics of IPMSM drives. Simulation and experimental results for the minimum-time ramp trajectory method for an IPMSM drive are presented. [ABSTRACT FROM AUTHOR]

This paper presents the direct compensation of the switching interval error of the effective voltage vectors by the dead time of a pulsewidth modulation voltage source inverter (PWM-VSI). The output voltages of a three-phase PWM-VSI are distorted and have voltage errors from the dead time to avoid the shoot-through of inverter arms and the time delay of the gate drive. Voltage distortion increases the harmonics of the output voltages and decreases control performance. This paper presents a simple and direct compensation technique to solve this problem in a three-phase VSI. The practical switching output voltages are determined by the dc-link voltage, the switching signals of each phase, the dead time, the time delay, and the current polarities of each phase. For these reasons, output voltage errors are not constant. In order to analyze the dead-time effect in the actual switching voltages of each phase, the practical switching voltages in a sampling period of a space vector PWM (SVPWM) method are calculated according to the current polarity. In the calculation, the dead time, the time delay of devices, and the voltage drops on power devices are included to consider nonlinear voltage distortion. From these practical switching voltages during the switching intervals in a sampling period, the average output voltages of each phase can be derived, and the output voltage errors between the voltage commands and the average output voltages of each phase are obtained. The SVPWM switching intervals of each phase can be derived by the average output voltages that are calculated according to the current polarity and nonlinear voltage distortion to compensate for the output voltage errors. With the simple detection of the current polarity, the practical errors of the switching intervals of each phase can be compensated by the addition of the compensated switching time. Simulation and experimental results validating the proposed compensation method are presented in this paper. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

Power conversion systems based on double-delta sourced winding (DDSW) had an optimization issue in terms of pulsewidth modulation (PWM). This issue was about inefficient employments of voltage levels during PWM and had to be considered for minimizing voltage stresses and current ripples on DDSW. In this paper, a novel method has been proposed to improve the performance of PWM in DDSW-based systems. The proposed method can be simply implemented as a carrier-based PWM and its principles are neatly summarized with equations. Finally, the effectiveness of the proposed method is demonstrated with experimental results, which were obtained by using a transformer and an induction machine. [ABSTRACT FROM PUBLISHER]

This paper presents the development and performance evaluation of the wavelet modulation technique for single-phase ($1\phi$) cascaded $H$-bridge (CHB) multilevel dc–ac power electronic converters (PECs). The developed technique is based on employing sets of resolution-segmented wavelet basis functions as switching signals, where each set operates one $H$ -bridge. The number of sets of wavelet basis functions is selected to match the number of levels in the output voltage of the $1\phi$ CHB dc–ac PEC. The wavelet modulation for $1\phi$ CHB multilevel dc–ac PECs is implemented for performance evaluation both in simulation and experimentation. The performance of the developed technique is evaluated for linear, nonlinear, and dynamic loads. Simulation and experimental results show significant reduction of output harmonics, along with high magnitude of the fundamental component in the output voltage. The improvements offered by the wavelet modulation technique are further demonstrated through comparisons with the level-shifted and phase-shifted pulse-width modulation techniques under similar loading conditions. [ABSTRACT FROM PUBLISHER]

This paper discusses the use of a cascaded multilevel converter for flexible power conditioning in smart-grid applications. The main feature of the proposed scheme is the use of independent dc links with reduced voltages, which makes such a topology an ideal candidate for medium- and high-power applications with increased reliability. The developed control strategy regulates independent dc-link voltages in each H-bridge cell, and allows the selective and flexible compensation of disturbing currents under a variety of voltage conditions without requiring any reference frame transformation. The selective control strategies are based on the decompositions proposed in the conservative power theory, which result in several current-related terms associated with specific load characteristics. These current components are independent of each other and may be used to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Experimental results are provided to validate the possibilities and performance of the proposed control strategies, considering ideal and deteriorated voltage conditions. [ABSTRACT FROM PUBLISHER]

Cascaded bidirectional dc–ac converters are commonly used in uninterruptible power supply applications and battery chargers for electric vehicles. Power conversion units for such applications employ a large electrolytic capacitor at high-voltage dc bus, which not only reduces the lifetime but also adds to the weight of the converter. In this paper, a novel bidirectional dual active bridge cascaded three-phase converter (DABCC) with six-pulse dc link is proposed. Also, a new closed-loop control scheme to implement the six-pulse modulation (SPM) technique in DABCC is proposed. The advantages of the proposed control scheme in DABCC are that the electrolytic capacitor is eliminated and is replaced with a low-value film capacitor resulting in increased reliability, compactness, and reduced cost. SPM technique also increases the dc bus utilization and decreases the inverter average switching frequency to 33% when compared with the conventional sine pulse-width modulation (SPWM). Harmonic components introduced in the pole voltages of the SPM-modulated DABCC due to inverter dead time are analyzed, and a resonant controller is designed to mitigate them. Also, root mean square current stress for high-voltage dc-link capacitor is studied, and it is shown that the capacitor requirement for SPM modulation is lower than the conventional SPWM. To validate the proposed control scheme, an 800-W proof-of-concept laboratory hardware prototype is fabricated and experimental results are demonstrated. [ABSTRACT FROM PUBLISHER]

Paralleling power converters is a common practice in industries to enhance total power rating, reliability, and availability of the system. In case of fault occurring in systems with parallel converters, the faulty power converter can be isolated and the system can still be operated at reduced power level. In this paper, a grid-connected power converter consisting of two parallel H-bridge converters with low ground leakage current is considered. Two contingency configurations, that are also of low ground leakage current, are proposed to enhance the availability of the system. This is done by reconfiguring the power circuit to a single H-bridge in the case of failure in one of the bridges. The power converter is experimentally tested with the proposed configurations for experimental validation. The results show that the second configuration has better performance in terms of power loss and current total harmonic distortion when operating at lower power level. [ABSTRACT FROM AUTHOR]

Soft-switching techniques have become very attractive in bidirectional grid-tie dc–ac converters utilizing high-frequency link transformers for galvanic isolation. This paper presents a new pulse-width modulation (PWM) switching technique for controlling a bidirectional isolated dc–ac–ac converter along with its soft-switching method. The proposed PWM technique has the ability to control the input dc current and to inject a sinusoidal three-phase current to the grid at unity power factor. In the first stage, an H-bridge converter is used to convert the dc voltage to a high-frequency square-wave single-phase voltage. In the second stage, a matrix converter is used to convert the high-frequency voltage waveform to conventional three-phase voltage synchronized with the grid. Therefore, a single-phase high-frequency transformer is used to link the H-bridge output voltage to the matrix converter input voltage. The proposed soft-switching technique is achieved by connecting shunt ceramic capacitors across all converter switches. The mathematical model and the circuit operation for soft-switching are presented along with the voltage controllable limits. The effectiveness of the proposed technique has been verified experimentally using a laboratory prototype. [ABSTRACT FROM PUBLISHER]

In order to increase the output voltage levels and reduce the isolated dc sources, a symmetrical hybrid nine-level inverter for high-speed motor drive applications is presented in this paper. Each phase of this inverter is composed of a five-level dc/dc converter cell and an H-bridge cell. The dc/dc converter is operated at high frequency with low-voltage devices and the H-bridge is operated at fundamental frequency with high-voltage devices. The three phases are connected to a common dc-link and each drives an isolated winding of an open-winding motor. The operating principles and modulation method are introduced. A detailed analysis of the average currents through the flying capacitor and neutral point of the dc-link is presented and a capacitor voltage balancing method based on phase-shifted pulse-width modulation is proposed. Simulation and experimental results are presented to demonstrate the feasibility of this topology and control method. [ABSTRACT FROM PUBLISHER]

This paper investigates the utilization of two different six-leg configurations of single-phase to three-phase converters. One of the topologies is transformerless and the other is transformer based. The studied converters allow feeding the load voltage with sinusoidal voltages with constant amplitude and frequency, and to operate with sinusoidal grid current with high power factor. The system model and pulse-width modulation techniques for one of the topologies are given. Control strategies for both topologies are provided. The studied topologies are compared with the conventional in terms of dc-link specification, voltages harmonic distortions, semiconductor losses, and other characteristics. Simulation and experimental results are provided to illustrate the operation of the systems. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology for a \text3-\phi three-level inverter with complete elimination of common-mode voltage (CMV). The proposed multilevel inverter (MLI) configuration is realized by modifying a T-structure \text3-\phi inverter. The proposed configuration is an optimized solution with respect to the pulse-width modulation strategy used for CMV elimination. The given three-level inverter structure uses only 16 power semiconductor switches, which is much lower than the existing configurations. A reduced number of power semiconductor devices results in a diminished number of driver circuits, less installation space, and low cost. Further, due to the complete elimination of CMV, the proposed MLI is free from issues such as electromagnetic interference and leakage current with a reduction in filter requirement. The presented topology is also compared with other existing topologies to prove its advantage. It is an optimized solution with respect to the dc bus voltage requirement and the total voltage rating of the devices or the components used in the system. Simulation and experimental results are presented to confirm the capability of the proposed MLI. [ABSTRACT FROM AUTHOR]

Single-phase pulse-width modulation (PWM) rectifier is commonly used in a high-speed railway electric traction system. Occurrence of unexpected failure in the sensors of the detection system may lead to feedback values deviation and system degradation, which can be extremely detrimental to the operation safety of the electric locomotive. This paper presents a fast and reliable fault diagnosis and fault resilient control strategy for catenary current and dc-link voltage sensor faults in the control system for an electric traction single-phase PWM rectifier. Sliding mode observers are designed to produce analytical redundancy. In order to avoid unobservable states and fluctuation introduced by discrete dynamics in observer design, a novel description for switching variables is presented in system modeling. Normalized residuals are generated using measured and observed values. The fault diagnosis unit proposed can detect and isolate three types of sensor faults online by comparing residuals with thresholds. System reconfiguration is realized by substituting the observed values for the information of faulty sensors. Simulation and experimental results are demonstrated to validate the effectiveness of the strategy. [ABSTRACT FROM AUTHOR]