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This paper presents a 10.56-GHz transceiver with ultracompact transformer-based transmit/receive (T/R) switching via matching network reuse. The reused transformer can operate as T/R switch and impedance matching networks for a power amplifier (PA) and a low-noise amplifier (LNA) simultaneously. The T/R switch, PA, and LNA are fully codesigned, and the interstage matching networks of the PA and LNA are comatched with the T/R switch to improve the performance of the front end (FE). A three-coil transformer is introduced in the PA to improve the linearity and bandwidth of the FE in the transmit (TX) mode. A mode selection unit (MSU) is also utilized in LNA to improve the TX/RX isolation and the linearity of the FE in the TX mode. Utilizing the fully codesign technique in the FE, the bandwidth of the FE is extended to over 4.2 GHz in both the TX and RX modes. A novel “gm-cell-based” broadband programmable gain amplifier (PGA) and a third-order transconductance-capacitor (gm-c) low-pass filter (LPF) are used in analog baseband to provide over 24-dB gain and 1.8-GHz bandwidth adjustment range with ultralow dc power consumption. To prove the concept, the new architecture is implemented in 28-nm CMOS technology. Measurement results prove that the insertion loss of the proposed T/R switch introduced in both the TX and RX modes is ~0.5 dB, and benefiting from this, the RX obtained a 4.2-dB noise figure, and TX obtained 9.9- and 14.1-dBm OP1dB and Psat. The measured single sideband bandwidth of the transceiver is wider than 2.1 GHz in both the TX and RX modes. [ABSTRACT FROM AUTHOR]

A time-division duplex (TDD) transmit/receive (T/R) millimeter-wave (mm-wave) front-end comprises a power amplifier (PA), a low-noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this paper, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure. The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated using 45 nm CMOS silicon-on-insulator that includes a high power, four-stack-based PA and an inductively source-degenerated cascode-based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak power added efficiency of 28%, while the LNA achieves NF of 3.2 dB. The overall chip area is 0.54 mm2, including pads. [ABSTRACT FROM AUTHOR]

This paper presents a type of bandpass filter (BPF)-integrated single-pole double-throw (SPDT) switch using common shorted stepped-impedance resonator technique. The BPF-integrated ON-state with reverse-biased p-i-n diodes can be synthesized by classical coupled-resonator filter design theory, and the OFF-state with forward-biased p-i-n diodes is detuned which exhibits high OFF-state suppression (OSS). The transmission zeros due to the direct coupled feed, the cross-couplings and the cancelling effect of mixed electric and magnetic coupling are produced to improve the ON-state passband selectivity significantly. As examples, the third-order/fourth-order BPF-integrated SPDT switches at center frequency $f_{0} = 1$ GHz with ripple bandwidth of 110/100 MHz are designed, which show low insertion losses of 1.08/1.58 dB, sharp skirts, high roll-off rate of sidebands, high OSSs of 40.9/40.1 dB as well as high port-to-port isolation of 57.4/47.8 dB. Then, the switched 50- $\Omega $ matching circuits are in series with two output ports of above BPF-integrated SPDT switches, resulting in the absorptive OFF-state. The fabricated third-order/fourth-order BPF-integrated SPDT switches with absorptive OFF-state have the matched return losses of 30/28.2 dB, and their OSSs and port-to-port isolations are also improved. [ABSTRACT FROM AUTHOR]

Class-E RF power amplifiers (PAs) are very power efficient under nominal operating conditions. Due to incorporating two tuned tanks, the dependence on the load impedance is, however, relatively large, resulting in, e.g., load-dependent output power, power efficiency, peak voltages, and peak (and average) currents which can lead to reliability issues. This paper presents load–pull analyses for class-E RF PAs from a mathematical perspective, with analyses and discussions of the effects of the most common nonidealities of class-E PAs: the limited loaded quality factor ($Q_{\mathrm {loaded}}$) of the series filter, switch ON-resistance, the limited quality factor of the dc-feed inductor, load mismatch-dependent switch conduction loss, and the limited negative voltage excursions (due to, e.g., the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and load–pull measurements of a class-E PA implemented in 65-nm CMOS technology. The PA provides 18.1-dBm output power and 72% efficiency at 1.4 GHz under nominal operating condition employing an off-chip matching network. [ABSTRACT FROM AUTHOR]

In this paper, a new plasma-based high-power microwave single-pole single-throw (SPST) switch is introduced and experimentally investigated. This switch is composed of a two-pole evanescent-mode cavity structure loaded with two gas discharge tubes over its posts. Since part of the energy required for the tubes ignition is supplied by the incoming electromagnetic waves, the switching mechanism is quasi absorptive. A prototype SPST switch at the frequency range of 2.8–3.9 GHz is fabricated and successfully examined over the power range of 2–20 W. With less than 1 dB of insertion loss, the ON/OFF isolation varies from 13 to 22 dB, depending on the input power. The measured switching time was on the order of tens of nanoseconds, and the input third-order intercept point that characterizes linearity was +53 dBm. Upon ignition, the microwave-sustained plasma in the switch operates in the $\alpha $ -discharge regime, ensuring that the switch performance is quite stable, with no degradation after long periods of operation. [ABSTRACT FROM AUTHOR]

This paper presents high-isolation single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) substrate integrated waveguide (SIW) mechanical switches in $V$ - and $W$ -bands. Four via holes with the proposed ring-and-cross etching patterns on the top side are placed in the middle of SIW path to block or pass the waves. As the ring-and-cross etching patterns being short-circuited, the via holes block the waves just like stockades do, in other words, turning the switch to OFF mode. And the ring-and-cross etching pattern makes the via holes invisible, turning the switch to ON mode. The $V$ - and $W$ -band SIW SPST and SPDT switches are designed and fabricated. The switches show the measured performances of better than 45-dB isolation for SPST and better than 50-dB isolation for SPDT, for $V$ -band operation, and a better than 50-dB isolation for both SPST and SPDT for $W$ -band operation. [ABSTRACT FROM AUTHOR]

In this paper, the capacitively coupled LC resonators with loaded p-i-n diodes are used to develop fixed-response filter-integrated single-pole double-throw (SPDT) switch. The filter-integrated on-state channel with reverse-biased p-i-n diodes can be designed and synthesized using the coupled-resonator filter theory, and the off-state channel with forward-biased p-i-n diodes exhibits high suppression. A 1-GHz filter-integrated SPDT switch with ripple bandwidth of 195 MHz is designed to demonstrate the proposed design concept. Measured results show that it has a low on-state insertion loss (IL) of 1.03 dB, a wide passband, high off-state suppression (OSS), high port-to-port isolation, and compact circuit size. Since both the properly misaligned resonant frequencies of LC resonators and weakly coupling between LC resonators also result in high suppression, a frequency-agile filter-integrated switchless SPDT switch without p-i-n diodes can be designed by using the varactor diodes to realize the corresponding capacitors. A frequency-agile filter-integrated switchless SPDT switch with constant 1-dB fractional bandwidth of 19.5% is also designed. Measured results show that its operating frequency can be tuned from 0.612 to 1.088 GHz with corresponding frequency tuning range of 58% and IL varying from 2.8 to 2.3 dB. Good return loss, high OSS, and port-to-port isolation can be also observed. [ABSTRACT FROM AUTHOR]

In this paper, the capacitively coupled LC resonators with loaded p-i-n diodes are used to develop fixed-response filter-integrated single-pole double-throw (SPDT) switch. The filter-integrated on-state channel with reverse-biased p-i-n diodes can be designed and synthesized using the coupled-resonator filter theory, and the off-state channel with forward-biased p-i-n diodes exhibits high suppression. A 1-GHz filter-integrated SPDT switch with ripple bandwidth of 195 MHz is designed to demonstrate the proposed design concept. Measured results show that it has a low on-state insertion loss (IL) of 1.03 dB, a wide passband, high off-state suppression (OSS), high port-to-port isolation, and compact circuit size. Since both the properly misaligned resonant frequencies of LC resonators and weakly coupling between LC resonators also result in high suppression, a frequency-agile filter-integrated switchless SPDT switch without p-i-n diodes can be designed by using the varactor diodes to realize the corresponding capacitors. A frequency-agile filter-integrated switchless SPDT switch with constant 1-dB fractional bandwidth of 19.5% is also designed. Measured results show that its operating frequency can be tuned from 0.612 to 1.088 GHz with corresponding frequency tuning range of 58% and IL varying from 2.8 to 2.3 dB. Good return loss, high OSS, and port-to-port isolation can be also observed. [ABSTRACT FROM PUBLISHER]

In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- \mu \textm high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( Lg = 0.2~\mu \text{m} ) with low R\mathrm{\scriptscriptstyle ON} {^\ast} C\mathrm{\scriptscriptstyle OFF} from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only 0.214 \times 0.19~\text mm^2 and 0.36 \times 0.19~ \text mm^2 , respectively. [ABSTRACT FROM AUTHOR]

In this paper, a GaAs absorptive single-pole double-throw (SPDT) RF switch and its application to a 2.4-GHz switched beamformer module are presented. The proposed absorptive SPDT RF switch features low-power consumption and low insertion loss with good output matching both in the on and off states. Specifically, the measured insertion loss in the on state is less than 1 dB, and the measured input and output return losses are both better than 11.2 dB from 1.9 to 2.6 GHz. The measured output return loss in the off state is better than 15 dB, and the measured isolation is better than 24.7 dB in the same frequency range. Two proposed absorptive SPDT switches are then employed to form an absorptive single-pole four-throw RF switch, and it is integrated with a miniaturized $4 \times 4$ Butler matrix using the integrated passive device (IPD) technology to achieve a compact 2.4-GHz switched beamformer module with a very low profile. Specifically, the module size is 4.9 mm $\times5$ mm with a thickness of only 0.4 mm. The IPD beamformer module is then used to realize a low-profile 2-D scanning antenna array, and 16 different beams in azimuth and elevation dimensions are successfully generated. [ABSTRACT FROM PUBLISHER]

This paper proposes a design technique for the implementation of a class- EM power amplifier (PA). Class- EM mode of operation has been proposed as an improved version of class-E in terms of efficiency and power gain, provided that the current fall time of switch is an appreciable portion of a period; the frequency of operation is high enough that the switching time of transistor can no longer be considered instantaneous. A novel approach for harmonic injection required for class- EM operation is proposed, followed by the system of equations and the design methodology governing the proposed circuit. As a proof of concept and verification of the proposed design method, a class- EM PA is designed and implemented in 0.25- \mu \textm gallium arsenide pHEMT technology. The fabricated class- EM PA operates at 2.4 GHz and delivers a power of 30 dBm to the load, with the power-added efficiency of 60% and a 14-dB power gain. [ABSTRACT FROM PUBLISHER]

In this paper, we show a new bandstop filter circuit topology. Unlike conventional bandstop filter circuit topologies, the new circuit topology has inter-resonator coupling structures. The presence of these inter-resonator coupling structures enables convenient switching from a bandstop to a bandpass filter. Using the new bandstop filter topology, this paper demonstrates a design of a frequency-agile bandstop-to-bandpass switchable filter. The filter is composed of tunable substrate-integrated cavity resonators and can be switched to have either a bandstop or bandpass response. Switching is achieved by turning on and off switches placed within the filter structure. A prototype of the proposed design is fabricated and the concept is verified experimentally. [ABSTRACT FROM AUTHOR]

A self-biased CMOS analog mixer for ultra-wideband (UWB) applications is presented in this paper. The proposed mixer is complementary and self-biased, and has lower power consumption, superior isolation, and larger bandwidth. The proposed low-power, down conversion mixer is designed and fabricated in UMC 0.18\mu \textm CMOS technology. The measurement results show that it can operate at UWB frequencies that range from 1 to 6 GHz. The proposed mixer provides a maximum conversion gain of 13 dB, −4.5 dBm of third-order input intercept point, and a minimum double sideband noise figure of 12 dB. The maximum values of the measured local oscillator LO-to-RF, RF-to-IF, and LO-to-IF isolations are 50, 45, and 52 dB, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, an efficient free-positioning wireless power transfer (WPT) system for charging multiple devices is proposed. For the system, a planar transmitting (Tx) coil that consists of a spiral coil and concentric multiple parallel loops and switchable impedance matching networks (IMNs) at a transmitter are developed. Using the Tx coil, mutual inductance between the Tx coil and the receiving (Rx) spiral coils is made uniform in the effective charging area. The parallel loops are placed in the interior of the Tx coil, and the magnetic field is enhanced and controlled by adjusting the space in each parallel loop. For optimal design of the coil, an analysis method using an equivalent circuit is explained in detail. It is found that the current of one loop of a parallel loop is more than the input current and negative current flows on the other loop, while the total current of each parallel loop is constant. An array of parallel capacitors with a switch as the switchable IMN is used for the maximum power transfer efficiency corresponding to the number of devices. The reflection coefficients of the fabricated WPT system are under −10 dB at 6.78 MHz, regardless of the number of devices and positions. The WPT system has the maximum power transfer efficiencies of 93% for two devices and simultaneously transfers uniform power to up to four devices with high efficiency. [ABSTRACT FROM PUBLISHER]

This paper presents a design methodology to drastically improve the hot-switching reliability of contact-type radio frequency microelectromechanical system (RF-MEMS) switches. In the proposed design, sacrificial contacts are placed in parallel with low-resistance contacts to significantly reduce the electric field across the latter. The lower field strength drastically reduces the contact degradation associated with field-induced material transfer. Theoretical and numerical modeling shows that the proposed protection scheme introduces minimal, if any, impact on the RF performance of the switch. To realize the protection scheme, we introduce a novel mechanical design that allows the correct protection actuation sequence to be realized using a single actuator and bias electrode. As a demonstration, several 0–40-GHz RF-MEMS switches are fabricated using a robust copper sacrificial layer technique. Compared with unprotected switches, the protected switch design exhibits over 100 times improvement in the hot-switching lifetime. In particular, we demonstrate a 100–150 million cycle lifetime at 1-W hot switching and 50 million cycles at 2-W hot switching before catastrophic failure, measured in an open-air lab environment. Further optimization of the structural design and contact materials is likely to further increase the hot-switching lifetime. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis of a novel high-pass filter/low-pass filter (HPF/LPF) switching concept. Since an HPF/LPF switching concept has a periodic structure, its equivalent circuit is almost the same as an LPF for the ON-state and is the same as an HPF for the OFF-state. The broadband isolation characteristics with low insertion loss can be achieved by designing its cutoff frequency. A three-stage single pole single throw InGaAs pseudomorphic high electron mobility transistor monolithic microwave integrated circuit switch based on the HPF/LPF switching concept is successfully demonstrated with an insertion loss of less than 1.6 dB and isolation of more than 82 dB below 6 GHz, with a size of 1.1 mm $\times \,\, 1.0$ mm. The RF performances are in good agreement with the theoretical calculations. The measured input power of 1-dB insertion loss compression, P1dB, and the measured third-order intercept point, IIP3, are 19 and 27.7 dBm, respectively, at 1.95 GHz. The measured ON-time is 5.5 ns without cable delay. The measured rise time is as fast as 1.4 ns. [ABSTRACT FROM AUTHOR]

Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65- and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of -\44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of -\44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. [ABSTRACT FROM PUBLISHER]

The recently introduced Class-EF power amplifier (PA) has a peak switch voltage lower than that of the Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. Consequently, soft-switching operation that minimizes power dissipation during off-to-on transition cannot be achieved at high frequencies. Two new Class-EF PA variants with transmission-line load networks, namely, third-harmonic-peaking (THP) and fifth-harmonic-peaking (FHP) Class-EF PAs are proposed in this paper. These permit operation at higher frequencies at no expense to other PA figures of merit. Analytical expressions are derived in order to obtain circuit component values, which satisfy the required Class-EF impedances at fundamental frequency, all even harmonics, and the first few odd harmonics as well as simultaneously providing impedance matching to a 50-\Omega load. Furthermore, a novel open-circuit and shorted stub arrangement, which has substantial practical benefits, is proposed to replace the normal quarter-wave line connected at the transistor's drain. Using GaN HEMTs, two PA prototypes were built. Measured peak drain efficiency of 91% and output power of 39.5 dBm were obtained at 2.22 GHz for the THP Class-EF PA. The FHP Class-EF PA delivered output power of 41.9 dBm with 85% drain efficiency at 1.52 GHz. [ABSTRACT FROM AUTHOR]

This paper presents two different types of high-power gallium–nitride (GaN) phase shifters designed for X-band (8–12 GHz), but offering good performance over a much wider band. The first is a 22.5^\circ switched-filter phase shifter, which has much wider bandwidth than is typically found with this configuration, while maintaining low insertion loss (<2 dB), good return loss (>11.15 dB), and an amplitude imbalance of less than 1.03 dB across X-band. The 1-dB compression point was higher than laboratory equipment was able to measure (>38 dBm) and the phase shifter monolithic microwave integrated circuit exhibited an input-referred third-order intercept point (IIP3) of 46.2 dBm. The second phase shifter is a novel design, which promises wide bandwidth (in our case, limited by the single-pole double-throw switch we have also designed), but which achieves decent insertion loss (5 dB), good return loss (better than 11 dB), and very low phase variation (1^\circ) across X-band, also with 22.5^\circ phase shift. It offers a 1-dB compression point of 30.1 dBm and an IIP3 of 46.3 dBm. The components for a 45^\circ differential phase shift using the same structure were also fabricated and verified with measurements. The high-power phase shifters have been fabricated in a 0.5-\mu\ m GaN HEMT process and were designed using an accurate customized switch field-effect transistor model. [ABSTRACT FROM PUBLISHER]

This paper presents a new symmetrical field-effect transistor (FET) model suitable for microwave switches. The model takes advantage of the inherent symmetry of typical switch devices, justifying a new small-signal model where all intrinsic model parameters can be mirrored between the positive and negative drain–source bias regions. This small-signal model is utilized in a new and simplified approach to large-signal modeling of these type of devices. It is shown that the proposed large-signal model only needs a single charge expression to model all intrinsic capacitances. For validation of the proposed model, small-signal measurements from 100 MHz to 50 GHz and large-signal measurements at 600 MHz and 16 GHz, are carried out on a GaAs pHEMT. Good agreement between the model and the measurements is observed under both small- and large-signal conditions with particularly accurate prediction of higher harmonic content. The reduced measurement requirements and complexity of the symmetrical model demonstrates its advantages. Further, supporting operation in the negative drain–source voltage region, the model is robust and applicable to a variety of circuits, e.g., switches, resistive mixers, oscillators, etc. [ABSTRACT FROM PUBLISHER]

This paper presents the circuit techniques to achieve superior linearity and isolation for a single-pole six-throw transmit/receive (T/R) switch designed for GSM/W-CDMA dual-band operation at 0.85–0.9 and 1.8–1.9 GHz. Implemented in a 0.18-\mum thick-film silicon-on-insulator (SOI) CMOS process, the switch employs an LC-tuned asymmetric topology for the transmit (Tx) and receive (Rx) branch to handle the high-power GSM transmitter requirement. The proposed design also features a switchable double LC-tank acting as a variable impedance block to relax the tradeoff among linearity, insertion loss (IL), and isolation. Feed-forward capacitors, ac-floating bias techniques, and floating-body SOI devices are utilized to further improve the linearity. The measured P-0.1\ {dB}, IL and Tx–Rx isolation in the lower and upper band are 37.2–35.6 dBm, 0.43–0.75 dB, and 45–37 dB, respectively. The proposed T/R switch design in SOI CMOS is an important building block toward more compact and lower cost RF frond-end modules, which integrate the switch, antenna tuning module, and control logic on the same chip. [ABSTRACT FROM AUTHOR]

This paper presents a gallium nitride (GaN)-based hybrid current-mode class-S (CMCS) power amplifier (PA) using a bandpass delta–sigma modulator (BPDSM) for a 955-MHz LTE signal. To enhance the drain efficiency of the CMCS PA, the chip-on-board (COB) technique, which can reduce the external parasitic components of the packaged transistor and allow fast switching operation at high frequencies by minimizing distortion of the pulse waveform, is adopted. Also, GaN Schottky barrier diodes are fabricated in-house to protect the switching transistor against the high negative voltage swing. The differential output filter and balun composed of lumped LC resonators are integrated at the back of the switching transistor to extract amplified LTE signal from the output rectangular waveform, and the fabricated CMCS PA is measured and analyzed at four different states of BPDSM according to the coding efficiency from different input power level to obtain higher power and efficiency. Finally, a cavity bandpass filter (BPF) is added to the output circuit for a more accurate reduction of the harmonics and out-of-band noise signals to enhance system efficiency. From the measured results for an 8.5-dB PAPR 3 G LTE 10-MHz input signal, the proposed CMCS PA has a maximum average output power of 37.61 and 30.78 dBm, and the resulting drain efficiencies of 33.3% and 38.6% with the drain voltage of 19 and 7 V, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low-loss and high Tx-to-Rx isolation single-pole double-throw (SPDT) millimeter-wave switch for true time delay applications. The switch is designed based on matching-network and double-shunt transistors with quarter-wavelength transmission lines. The insertion loss and isolation characteristics of the switches are analyzed revealing that optimization of the transistor size with a matching-network switch on the receiver side and a double-shunt switch on the transmitter side can enhance the isolation performance with low loss. Implemented in 90-nm CMOS, the switch achieves a measured insertion loss and Tx-to-Rx isolation of 1.9 and 39 dB at 60 GHz, respectively. The input 1-dB gain compression point is 10 dBm at 60 GHz, and the return loss of the SPDT switch ports is greater than 10 dB at 48–67 GHz. [ABSTRACT FROM PUBLISHER]

This paper presents the design considerations of a silicon-based transmit/receive (T/R) switch for microwave and millimeter-wave frequencies. Techniques for minimizing switch size and loss while increasing linearity are discussed. With the dedicated idea of the standing-wave concept, a combo design of a bandpass filter and switch, called the filtering switch, is introduced for the front-end system to achieve better performance in terms of low insertion loss, compact size, and good linearity simultaneously. Based on the proposed switchable artificial resonator, a standing-wave single-pole single-throw (SPST) and a single-pole double-throw (SPDT) filtering switches are designed and implemented for demonstration. Fabricated with a 0.18-\mu\ m SiGe BiCMOS process, the standing-wave SPST exhibits only 1.9-dB insertion loss and 18-dB isolation with a compact chip area of only 0.027 \ mm^2 at 50 GHz. The SPDT T/R switch exhibits 3.2-dB insertion loss, good stopband rejection, and 20-dB isolation with only 0.0675 \ mm^2 active chip area at 60 GHz. With the proposed standing-wave topology, a good linearity with the input 1-dB compression point (P1dB) of 21 dBm is obtained for both switches. [ABSTRACT FROM AUTHOR]

This paper presents passive integrated circuits for millimeter-wave transmitters and receivers implemented in a 45-nm CMOS silicon-on-insulator (SOI) process. The advantages of SOI over bulk CMOS are discussed for millimeter-wave passive circuits. First, a single pole double throw (SPDT) switch demonstrates a measured insertion loss of less than 1.7 dB at 45 GHz and third-order intermodulation intercept point (IIP3) of 18.2 dBm. Second, a double-balanced passive in-phase/quadrature (I/Q) mixer exhibits a conversion loss of 8.35 dB at 44 GHz and IIP3 of 15.5 dBm. At a fixed IF of 200 MHz, the minimum I/Q gain and phase imbalance is 0.25 dB and 1.9^\circ. The passive mixer and SPDT switch results demonstrate a record minimum insertion loss and linearity performance for the passive millimeter-wave circuits. [ABSTRACT FROM AUTHOR]

This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and simulated power-handling capability of 13.8 dBm at 60 GHz. The proposed SPDT switch demonstrates such superior performances and consumes a much smaller die area to those of other SPDT switches, and therefore has potential to be used in highly integrated 60-GHz CMOS radios. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage, low-power, low-noise, and ultra-wideband (UWB) mixer using bulk-injection and switched biasing techniques. The bulk-injection technique is implemented for a low supply voltage, thus resulting in low power consumption. This technique also allows for a flat conversion gain over a wide range of frequencies covering the full UWB band; this is a result of the integration of the RF transconductance stage and the local oscillator switching stage into a single transistor that is able to eliminate parasitic effects. Moreover, since the bulk-injection transistors of the mixer are designed to operate in the subthreshold region, current dissipation is reduced. A switched biasing technique for the tail current source, in place of static biasing, is adopted to reduce noise. The effects of modulated input signals, such as AM and FM, are simulated and measured to demonstrate the robustness of the switched biasing technique. The proposed mixer offers a measured conversion gain from 7.6 to 9.9 dB, a noise figure from 11.7 to 13.9 dB, and input third-order intercept point from -10 to -15.5 dBm, over 2.4 to 11.9 GHz, while consuming only 0.88 mW from a 0.8-V supply voltage. The chip size including the test pads is 0.62\,\times\,0.58 mm^2 using a 0.18-\mum RF CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a novel dual-band voltage-controlled oscillator (VCO) in a standard 0.18-\mu\m CMOS technology. With special design in the LC tank, the circuit exhibits two oscillation modes in different frequency bands. The frequency band selection is achieved by a switched coupled inductor with the tunable inductance and quality factor. This VCO can operate in a 10-GHz band with 7.6% tuning range and a 22-GHz band with 8% tuning range, while the core circuit draws a dc current of 8.44 mA from a 1.8-V supply voltage. The figures-of-merit at 10- and 22-GHz bands are -184.63 and -181.81 dBc/Hz, respectively. These performances are comparable with state-of-the-art dual-band LC-VCOs. [ABSTRACT FROM AUTHOR]

This paper presents an ultrafast wideband low-loss single-pole double-throw (SPDT) differential switch in 0.35 \mum SiGe bipolar technology. The proposed topology adopting current-steering technique results in a total measured switching time of 75 ps , which suggests a maximum switching rate of 13 Gb/s, the fastest ever reported at V-band. In addition, the switch exhibits an insertion loss lower than 1.25 dB and an isolation higher than 18 dB from 42 GHz to 70 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a 0.01–8-GHz 4\,\times\,4 switch matrix in 0.13-\mu\ m CMOS technology. A deep n-well series–shunt–series switch is chosen as the switching core, and the transistor sizes are optimized for low insertion loss and high isolation up to 8 GHz. Full electromagnetic analysis is also performed on the switching core to result in a compact design. The 4\,\times\,4 switch matrix shows a measured insertion loss of 2.0–3.3 dB and an isolation of 50–44 dB at 2–8 GHz with near-zero power consumption. The measured input P1~{dB} and IP3 are 8–10 and 26–30 dBm at 0.5–8 GHz. The switch matrix has very low dispersion with < \ 6-ps group-delay variation and can switch a 12.5-Gb/s signal with a bit error rate of < \10^-12. The design can be used in reconfigurable 0.01–8 GHz communication systems or as a crossbar switch matrix for data routing. [ABSTRACT FROM PUBLISHER]

This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a \ 0.18-\mu\ m CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, \Delta C of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -\ 117.6~\ dBc/Hz at 1-MHz offset from 5.8 GHz. [ABSTRACT FROM AUTHOR]