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This paper presents a rotatable cyclic Vernier digital-to-time converter (DTC) with 1.8 ps timing resolution on an 80 ns time scale. The proposed DTC features high timing resolution, and can be utilized in beam-steering arrays, which is infeasible for ordinary Vernier DTCs. The proposed DTC was implemented within a passive time-equivalent direct-sampling ultra-wideband impulse-radio radar system and was fabricated in 65 nm CMOS technology. This radar system is capable of quantizing direct-sampled impulse waveforms to provide full degrees of freedom for backend digital signal processing. The measured differential nonlinearity/integral nonlinearity of the DTC was +4.6/−3 and 12.4/−9.4 where the LSB was 1.8 ps, and the total power consumption was 133 mW. Also, a new method for localization between wireless sensor nodes of equivalent-time direct-sampling radar is presented in this paper; this method can theoretically achieve resolution as high as that of regular radar. [ABSTRACT FROM PUBLISHER]

Based on time-variant behavior of metal-oxide–semiconductor field-effect transistors in large-signal operations, harmonic translations and their mutual effects are analyzed. Large amplitudes at terminal voltages of these transistors push them into different regions of operation. In this paper, harmonic translations are derived as a result of such changes in operation region of transistors. Operation in triode region for a portion of oscillation cycle results in iterative harmonic translations between fundamental frequency and second harmonic. They boost each other constructively for significantly stronger oscillation, more second harmonic output power, and enhanced dc-to-RF efficiency. Based on this analysis, a 215-GHz signal source, implemented in a TSMC 65-nm CMOS LP is presented. The proposed oscillator achieves a maximum output power of 5.6 dBm and a dc-to-RF efficiency of 4.6%. The measured phase noise is −94.6 dBc/Hz at 1-MHz offset. The proposed oscillator occupies only 0.08 mm2 of chip area. [ABSTRACT FROM PUBLISHER]

Impedance translation using passive N-path mixers has been used to achieve local oscillator (LO)-defined series bandstop and shunt bandpass filtering. In this paper, we generalize N-path filtering using a correlator-based approach and propose N-path passive mixers driven by orthogonal sequences. Such sequence-driven N-path filters can potentially reject or select signals based on their properties in the spectral, spatial, and code domains. Specifically, a Walsh-function (WF) sequence (WF-seq)-based N-path shunt filter is implemented, demonstrating the feasibility of shunt bandstop filtering using LO sequences other than nonoverlapping pulses. The WF-seq approach enables reconfigurable concurrent filtering at two different frequencies with shunt operation avoiding penalties due to the switch drive overlap. A 65-nm CMOS implementation achieves 20-dB rejection at one frequency and 14-dB rejection concurrently at two frequencies between 0.3 and 1.4 GHz. The reconfigurable bandstop filter is implemented using analog gyrators and consumes 35–62.5 mW and achieves 2.9-dB noise figure and −2.5–5-dBm IIP3. [ABSTRACT FROM AUTHOR]

This paper presents a low noise figure (NF) and high gain super-regenerative receiver (SRR) with coupled networks for portable millimeter-wave (mm-wave) imaging systems. Compared with the previous SRR designs, this paper presents a novel SRR structure comprising of two oscillators coupled by a serial resonator, which consists of the inductors and capacitors. Due to the coupled oscillators, the gain of the SRR is significantly improved and the NF of the SRR structure is reduced by 3 dB simultaneously. These benefits lead to a high-sensitivity SRR at mm-wave frequency. The circuit is realized in 65-nm CMOS process with a core area of 0.06 mm2. Measured results show that the receiver can detect −84-dBm minimum input power with 541-MHz integration bandwidth (BW). It has a noise-equivalent-power of 0.615 fW/(Hz), a NF of 7.52 dB, a BW of 3.5 GHz, and a power consumption of 8.1 mW. With frequency calibration procedure, these performances show the proposed chip meets portable imaging system requirement. [ABSTRACT FROM AUTHOR]

Integrated antennas have become the attractive solution as the electromagnetic (EM) interface for mm-Wave and terahertz ICs. However, on-chip antennas lying at the interface between two different dielectrics (such as air and substrate) can channel most of its power into multiple nonradiative surface-wave modes, reducing efficiency drastically. In this paper, we consider the following problem: given a dielectric substrate, what is the theoretical optimal 2-D surface-current configuration that collectively suppresses surface waves and maximizes radiation efficiency with the desirable radiation pattern? This paper also discusses demonstrative examples of a circuit-EM codesign approach to realize the approximation of such current configurations. Measurement results of radiating arrays in CMOS at mm-Wave frequencies (250–300 GHz) are presented and compared with theoretical predictions. [ABSTRACT FROM PUBLISHER]

We present a novel method of maximizing the output power and efficiency of millimeter-wave and terahertz signal sources, which are based on the push-push topology. In this method, the common-mode impedance of a differential Colpitts oscillator operating in the odd mode is maximized by introducing a fixed-valued capacitor ( Cr ) at the common-base node. This capacitor is designed to introduce a common-mode parallel resonance at the desired second harmonic, boosting the common-mode voltage swing and subsequently its output power. The proposed method is analyzed using a high-frequency even-mode $\pi $ -model. Analytical expressions of input impedance are derived and are used for calculating the common-mode resonance frequency and the required value of Cr . Two 0.3-THz voltage-controlled oscillators (VCOs) are implemented in a 130-nm SiGe BiCMOS process. It is shown that by using the proposed technique, the output power is improved by more than 6 dB, as compared with the conventional approaches. The implemented VCOs work from 292 to 318 GHz and 305 to 327 GHz, delivering a peak output power of 0.6 and 0.2 dBm, with a dc-to-RF efficiency of 0.8% and 0.9%, and can achieve a phase noise of −108 and −105 dBc/Hz at 10-MHz offset, respectively. As compared with the prior state-of-the-art Si-based tunable signal sources and arrays working above 270 GHz, this paper shows the lowest phase noise and the best figure-of-merit, while having an excellent output power, a tuning range, and a dc-to-RF efficiency. [ABSTRACT FROM PUBLISHER]

This paper presents a balanced frequency doubler with 6.5-dBm peak output power at 204 GHz in 130-nm SiGe BiCMOS technology ( fT/f\max =210 /250 GHz). To convert the single-ended input signal to a differential signal for balanced operation, an on-chip transformer-based balun is employed. Detailed design procedure and compensation techniques to lower the imbalance at the output ports, based on mixed mode S parameters are proposed and verified analytically and through electromagnetic simulations. The use of optimized harmonic reflectors at the input port results in a 2-dBm increase in output power without sacrificing the bandwidth of interest. The measured conversion loss of the frequency doubler is 9 dB with 6-dBm input power at 204-GHz output. The measured peak output power is 6.5 dBm with an on-chip power amplifier stage. The 3-dB output power bandwidth is measured to be wider than 50 GHz (170–220 GHz). The total chip area of the doubler is 0.09 mm2 and the dc power consumption is 90 mW from a 1.8-V supply, which corresponds to a 5% collector efficiency. [ABSTRACT FROM PUBLISHER]

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18- \mu \textm SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of −97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz–10 MHz is 2.05° rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm $\times$ 1.86 mm. [ABSTRACT FROM PUBLISHER]

This paper introduces a system-level approach to develop the first-ever fully discrete-time (DT) superheterodyne receiver (RX) for Internet-of-Things applications, such as Bluetooth low energy (BLE). It exploits fast switching speed and low internal capacitances of deep-nanoscale CMOS devices to realize a high intermediate-frequency (IF) architecture based on switched-capacitor-based charge-domain bandpass filtering. Power consumption is minimized by aggressively reducing the size of MOS devices and judiciously applying a sampling-rate decimation. The resultant increase in the flicker noise is mitigated by placing the IF frequency beyond the flicker corner frequency. Likewise, the decimation-induced aliasing is mitigated by DT filtering of preceding stages. The BLE RX is fully standard-compliant and achieves a record-low-power consumption of 2.75 mW (including its local oscillator) while delivering the state-of-the-art performance: 6.5-dB noise figure and −19-dBm third-order input intercept point, with a direct antenna connection and thus without the typical external bandpass filters. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS transceiver IC for a single-antenna frequency-modulated continuous wave (FMCW) radar. Since transmitter (Tx) leakage is critical in a single antenna radar with CMOS technology, a comprehensive leakage canceling technique is proposed. It is able to cancel all the leakages caused by antenna reflection, asymmetry of a balanced structure, and lossy substrate without additional power or area. Even-order harmonic leakages from the power amplifier (PA) are also reduced by an even-harmonic filter, which is implemented simply by removing the real ground from the symmetrical point of the PA output transformer. Matching networks are simplified by using a modified coupler structure. A low-noise combining amplifier is used to make the combining circuit compact. As a result, the transceiver achieves the output power of −1.6 dBm, the phase noise of −105.44 dBc/Hz at 1MHz offset, the receiver (Rx) gain of 15.3 dB, and the noise figure of 11.6 dB. Tx leakages are canceled so that the isolation between Tx and Rx is 47.3 dB. The chip consumes 74.1 mA from a 1.5-V power supply. Despite the high integration level, the chip area including pads is 1.7 mm $\times $ 0.9 mm. A {K} -band FMCW radar module with a single antenna is implemented with this chip. [ABSTRACT FROM PUBLISHER]

A 28 nm CMOS software-defined transceiver (SDTRX) enabling high-speed data (HSD) streaming, including ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024-QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the-art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a digital-to-analog converter-based TX and a smart phase-locked loop system. It operates over 0.4–1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple transmitter (TX) to receiver (RX) loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia system-on-chip and is, to the authors’ knowledge, the first reported transceiver front-end to enable true HSD streaming within home cable networks. [ABSTRACT FROM AUTHOR]

This paper presents an injection-locked 65-nm CMOS circuit that upconverts and power amplifies baseband signals to RF. The circuit delivers an RF output power of 28.7 dBm, with a power gain and maximum power added efficiency (PAE) of 20.6 dB and 68.1%, respectively. Both AM–AM-conversion and AM–PM-conversion are low, less than 1 dB and 1°, respectively, resulting in an EVM of 4.7% for Long Term Evolution (LTE) and 4.1% for WCDMA signals. The circuit provides an average output power of 20.3 dBm for LTE, with a PAE of 44.1%, and for WCDMA, the average output power is 23.8 dBm with a PAE of 55.6%. Supply modulation improves power back-off efficiency and the voltage range is from 540 mV to 3 V. The spectral mask for LTE signals has a worst case ACLR of 33.2 dBc using predistortion. For WCDMA signals, ACLR1 is 39.9 dBc and ACLR2 is 47.2 dBc, both values worst case and using baseband predistortion. This performance is achieved by introducing a cross-coupled cascode topology, and supporting theory and simulations are presented. The startup loop-gain and small-signal equivalents are derived, a power dissipation analysis is performed, and the injection circuit is analyzed to investigate the AM–PM behavior. Analysis and simulations show that, compared to conventional cascode amplifiers, PAE is improved by 24% (15% points). The circuit is implemented in an STM 65-nm CMOS process and occupies an area of $1.0 \times 0.53$ mm2. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an interpolation-based low noise and variable gain cell (IBA-cell) in the 60-GHz band, using a 40-nm CMOS technology. The interpolation-based gain cell is designed for an innovative analog beamforming front end, where the array pattern is not only controlled in the phase domain, but also wins the flexibility in the magnitude domain. The circuit specifications are first derived for the application at 60 GHz. Techniques to combine low noise figure (NF) with variable gain tuning are presented focusing on the NF and linearity (IIP3) on the example of a 60-GHz low noise amplifier and variable gain amplifier. Subsequently, the design and measurement of the whole gain cell (IBA-cell) integrated into a single chip are reported with the technique of a cross-coupled feedback loop to reduce the phase variations over the gain tuning states and enhance the variations of IIP3. The IBA-cell achieves 15.8-dB maximum gain and 6.5-dB NF at 57 GHz with the gain tuning range from −2 to 15.8 dB and IIP3 varying from −11.3 to −16 dBm over the gain control range. The IBA-cell consumes a dc power of maximum 54 mA from 1.1 V. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE's frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD's balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18-μm SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6-3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes. [ABSTRACT FROM AUTHOR]

This paper proposes the use of a high-power stacked output stage for a current-based in-phase/quadrature (I/Q) direct digital to RF modulator (DDRM) in bulk CMOS. The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (PSAT) of 25 dBm and a peak output power (Pout) of 21 dBm at 1-GHz carrier frequency ( fc). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (ηsys), respectively. In addition, it achieves 11.5% ηsys with a -30.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. The WLAN signal is transmitted at 12-dBm average Pout, and at 1-GHz fc with 8.73-dB peak to average power ratio (peak Pout of 20.73 dBm). [ABSTRACT FROM AUTHOR]

This paper presents the first wirelessly synchronized multichip array (WSMA) in 65-nm CMOS. The proposed architecture makes use of a central wireless signal to synchronize an mm-wave array, eliminating the need for connecting wires between the array elements. Wireless injection locking of a single chip is successfully demonstrated, and a 3-dB linewidth of 400 Hz at a carrier frequency of 50 GHz is achieved (stability ratio of 8 ppb). In addition, a two-element WSMA with an array aperture greater than 20 wavelengths is demonstrated using the proposed transceiver architecture. The reported transceiver includes a receiving on-chip antenna, a low-noise amplifier, an injection-locked voltage-controlled oscillator, a buffer amplifier, an in-phase/quadrature generator, a phase shifter, a power amplifier, and a transmitting on-chip antenna. The chip is fabricated in a 65-nm CMOS process and occupies an area of 1.7 mm $\times 3.8$ mm. This paper sets the foundation for increasing the array aperture through wireless injection locking, extending traditional array systems into the high-resolution, narrow-beamwidth regime. [ABSTRACT FROM PUBLISHER]

This paper presents a wideband 2\times13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based all-digital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides more than 21-dBm RF output power within a frequency range of 1.36–2.51 GHz. The peak RF output power, overall system, and drain efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below -160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and local oscillator leakage of -65 and -68 dBc, respectively. It could be linearized using either of the two digital predistortion (DPD) approaches: a memoryless polynomial or a lookup table. Its linearity is examined using single-carrier 4/16/64/256/1024 quadrature amplitude modulation (QAM), as well as multi-carrier 256-QAM orthogonal frequency-division multiplexing baseband signals while their related modulation bandwidth can be as high as 154 MHz. Employing DPD improves the third-order intermodulation product (IM3) by more than 25 dB, while the measured error vector magnitude for a “single-carrier 22-MHz 64-QAM” signal is better than -28 dB. [ABSTRACT FROM AUTHOR]

This paper presents a highly linear and power back-off efficiency-enhanced Doherty power amplifier (PA) fully integrated into CMOS. The proposed Doherty PA employs a transformer-based quadrature signal generator, multigated transistors (MGTRs) in the main PA, Class-C mode auxiliary PA, and synthesized transformer-based Doherty parallel output network with the second-harmonic control circuits. An on-chip 8-port transformer-based quadrature signal generator is designed within a single transformer footprint ($340\,\,\mu \text{m}\,\,\times 340\,\,\mu \text{m}$) and provides 0°/−90° differential signals to the main/auxiliary PAs. The MGTR in the main PA is implemented using four transistors with different sizes and biases to generate and extend a near-zero $\text {g}_{\text {m3}}$ operation region. Moreover, an on-chip transformer-based Doherty parallel output network with the second-harmonic control circuits shows higher passive efficiency compared with a conventional Doherty parallel output network and provides low second-harmonic loads to the main/auxiliary PAs. Both the proposed MGTR in the main PA and the second-harmonic control circuits in the main/auxiliary PAs suppress the third-order intermodulation distortion of the Doherty PA. This results in a substantial linearity improvement of the Doherty PA, which can support high-order modulation signals and reduce or even eliminate the need for digital predistortion (DPD). As a proof-of-concept design, a 5.8 GHz Doherty PA is implemented in a standard 55 nm bulk CMOS process. The proposed Doherty PA exhibits 27.2 dBm saturated output power with 24.5% power-added efficiency (PAE) at 5.8 GHz. The measured error vector magnitude with 40/80 MHz of 64-QAM/256-QAM is 2.5%/1.8% with 20.7/17 dBm average output power, 9.5%/5.3% average PAE, and −33.2/−36.3 dBc adjacent channel leakage ratio without any DPD. [ABSTRACT FROM AUTHOR]

A flip-chip-assembled W-band receiver composed of a 90-nm CMOS chip and an integrated-passive-device (IPD) carrier is presented in this paper. The chip which integrates a low-noise amplifier, a single-sideband mixer, a frequency doubler (FD), and a wide-band variable-gain amplifier, is flip-chip packaged to the IPD carrier through a low-loss interconnect. The simulated loss of the interconnect without any compensation network is only 0.95 dB at 94 GHz. The FD can provide differential output without any additional lossy balun required, effectively increasing the FD output power, and hence relaxing the local oscillator generation circuit design. The experimental results show that the proposed packaged receiver can provide a variable gain from 11.3 to 48.2 dB, while having an input 1-dB compression point from −43.7 to −29 dBm as the RF frequency is 90 GHz. The intermediate bandwidth and minimum noise figure can be 1.0 GHz and 7.8 dB, respectively. The proposed receiver only consumes 73.9 mW from a 1.2-V supply. As compared with prior works, the proposed receiver exhibits higher gain, lower noise, and lower power dissipation even though a less-advanced 90-nm CMOS technology is adopted. To the best of the authors’ knowledge, this is the first W-band CMOS receiver assembled on an IPD carrier reported thus far. [ABSTRACT FROM AUTHOR]

A time-division duplex (TDD) transmit/receive (T/R) millimeter-wave (mm-wave) front-end comprises a power amplifier (PA), a low-noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this paper, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure. The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated using 45 nm CMOS silicon-on-insulator that includes a high power, four-stack-based PA and an inductively source-degenerated cascode-based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak power added efficiency of 28%, while the LNA achieves NF of 3.2 dB. The overall chip area is 0.54 mm2, including pads. [ABSTRACT FROM AUTHOR]

In this paper, an ultra-compact low-pass filter (LPF) with wide stopband is proposed based on lumped L-C structure in through-silicon via-based 3-D stacked configuration. The spiral inductor (L), interdigital capacitor (C), and the proposed LPF are theoretically analyzed based on parasitic parameters and equivalent circuit models. To evaluate the characteristics, the proposed LPF is simulated by HFSS, fabricated with CMOS-process-compatible technology, and measured with de-embedding method. Simulation and measured results are in good agreement. Compared with the other literature, the proposed LPF has the most compact size of $0.028\lambda _{g }\times 0.017 \lambda _{g}$. ($\lambda _{g}$ is the guide wavelength at $f_{c}$.) With the cutoff frequency at 10.05 GHz, the filter has an insertion loss of 0.14 dB and reflection loss over 13 dB from dc to 9 GHz in the passband. The suppression levels are better than 20 dB from 20.4 up to 40 GHz in the stopband. [ABSTRACT FROM AUTHOR]

Distributed LC resonator and resistively distributed resonator belong to the same technique used to extend the locking range of injection-locked frequency divider (ILFD). ILFD using the former resonator often has one locking range, and extension of locking range is attributed to oscillation frequency increment. This paper measures and analyzes the input sensitivity of a CMOS ILFD with a resistively distributed resonator and with the divide-by-3 and divide-by-2 functions, and the input sensitivity shows a wide single-band locking range. The fabricated 0.18- $\mu \text{m}$ CMOS ILFD is made of a pair of cross-coupled n-type transistors, two direct-injection MOSFETs, and a resistively dual-resonance resonator. The wide single-band locking range of the designed ILFD is owing to the overlapped locking ranges, and it is verified by the smooth tuning range without forbidden region and nonoverlapped locking ranges measured on the same chip with the unbalanced injection structure. The frequency tuning is obtained with large tank resistance, which also reduces the frequency tuning hysteresis effect. [ABSTRACT FROM AUTHOR]

In this paper, we present a dual-mode power harvesting system for millimeter-sized biomedical implants that are immune to the variation of wireless link parameters and loading. The design includes a multistage full-wave voltage rectifier, a power management unit, and a low dropout voltage regulator. Depending on the received RF power level and the required power by the load, power delivery is conducted in a continuous or duty-cycled mode. The system is fabricated in 180-nm silicon on insulator (SOI) CMOS technology with an active area of 2.56 mm2 including an on-chip coil. RF power is transferred to the chip from a $2\times 2$ cm2 coil through 10 mm of air at 434 MHz. The efficiency of the designed wireless link, which is the power transfer efficiency from the external coil to the on-chip coil, reaches up to 0.68% (−21.7 dB) at 10-mm separation through air. Keeping the transmitted RF power below 24 dBm, the system can provide a 1.08-V dc voltage for resistive loads larger than 20 $\text{k}\Omega $ continuously over time. When the harvested power is not enough to drive the load continuously, the system operates in the duty-cycled mode. Measurement results show that the system can drive a 1- $\text{k}\Omega $ load in the duty-cycled mode when the transmitted power level is 15 dBm. [ABSTRACT FROM AUTHOR]

This paper presents a 28-GHz common-leg phased-array front-end in 45-nm CMOS silicon on insulator with transmit and receive capabilities. The design alternates cascode amplifiers with passive switched- $LC$ phase-shifter cells to result in 5-bit phase control with an rms phase and gain error <4° and <0.8 dB, respectively, at 24–30 GHz, over 32 phase states. The front-end has 2- and 3-bit variable gain amplifiers with 7.5-dB total gain control, without affecting the system noise figure (NF). Two low-loss high-linearity single-pole double-throw switches are used to switch between transmit and receive modes. In the receive (Rx) mode, the measured gain, NF, input 1-dB compression point (P1dB), and input third-order intercept point are 16 dB, 3.7 dB, −15 dBm, and −7 dBm, respectively, with 54-mW dc power consumption. In the transmit (Tx) mode, measurements show 16.5-dB gain, an output P1dB of 8 dBm, and an output IP3 of 16 dBm with 100-mW dc power consumption. The error-vector magnitude and adjacent-channel-power-ratio measurements demonstrate quadrature phase-shift keying, 16-quadrature amplitude modulation (QAM), 64-QAM, and 16-QAM orthogonal frequency-division multiplexing modulations with several symbol-rates reaching up to 8 Gb/s data-rate for both the Rx and Tx modes at 2- and 5-dB back-off. The application areas are in fifth-generation phased arrays requiring high-linearity receivers and using external front-end modules for added transmit power. [ABSTRACT FROM AUTHOR]

A single-output, band selecting interposer is designed to combine three identical all-digital CMOS transmitter (Tx) chips. The open-drain CMOS Txs are flip-chip connected to the primary windings of three frequency selecting transformers realized on a single PCB interposer. The secondary windings of the three transformers are connected in series and they share a single output. Across 0.4 to 4 GHz, a peak power higher than 22.9 dBm is achieved collectively by the three sub-Txs with a drain efficiency (DE) better than 25%. The peak powers/DE of the three sub-Txs are 28.6 dBm/50%, 27.4 dBm/49%, and 24.7 dBm/34%, at 0.85, 2.1, and 3 GHz, respectively. This paper further demonstrates that the band selection can be achieved via reconfiguring the CMOS inverse Class-D switching power amplifiers. As demonstrated via continuous wave and 64-quadratic-amplitude modulation, WLAN, and LTE modulation tests, the reconfigurable Tx package exhibits high power and efficiency across all supported bands. [ABSTRACT FROM AUTHOR]

Nonreciprocal components, such as isolators and circulators, are critical to wireless communication and radar applications. Traditionally, nonreciprocal components have been implemented using ferrite materials, which exhibit nonreciprocity under the influence of an external magnetic field. However, ferrite materials cannot be integrated into IC fabrication processes and, consequently, are bulky and expensive. In the recent past, there has been strong interest in achieving nonreciprocity in a nonmagnetic IC-compatible fashion using spatio-temporal modulation. In this paper, we present a general approach to nonreciprocity based on switched transmission lines. Switched transmission lines enable broadband, lossless, and compact nonreciprocity and a wide range of nonreciprocal functionalities, including nonreciprocal phase shifters, ultra-broadband gyrators and isolators, frequency-conversion isolators, and high-linearity/high-frequency/ultra-broadband circulators. We present a detailed theoretical analysis of the various nonidealities that impact insertion loss and provide design guidelines. The theory is validated by experimental results from discrete-component-based gyrators and isolators and a 25-GHz circulator fabricated in a 45-nm SOI CMOS technology. [ABSTRACT FROM AUTHOR]

An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1–10.6-GHz band efficiently for high data-rate short-range wireless connectivity even in overcrowdedness of the frequency spectrum. Frequency synthesizers tailored to the UWB-based CR should provide wide lock range, multiple frequency bands, and low in-band spurs while consuming low power. This paper investigates a low power, wide lock range, integer-N frequency synthesizer approach with 132-MHz frequency step and 57 subbands in the UWB band. Two-stage supply regulated differential ring oscillator provides linear and wide tuning range with voltage controlled oscillator gain of 22.5 GHz/V and low supply-noise sensitivity. A modular true-single-phase-clock programmable divider achieves wide operating frequency range of 0.1–6.5 GHz and power efficiency of 6.25 GHz/mW by compensating leakage current at the dynamic nodes with conditional latches. Replica-based digital calibration reduces the current mismatch of the charge pump to <1% for low in-band reference spurs of <−60 dBc. A frequency synthesizer test chip was fabricated in 65-nm complementary metal–oxide–semiconductor technology. The active area of the frequency synthesizer is 0.12 mm2. It achieves <−30-dBc integrated phase noise and enables the UWB-based CR to get bit error rate of <10−3 while consuming <−10.1 mW. [ABSTRACT FROM AUTHOR]

This paper presents the temperature effect on a Ku-band NMOS common-gate low-noise amplifier (CG-LNA). The temperature characteristics of an NMOS transistor and spiral inductors are obtained over the temperature range from 253 to 393 K. These results show that the optimal bias condition minimizes the transconductance and drain current temperature variations. Based on these results, a current-reused CG-LNA with good temperature performance is designed. At ambient temperatures, the CG-LNA has a measured power gain of 10.3 dB and a noise figure (NF) of 4.3 dB at 15.2 GHz, while consuming 4.5 mA from a 1.3-V power supply. When the temperature varies from 253 to 393 K, the CG-LNA has a power gain variation of 3 dB, NF variation of 2 dB, and dc power consumption variation of 11.9%. This paper is the first to report the temperature effect on Ku-band CG-LNAs. [ABSTRACT FROM AUTHOR]

Editorial. Discusses articles relating to microwave theories and techniques. Survey paper on dominant architecture for low-cost integrated radios; Discussion on Ka-band direct digital receiver; Discussion on the reliability issues for complementary metal oxide semiconductor voltage-controlled oscillators; Active predistortion technique to boost linearity and efficiency of high-power amplifier.

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE. [ABSTRACT FROM PUBLISHER]

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different junction area are fabricated using a standard NMOS transistor in 90-nm CMOS technology having a width of 5- and 20- \mu \text m , respectively. From the experimental characterization emerges that the breakdown voltage of the source/drain to bulk diodes is 12.4 V, whereas excess noise ratios (ENRs) of 20 dB (5- \mu \text m source) and of 25 dB (20- \mu \text m source) are observed at 24 GHz for a current density of about 0.14 mA per square micrometer. Finally, a theoretical explanation of the observed behaviors is proposed by means of an equivalent circuit. The developed noise source can be used in a CMOS system-on-chip (SoC) for a variety of applications ranging from the built-in self test (BIST) of the RF chain to the calibration of fully integrated microwave radiometric sensor. [ABSTRACT FROM PUBLISHER]

This paper discusses the design of a batteryless wirelessly powered ultra-wideband (UWB) system-on-a-chip (SoC) tag for area-and-volume-constrained localization applications such as insect tracking. Key challenges for wirelessly powered operation at 10-m range include the design of high-sensitivity rectifiers and low-voltage high-efficiency UWB transmitters (TX). An antenna-rectifier co-design methodology is presented for sensitivity optimization under area constraints. A 300-nA power management unit (PMU) and low-voltage (0.8-V) UWB TX increases tag operating range by ensuring high rectifier sensitivity under loaded conditions and reducing required rectifier output voltage. The rectifier, PMU, and UWB TX are integrated in 65-nm CMOS, and the rectifier demonstrates state-of-the-art -\30.7–dBm sensitivity for 1-V output voltage with only 1.3 \cm^2 antenna area, representing a 2.3\,\times improvement in sensitivity over previously published work, at 2.6\,\times higher frequency with 9\,\times smaller antenna area, translating into a 50% longer range at the same frequency. The 0.8-V UWB TX consumes 64 pJ/pulse at 28-MHz pulse repetition rate and achieves 2.4 GHz -\10-dB bandwidth. Wireless measurements demonstrate sub-10-cm range resolution at ranges exceeding 10~m. Tag measurements in typical office environments demonstrate 20-m-range RF-energy harvesting with 36-dBm effective-isotropic radiated power in the 2.4-GHz ISM band. [ABSTRACT FROM PUBLISHER]

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of \0.12 mm^2. Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving. [ABSTRACT FROM PUBLISHER]

In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm^2 and 0.24 mm^2, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a high power efficient broad-band programmable gain amplifier with multi-band switching. The proposed two stage common-emitter amplifier, by using the current reuse topology with a magnetically coupled transformer and a MOS varactor bank as a frequency tunable load, achieves a 55.9% peak power added efficiency (PAE), a peak saturated power of +11.1 dBm, a variable gain from 1.8 to 16 dB, and a tunable large signal 3-dB bandwidth from 24.3 to 35 GHz. The design is fabricated in a commercial 0.18-\mum SiGe BiCMOS technology and measured with an output 1-dB gain compression point which is better than +9.6 dBm and a maximum dc power consumption of 22.5 mW from a single 1.8 V supply. The core amplifier, excluding the measurement pads, occupies a die area of 500 \mu\ m\times \ 450~\mu\ m. [ABSTRACT FROM AUTHOR]

This paper presents a single-chip CMOS multi-standard frequency synthesizer for global system for mobile communications (GSM)/enhanced data rate for GSM evolution (EDGE) and long-term evolution (LTE) applications. Low phase-noise characteristics are achieved both in-band and out-of-band through a voltage-and-digitally controlled oscillator (VDCO) and digital calibration blocks. The proposed hybrid phase-locked loop (PLL) has two feedback loops. One is the main loop of the analog PLL and the other is a digital feedback loop used for polar modulation and digital calibrations. The digital feedback loop, nested inside the PLL, linearizes and accurately controls the tunable characteristic of the VDCO, which is important for the polar modulation. In the GSM/EDGE mode, the PLL has a 0.79^\circ root-mean-square (rms) phase error and the measured phase noise is -\162.5 dBc/Hz at a 20-MHz offset from an 824-MHz carrier. In the LTE mode, the measured local oscillator rms jitter is 218 fs while the PLL consumes 26.4 mW. The resulting figure of merit of the proposed PLL is -\239 dB, which is superior to recent multi-standard PLLs. This multi-standard hybrid PLL is implemented in a 65-nm CMOS technology and occupies \0.72 mm^2. [ABSTRACT FROM PUBLISHER]

A new equivalent-circuit model and parameter-extraction method for six-port M:N on-chip transformers and baluns are presented in this paper. All of the elements in the proposed model are extracted directly by S-parameters based on full-wave electromagnetic (EM) simulations. Series branches in the model are used to capture the characteristics of the primary and secondary windings. The shunt impedance networks on the terminals represent the substrate loss. The magnetic coupling effects of windings are denoted by six mutual inductances. The electrical coupling effects are represented by mutual capacitances. In this paper, we have developed a parameter-extraction methodology for mutual inductances of six-port transformers. The proposed model and parameters extraction methodology are verified with a number of six-port transformers with different turn ratio by measurements and full-wave EM simulations. The proposed model shows good agreement with measured data over a wide frequency band. [ABSTRACT FROM PUBLISHER]

In this paper, we introduce the concept of near-field synchronization as an efficient, scalable, and robust method to synchronize a 2-D array of mutually coupled oscillators for beam-forming at frequencies above f\max of a technology. The method employs an array of on-chip sense antennas to probe electromagnetic near-fields of the on-chip radiators. These sense antennas are then coupled to each other appropriately through a network that establishes the synchronized state as the lowest energy state. A circuit-electromagnetic co-design methodology is employed to demonstrate beam-steering near 200 GHz with a synchronized 2\,\times\,2 array. Each element of the array is a traveling-wave oscillator with the nonlinear active devices selectively radiating its second harmonic through the same electromagnetic structure. The beam-pattern can be varied by more than 70^\circ in both azimuth and elevation. The chip is realized in 65-nm bulk CMOS. [ABSTRACT FROM PUBLISHER]

This paper presents a CMOS broadband programmable gain active balun (PGAB) that demonstrates seven digitally controlled gains with 0.5-dB gain steps separately for plus and minus output ports. The PGAB was designed and fabricated in a 130-nm RFCMOS process. For the maximum gain state, the measured gains of the plus and minus ports are 0.0 and 1.1 dB at 2 GHz. The operating frequency range is from 1.0 to 8.0 GHz by 0.3-dB gain step error, and it is from 1 to 13.0 GHz by 3-dB gain attenuation. For the maximum gain state, the measured amplitude imbalance and phase imbalance from 1 to 16 GHz are less than 1.4 dB and 4.1^\circ, respectively. The measured input return losses are better than 13.5 dB, and the output return losses are better than 18.5 dB for all controlled gain states from 1 to 16 GHz. The measured IP1dB at 7 GHz is 6.1 dBm. The measured noise figures for the plus and minus ports from 2 to 14 GHz are less than 11.2 and 10.2 dB, respectively. The supply voltages are 3.0 and 1.5 V, and the measured power consumption is 93 mW. The core area of the fabricated integrated circuit is 0.38 mm\,\times\,0.36 mm. [ABSTRACT FROM AUTHOR]

The downscaling of CMOS processes has led to devices with an impressive RF performance. Advanced nanoscale RF MOSFETs present very high transit frequency, which can be traded off with lower power consumption, by shifting the operating point towards the weak inversion (WI) regime. This paper explores whether the simple RF schematics and models used in strong inversion remain valid in moderate or even down to deep WI regions for nanoscale devices. A simple RF equivalent circuit is proposed, leading to first-order analytical expressions, which are able to describe the RF small-signal behavior of nanoscale MOSFET, including noise, across all inversion levels. Using these expressions it is possible to extract the values of all the RF components and noise model parameters directly from measurements. The analytical models are compared to RF measurements of a commercial state-of-the-art 40-nm CMOS process and to the advanced BSIM6 compact bulk MOSFET model, showing very good accuracy. [ABSTRACT FROM PUBLISHER]

A phase noise reduction scheme using a sensitive resonator-based low-noise phase-frequency discriminator is presented in this paper. The discriminator uses a high quality factor thin film bulk acoustic resonator in a notch filter configuration with common-mode traps to reduce the low-frequency noise up-conversion. The phase noise reduction scheme comprises of a main feedback loop to lock a voltage-controlled oscillator to the discriminator and another loop to adjust the depth of the notch. Two chips were fabricated in 0.13-\mum CMOS technology integrating the discriminator and the phase noise reduction schemes, respectively. The 1.5-GHz discriminator shows phase noise floor of -\128 dBc/Hz at 20 kHz, -\142 dBc/Hz at 100 kHz, -\162 dBc/Hz at 1 MHz, and -\166 dBc/Hz at 4 MHz, while consuming 26 mW of power. The measured phase noise of the feedback reduction circuitry reaches the phase noise floor of the discriminator within the loop bandwidth, as expected. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive theoretical study on Doherty power amplifiers (PAs) under antenna impedance mismatch. It is demonstrated for the first time that by varying the relative gain and phase of the carrier and peaking amplifiers, the PA performance degradation caused by the antenna impedance mismatch can be largely compensated. Such a compensation effect is discussed extensively for different antenna impedance conditions. Four types of Doherty PAs, i.e., three digital Doherty PAs with different degrees of flexibility and the classical analog Doherty PA, are covered in the complete theoretical analysis. To intuitively show the proposed concept, this paper presents numerical simulation results based on the theoretical analysis. In addition, measurement results on a fully integrated digital Doherty PA implemented in 65-nm bulk CMOS are demonstrated to verify our theoretical study. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed and low feed-through sampler with two-channel time-interleaved track-and-hold amplifiers (THAs). The THA is based on switched buffer with active inductors load such that wide bandwidth in track-mode and small-signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. With two-channel accurate on-chip clock and its distribution network, double sampling rate is achieved due to the two-channel time-interleaved structure used. The chip was fabricated in 65-nm RF-CMOS process with core area of 0.07 mm^2 and power consumption of 211 mW. The measurements show that the S-parameters matched input and output up to 40 GHz with 19.3-GHz bandwidth in track-mode, the spurious-free-dynamic-range above 35 dB and total harmonic distortion below -\30 dB up to 6 GHz when the sampling rate is 16.26 GS/s for one channel. [ABSTRACT FROM AUTHOR]

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low VDD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-\mu\ m silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control. [ABSTRACT FROM AUTHOR]

This paper presents low-noise amplifiers (LNA) at X- and K-band frequencies in a 0.18-\mum SiGe HBT technology. A method of noise match optimization with respect to base inductance in SiGe LNA design with large transistors is proposed. The measured X- and K-band LNAs result in 1.2- and 2.2-dB mean noise figure in their frequency bands, with an associated peak gain of 24.2 and 19 dB at 8.5 and 19.5 GHz, respectively. The measured IIP3 is -\11 and -\4 dBm at 10 and 20 GHz, for a power consumption of 32.8 mW (X-band LNA) and 22.5 mW (K-band LNA). To the authors' best knowledge, these results outperform all available CMOS designs and achieve the lowest mean noise figure at X- and K-bands in any SiGe or CMOS process. The main application areas are in low-noise receivers for terrestrial communication systems and low-cost radars. [ABSTRACT FROM AUTHOR]

With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power operation with the aid of two novel implementation methods is presented. In an FSDT system, data rate is limited by the number of Walsh spreading codes available for use in the optimal body channel band of 40–80 MHz. The first method overcomes this limitation by applying multi-level baseband coding scheme to a carrierless FSDT system to enhance the bandwidth efficiency and to support a data rate of 60 Mb/s within a 40-MHz bandwidth. The proposed multi-level coded FSDT system achieves six times higher data rate as compared to other BCC systems. The second novel implementation method lies in the use of harmonic frequencies of a Walsh encoded FSDT system that allows the BCC system to operate in the optimal channel bandwidth between 40–80 MHz with half the clock frequency. Halving the clock frequency results in a power consumption reduction of 32%. The transmitter was fabricated in a 65-nm CMOS process. It occupies a core area of 0.24\,\times\,0.3 mm^2. When operating under a 60-Mb/s data-rate mode, the transmitter consumes 1.85 mW and it consumes only 1.26 mW when operating under a 5-Mb/s data-rate mode. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-cost 45-GHz on–off keying (OOK) transceiver system in 90-nm CMOS for high-speed short-range wireless communications. The system includes a transmitter (Tx), a receiver (Rx), and two on-board substrate integrated waveguide fed Yagi–Uda antennas. The Tx provides about 7 dBm of output power and better than 50-dB on/off isolation while consuming 61.6 mW of dc power. The Rx performs noncoherent demodulation with a power consumption of 53.6 mW. The on-board antennas are integrated with the Tx and Rx using carefully designed broadband wire-bond interconnections, resulting in a low-cost system integration. The proposed transceiver achieves error-free operation (bit error rate <\10^-12) of 4-Gb/s data rate over a distance of 55 cm, which results in a bit energy efficiency per distance (BEEPD) of 0.52 pJ/bit/cm. To our best knowledge, this work shows the highest on/off isolation among the OOK Txs, the longest transmission distance, and the best BEEPD among the OOK transceivers reported to date in the millimeter-wave frequency band. [ABSTRACT FROM PUBLISHER]

This paper introduces a transformer-based, dual-coupled, triple-mode voltage-controlled oscillator (VCO) using a transformer-based fourth-order tank with tunable transconductance feedback between the primary and secondary coils. The tank impedance can be reshaped by the transconductors through the tuning of their biasing currents. By controlling the bias currents, the VCO has three different operational modes, capable of generating a single frequency in either the 3- or 5-GHz band as well as two frequencies in the 3- and 5-GHz bands simultaneously. The measured phase noise at 1-MHz offset frequency is -109.5 and -118.8 dBc/Hz when the oscillator oscillates at a single frequency of 5.24 or 3.22 GHz, respectively. The phase noise is -104.3 and -112.6 dBc/Hz, respectively, when the oscillator oscillates at 5.34 and 3.03 GHz simultaneously. The triple-mode VCO was fabricated in a 0.13-\mum CMOS process, occupies a core area of 0.16 mm^2, and dissipates 5.6 mW from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of >\0 dBm, while consuming 48 mA from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-locked quadrature voltage-controlled oscillator (QVCO) and quadrature frequency-locked loop (FLL) are presented in this paper using 90-nm CMOS process. A modified self-injection technique is employed in the QVCO to reduce quadrature error and phase noise. A transformer coupled topology is adopted to widen the locking range (LR) of the subharmonically injection-locked QVCO. With a subharmonic number of 3, the proposed subharmonically injection-locked QVCO demonstrates an overall LR of 3.5 GHz, a phase noise of −126.8 dBc/Hz at 1-MHz offset, a phase error of 0.32°, and an amplitude error of 0.26 dB. Moreover, the quadrature FLL is developed using the QVCO, and the subharmonic number can be up to 32 since the control voltage of the QVCO is adaptively aligned to overcome the LR. The operation frequency of the subharmonically injection-locked quadrature FLL is from 49 to 51.4 GHz. The measured amplitude and phase errors are 0.5 dB and 2.5°, respectively. Between 15 °C and 50 °C, the measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are lower than −106 dBc/Hz and 110 fs, respectively. Compared to the prior art, the proposed $V$ -band subharmonically injection-locked quadrature QVCO and quadrature FLL feature excellent performance and good robustness. [ABSTRACT FROM AUTHOR]