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A frequency-modulated ultrawideband (FM-UWB) hybrid transceiver, with a high system reuse ratio up to 90%, is fabricated in the 65-nm CMOS process for both short-range wireless communication and high-resolution radar ranging. The radio frequency (RF) front-ends (RFFEs) based on module stacking and current reuse achieve significant RF power savings of about 30% and 50% for the transmitter and the receiver (RX), respectively. The presented IF zero-crossing delay discrimination benefits a high radar resolution less than 1 cm. A multimode relaxation oscillator (OSC) for the reconfigured triangular subcarrier generation and a dual-path ring voltage-controlled oscillator (VCO) for the linear FM, stacked by a wideband push–pull power amplifier (PA), generate an FCC-compliant UWB signal. An active balun embedded low-noise amplifier (LNA) and two symmetric-detuning band-passed filters (BPFs) are stacked with the bandwidth extension to linearly demodulate the UWB FM signal. Experimental results show that the 3.75–4.25-GHz hybrid transceiver has an energy efficiency of 1.9 nJ/bit with an active area of 0.7 mm2 and a power dissipation of 1.9 mW and achieves the RX sensitivity of −71 dBm and the transmitted power of −14.1 dBm, with a bit error rate (BER) of 10−4 at a distance of 4 m under the data rate (DR) of 0.1–1.0 Mbps. The transceiver also achieves the noise figure (NF) of 4.8 dB and the phase noise of −78.6 dBc/Hz at 1-MHz offset frequency. [ABSTRACT FROM AUTHOR]

In this article, a Schottky diode-based microwave rectifier that employs coupled transmission lines (CTLs) is proposed. CTL is herein used to enhance the voltage amplitude across the Schottky diode with the consequent increase in the rectifier efficiency, especially for low input powers. It is also shown that multiple cascaded CTLs can further enhance the rectifier conversion efficiency, even if this benefit is partially annihilated by the increased insertion loss. Several compact prototypes with single and dual CTLs for 2.45 GHz have been fabricated and measured for different input power levels. Particularly, a single CTL rectifier exhibits RF-to-dc conversion efficiency of 67.7% for an input power of 0 dBm, leading to an improvement of about 3% with respect to other referred rectifiers (with a dc load of 4.47 k $\Omega $), while dual CTL rectifier has an outstanding efficiency of 75.3% for an input power of only 5.5 dBm (with a dc load of 1.76 k $\Omega $). Passive voltage boost by means of CTLs can be applied to other rectifier circuits as also demonstrated. [ABSTRACT FROM AUTHOR]

This article proposes a harmonic-extraction technique to enhance the amplitude and the phase noise of LC oscillators at the third-harmonic frequency. By leveraging this technique, a cascaded subterahertz (sub-THz) injection-locked local oscillator (LO) generator is proposed, which consists of a fundamental voltage-controlled oscillator (VCO) and a millimeter-wave (mm-wave) injection-locked frequency multiplier (ILFM). Fabricated in a 65-nm CMOS process, the VCO prototype concurrently generates two output signals: the first output at the fundamental frequency from 17.1 to 21.7 GHz with a 10-MHz-offset phase noise from −120.6 to −126 dBc/Hz, the second output at the third-harmonic frequency from 51.3 to 65.1 GHz with a 10-MHz-offset phase noise of −116.3 dBc/Hz, and the third-harmonic output power of −19.1 dBm. The VCO prototype consumes 1.4 mW from a 0.3-V supply, resulting in an FoM from −186 to −189.6 dBc/Hz at the fundamental frequency. The sub-THz injection-locked LO generator achieves a frequency tuning range of 23.7% from 153.9 to 195.3 GHz with a 10-MHz-offset phase noise of −106.8 dBc/Hz and the output power of −14.6 dBm, and consumes 8.4 mW, which corresponds to an FoM of −181.2 dBc/Hz and an ${\mathrm {FoM}}_{T}$ of −188.7 dBc/Hz at 153.9 GHz. [ABSTRACT FROM AUTHOR]

An injection-current-boosting (ICB) locking-range enhancement technique is presented to increase the locking range (LR) of the millimeter-wave (mm-wave) injection-locked frequency triplers (ILFTs). With a transformer-based fourth-order injection-coupling network, the parallel capacitance from the injection devices is resonated out over a wide frequency range and the injection current is boosted greatly. Analytical models of the ICB–ILFT are introduced, based on which the current-boosting phenomenon is analyzed. Meanwhile, the design concepts of the ultra-wideband mm-wave ILFT are presented. With the proposed ICB technique, an ICB-ILFT is designed and fabricated in 65-nm CMOS process. With a 0-dBm RF injection source, the ICB-ILFT can be locked from 22.8 to 43.2 GHz without calibration, achieving a 61.8% LR. The power consumption is only 5.0 mW and a 9.5-dB phase noise difference is observed, which is close to the theoretical value. [ABSTRACT FROM AUTHOR]

Terahertz (THz) sources with stabilized output frequencies are desired in many systems, however, the design of conventional THz phase-locked loops encounters many challenges. In this paper, a fully on-chip frequency-stabilization feedback mechanism is proposed, which avoids the use of both frequency dividers and the off-chip reference, achieving much lower power consumption and system integration cost. Using this scheme, two circuit prototypes are designed in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. The first one is a 302–332-GHz frequency-stabilized source with ultralow power consumption. It achieves a −13.9-dBm probed output power with a dc power consumption of only 51.7 mW. The second design is a 308–317-GHz frequency-stabilized high-output-power radiating array, which achieves a peak-radiated power and EIRP of 4.6 mW and 24.7 dBm, respectively, with a total dc power consumption of 1.18 W. With significantly lower system integration cost and power consumption, the proposed scheme is attractive for many applications that require short coherence time, such as THz active imaging systems and short-range millimeter-wave (mm-wave)/THz FMCW radars. With further calibration and enhancement in long-term stability, this scheme will also be useful in systems like communication transceivers. [ABSTRACT FROM AUTHOR]

This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm2. The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between −93 and −96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of −245 dB. The lock time in low-noise mode is up to $12~\mu \text{s}$ , which is improved to $3~\mu \text{s}$ by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between −235 and −240 dB. [ABSTRACT FROM AUTHOR]

This paper presents a 1.7-mW low-intermediate-frequency receiver design for Bluetooth low-energy (BLE) applications. The design exploits particular aspects of BLE, such as the relaxed in-band interference characteristics, more precisely the $C/I_{1~\textrm {MHz}}$ , and the relatively high-frequency-shift keying modulation index, to deliver a high level of energy efficiency and simplicity to the receiver baseband architecture. Reliable quadrature signals are generated in the RF signal path without consuming energy, which is supported by an inverter-based low-noise amplifier (LNA) that achieves high gain and low noise figure under low-power budgets. A small-signal analysis of low-power inverter-based LNAs is presented offering simple design equations. Seeking an affordable solution, the fabricated prototype is fully integrated into an earlier generation CMOS technology node ($0.13~\mu \text{m}$), occupying a silicon area smaller than 0.7 mm2. The receiver achieves a sensitivity level of −92 dBm while consuming 1.41 mA from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1–10.6-GHz band efficiently for high data-rate short-range wireless connectivity even in overcrowdedness of the frequency spectrum. Frequency synthesizers tailored to the UWB-based CR should provide wide lock range, multiple frequency bands, and low in-band spurs while consuming low power. This paper investigates a low power, wide lock range, integer-N frequency synthesizer approach with 132-MHz frequency step and 57 subbands in the UWB band. Two-stage supply regulated differential ring oscillator provides linear and wide tuning range with voltage controlled oscillator gain of 22.5 GHz/V and low supply-noise sensitivity. A modular true-single-phase-clock programmable divider achieves wide operating frequency range of 0.1–6.5 GHz and power efficiency of 6.25 GHz/mW by compensating leakage current at the dynamic nodes with conditional latches. Replica-based digital calibration reduces the current mismatch of the charge pump to <1% for low in-band reference spurs of <−60 dBc. A frequency synthesizer test chip was fabricated in 65-nm complementary metal–oxide–semiconductor technology. The active area of the frequency synthesizer is 0.12 mm2. It achieves <−30-dBc integrated phase noise and enables the UWB-based CR to get bit error rate of <10−3 while consuming <−10.1 mW. [ABSTRACT FROM AUTHOR]

A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push-pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)-RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW. [ABSTRACT FROM AUTHOR]

A low-power 28-GHz phased-array receiver (RX) front end is presented that incorporates a low-power low-noise amplifier (LNA) and a passive reflection-type phase shifter (RTPS) capable of 360° phase shift with 5-b phase resolution and low gain variation. Passive phase shifters are limited by tradeoffs between phase resolution, insertion loss, and phase shift range. The proposed RTPS load design and optimization approach leads to a 28-GHz RTPS achieving the state-of-the-art insertion loss with 360° phase shift range and low loss variation across the phase shift. The LNA adopts a transformer-coupled neutralization architecture that increases available gain, enabling lower power consumption. The phased-array front end is designed for Ka-band applications and has been implemented in 65-nm CMOS. The measured RTPS achieves 360° phase shift with 7.75 ± 0.3 dB insertion loss and an rms phase error of 0.3° at 28 GHz. The low-power phased-array RX front end has an overall gain of 9.5 ± 0.4 dB and noise figure <;5.5 dB at 28 GHz. The RX front end consumes 10 mW from a 0.9-V supply with phase shifter and an LNA active area of 0.16 and 0.32 mm2, respectively, in 65-nm CMOS, demonstrating its suitability for low-power phased-array RX for emerging wireless links. [ABSTRACT FROM AUTHOR]

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18- \mu \textm SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of −97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz–10 MHz is 2.05° rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm $\times$ 1.86 mm. [ABSTRACT FROM PUBLISHER]

This paper presents a wideband fractional- N frequency synthesizer design with a low-effort adaptive calibration technique for \Sigma \Delta quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital–analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications. [ABSTRACT FROM PUBLISHER]

A low-power low-noise 0.7-V mixer-first RF frontend for an IEEE 802.15.6 narrowband receiver is presented, which uses frequency translated mutual noise cancellation based on passive coupling. Unlike traditional noise-cancelling techniques, we perform symmetrical noise cancellation of a fully differential structure where each path cancels the noise of the other at IF. This prototype design realized in TSMC’s 65-nm CMOS tackles the noise figure and power consumption problems of sub-1-V mixers. The figure of merit is 10 dB higher and the power consumption is 194 \mu\W, which is 0.5\times lower than the state-of-the-art. The local oscillator power used is -\14 dBm. [ABSTRACT FROM PUBLISHER]

Low-power cryogenic low-noise amplifiers (LNAs) are desired to ease the cooling requirements of ultra-sensitive cryogenically cooled instrumentation. In this paper, the tradeoff between power and noise performance in silicon–germanium LNAs is explored to study the possibility of operating these devices from low supply voltages. A new small-signal heterojunction bipolar transistor noise model applicable to both the forward-active and saturation regimes is developed from first principles. Experimental measurements of a device across a wide range of temperatures are then presented and the dependence of the noise parameters on collector–emitter voltage is described. This paper concludes with the demonstration of a high-gain 1.8–3.6-GHz cryogenic LNA achieving a noise temperature of 3.4–5 K while consuming just \290~\mu\W when operating at 15-K physical temperature. [ABSTRACT FROM AUTHOR]

In this paper, two proposed bandwidth (BW) extension techniques are discussed and analytically analyzed. The capabilities of the proposed feedback techniques are demonstrated with two design examples of different circuitry, supported by simulation and measurement results. The first design example is a broadband low-power active balun, employing one of the presented feedback techniques. It is capable of operating with a gain of 2.2 dB and BW of more than 70 GHz. The amplitude imbalance is less than 2.4 dB, while the phase imbalance is below 7^\circ up to 60 GHz and 14^\circ up to 70 GHz, consuming a low-power of 29.7 mW. The second design example is a differential three-stage amplifier, incorporating the two techniques, where their combined performance achieves a gain of 54 dB and a 3-dB BW of 25 GHz, resulting in a gain-BW product (GBP) of 12.5 THz, with a power consumption of 180 mW from a 3.3-V supply. The chips are fabricated in a 0.35-\mum SiGe:C bipolar technology with a f_t/ f\max of 200/250 GHz. [ABSTRACT FROM PUBLISHER]

A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5°. The EIRP can be further raised to 9.5 dBm as the supply V DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm2. All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far. [ABSTRACT FROM AUTHOR]

This paper presents a high-efficiency 60-GHz on–off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on–off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of \ 0.077 mm^2. A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-cost 45-GHz on–off keying (OOK) transceiver system in 90-nm CMOS for high-speed short-range wireless communications. The system includes a transmitter (Tx), a receiver (Rx), and two on-board substrate integrated waveguide fed Yagi–Uda antennas. The Tx provides about 7 dBm of output power and better than 50-dB on/off isolation while consuming 61.6 mW of dc power. The Rx performs noncoherent demodulation with a power consumption of 53.6 mW. The on-board antennas are integrated with the Tx and Rx using carefully designed broadband wire-bond interconnections, resulting in a low-cost system integration. The proposed transceiver achieves error-free operation (bit error rate <\10^-12) of 4-Gb/s data rate over a distance of 55 cm, which results in a bit energy efficiency per distance (BEEPD) of 0.52 pJ/bit/cm. To our best knowledge, this work shows the highest on/off isolation among the OOK Txs, the longest transmission distance, and the best BEEPD among the OOK transceivers reported to date in the millimeter-wave frequency band. [ABSTRACT FROM PUBLISHER]

In this paper, the MOS transistor (MOST) moderate-inversion (MI)–weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)–power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI–WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation—showing the MI–WI region as the optimum design zone—is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 \mu\W, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -\4 dBm with load and source resistances of 50 \Omega. [ABSTRACT FROM AUTHOR]

A low-power and high data-rate fully integrated 60-GHz on–off keying (OOK) transceiver for short-range wireless communication is demonstrated. The transceiver consists of a switch, transmitter, and receiver and uses OOK modulation for a compact and low-power design. With a highly efficient Tx, high-speed modulator/demodulator, and wideband characteristic, the transceiver has low-power and high data-rate capability. Implemented in 90-nm CMOS technology, the transmitter and the receiver consume 31 and 36 mW at 10.7 Gb/s and occupy an active footprint of 0.15 and \ 0.29 mm^2, respectively. The transceiver with an on-board Yagi–Uda antenna achieves 10.7-Gb/s wireless OOK data transmission over 10 cm at a bit-error rate of less than \10^-12 for \2^7 -\1 pseudorandom binary sequence. As a result, the proposed transceiver achieves energy efficiency of 6.26 pJ/bit. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a low-voltage current-reused single-sideband mixer (SSBM) and quadrature voltage-controlled oscillator (QVCO) for Mode-1 multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer application. The proposed architecture is a low-voltage and low-power solution by stacking the SSBM on top of a pMOS parallel QVCO. For low-voltage operation, two symmetric transformers are used to perform quadrature oscillation and signal coupling. In addition, source degeneration capacitors are introduced to eliminate bimodal oscillation in QVCO and fix the phase sequence of the quadrature signal. For experimental demonstration, the proposed circuit was fabricated in a 0.18-\mu\ m CMOS technology. The prototype occupies a core area of 0.8 \ \ mm^2 and consumes about 11 mA from a 1.6-V power supply. Measurement results show that the image spurious rejection is over 43 dBc and the output phase noise of the SSBM is better than -\111.4 dBc/Hz at 1-MHz offset from carrier (3.432 GHz). [ABSTRACT FROM PUBLISHER]

An ultra-low-power consumption and ultra-low local oscillator (LO) power double-balanced down-conversion mixer using standard 90-nm CMOS technology is presented in this paper. By employing a weak inversion biasing technique in a source-driven topology, the proposed V-band mixer can operate at microwatt power consumption of 453 \mu\W and has an ultra low LO power of -\6 dBm. In addition, under 1.2-V standard supply voltage, the down-conversion mixer exhibits excellent conversion-gain flatness of \ 5.9\pm\ 1.5~\ dB and the measured LO-to-RF isolation is more than 37 dB from 53 to 70 GHz, and OP1 dB of -\9.2 dBm at RF frequency of 60 GHz. Based on aforementioned results, the presented monolithic microwave integrated circuit can mitigate power-hungry issues while providing reasonable RF performance, which is important for a low-power communication system. [ABSTRACT FROM AUTHOR]

A surface-acoustic-wave-less first folded-conversion and second down-conversion receiver for the AM/FM/digital radio mondiale (DRM)/digital audio broadcasting (DAB) radio standards is presented. This architecture is more suitable for broadcasting radio with ultra-narrow signal bandwidth since it relaxes the requirement on the local area (LO) generator by decreasing its tuning range. To reduce the blockers and out-of-band (OB) interferers, current amplifying and polyphase filters are introduced simultaneously. An inverter-based switched capacitor array technique is proposed in voltage-controlled oscillator (VCO) design to isolate the noise from the substrate. With a single VCO, the receiver can cover the frequency range from 100 kHz to 1.5 GHz. Without the RF pre-filters, the in-band IIP3 is 1.5 dBm, and the OB IIP3 is up to 17.4 dBm. The LO phase noise in the worst case is -119 dBc/Hz@1 MHz. The chip is fabricated in a 0.18-\mu\m CMOS technology, and mounted on a QFN package. It consumes only 86.4 mW under 1.8-V supply. To our best knowledge, this is first receiver reported thus far that supports all four AM/FM/DRM/DAB standards. [ABSTRACT FROM AUTHOR]

This paper proposes progressive mixing as a technique to widen the locking range of injection locked frequency dividers (ILFDs) with higher division ratios. The ILFD locking range for a certain division ratio depends on the harmonics that are used to generate the injection signal. Compared to the conventional ILFD, the proposed technique uses much stronger harmonics in the mixing process to generate the injection signal more efficiently for higher division ratios. This is achieved through the reuse of higher harmonics of the ILFD fundamental oscillation frequency to perform progressive or multisteps divide-by-2 mixing of the injection signal. This results in that the injection signal is mixed with much stronger harmonics compared to the conventional single-step mixing and a stronger injection is produced. Since each divide-by-2 step uses higher harmonics of the fundamental, there is no increase in power consumption while the locking range is significantly enhanced. Two progressive mixing ILFDs are designed using a 65-nm CMOS to divide-by-4 and divide-by-8. The former has an operation range from 7.3 to 21.3 GHz while maintaining a locking range greater than 31% and consuming 3.9 mW from a 1.2-V supply. The latter has an operation range from 12.6 to 24.7 GHz while maintaining a locking range greater than 15% and consuming 7.1 mW from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

The factors that impact the intermodulation distortion performance of an active downconverting mixer are investigated. Through a Volterra-series analysis of the RF transconductor stage of the mixer, design principles are formulated to maximize the mixer's IIP3. To verify the theoretical analysis, a 0.3–1.2-GHz low-voltage mixer operating from a 0.9-V supply was designed, fabricated, and tested. The mixer employs a common-gate common-source RF transconductor stage with simultaneous distortion and noise cancellation. Experimental results reveal that the mixer can yield an IIP3 of -0.8 dBm, a double-sideband noise figure below 4.8 dB, and a maximum conversion gain of 8.8 dB. [ABSTRACT FROM AUTHOR]

This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-\mu\ m CMOS technology. The experimental result shows that the - \ 3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -\7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 \ mm^2. [ABSTRACT FROM PUBLISHER]

This paper discusses an 866-MHz UHF quadrature voltage-controlled oscillator (QVCO) for RFID front-end. The VCO achieved an improved phase noise performance of -130 dBc/Hz at a carrier-offset of 1 MHz using an improved architecture employing pulsed self-biasing. It was fabricated using the IBM 130-nm CMOS process with the core VCO occupying around 0.36 mm2 die area. The loading effect of finite gds for nanometric CMOS design was also considered. The VCO achieved 8% tuning range with very low quadrature error. It was tested using a power supply in the range of 0.6-1 V, drawing a maximum of 2.5 mW. In addition, it achieved a figure of merit of -185 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper reports the design and analysis of 21–29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-\mum CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21–29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21–29-GHz band, the receiver front-end exhibits excellent noise figure of \4.6 \pm \0.5\ dB, conversion gain of \23.7 \pm \1.4 dB, RF port reflection coefficient lower than -\8.8 dB, LO-IF isolation lower than -\47 dB, LO-RF isolation lower than -\55 dB, and RF-IF isolation lower than -\35.5 dB. The circuit occupies a chip area of 1.25\,\times\,1.06 mm^2, including the test pads. The dc power dissipation is only 39.2 mW. [ABSTRACT FROM AUTHOR]

A 50-Mb/s quadrature phase-shift keying (QPSK)/offset quadrature phase-shift keying (O-QPSK) transmitter suitable for biomedical high-quality imaging application is presented. Centered at 915 MHz, the phase modulation is achieved by directly modifying the self-resonant frequency of an LC voltage-controlled oscillator through capacitor bank switching. By eliminating many unnecessary building blocks in the conventional QPSK/O-QPSK transmitter, significant power and area savings are achieved. Implemented in 0.18-\mu\ m CMOS technology, it occupies an active core area of \ 0.28 mm^2. With 305-MHz injection frequency and consuming 5.6 mW under 1.4-V supply, the transmitter achieves error vector magnitude (EVM) of 11.4%/5.97% for O-QPSK/QPSK modulation while delivering output power of -\3 dBm at 50 Mb/s. By lowering the injection frequency to 101.67 MHz, it consumes 5.88 mW under the same supply voltages while delivering an output power of -\3.3 dBm. The transmitter achieves measured EVM of 6.4% at 50 Mb/s under QPSK modulation. [ABSTRACT FROM PUBLISHER]

A wideband low-noise amplifier (LNA), which is a key block in the design of broadband receivers for multiband wireless communication standards, is presented in this paper. The LNA is a fully differential common-gate structure. It uses multiple feedback paths, which add degrees of freedom in the choice of the LNA transconductance to reduce the noise figure (NF) and increase the amplification. The proposed LNA avoids the use of bulky inductors that leads to area and cost saving. A prototype is implemented in IBM 90-nm CMOS technology. It covers the frequency range of 100 MHz to 1.77 GHz. The core consumes 2.8 mW from a 2-V supply occupying an area of 0.03 \ mm^2. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB, while the average NF is 2 dB across the whole band. The LNA achieves a return loss greater than 10 dB across the entire band and a third-order input intercept point IIP3 of -2.85 dBm at the maximum gain frequency. [ABSTRACT FROM PUBLISHER]

A low-power, high-gain (HG), and low-noise (LN) CMOS distributed amplifier (DA) using cascaded gain cell, formed by an inductively parallel-peaking cascode-stage with a low-Q RLC load and an inductively series-peaking common-source stage, is proposed. Flat and high S21 and flat and low noise figure (NF) are achieved simultaneously by adopting a slightly under-damped Q factor for the second-order transconductance frequency response. A single-stage and a two-stage DA for ultra-wideband (UWB) systems are demonstrated. In the LN mode, the two-stage DA consumes 22 mW and achieves flat and high S21 of 14.07 \pm 1.69 dB with an average NF of only 2.8 dB over the 3–10-GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or LN amplifier in the literature. In addition, in the low-gain mode, the two-stage DA consumes 6.86 mW and achieves S21 of 11.03 \pm 0.98 dB and an average NF of 4.25 dB. In the HG mode, the two-stage DA consumes 37.8 mW and achieves S21 of 20.47 \pm 0.72 dB and an average NF of 3.3 dB. The analytical, simulated, and measured results are mutually consistent. [ABSTRACT FROM AUTHOR]

In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the g_m/I_D technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. [ABSTRACT FROM PUBLISHER]

In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18-\mu\ m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermodulation intercept point of the entire circuit are 16 dB, 17.4 dB, and -1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only -9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique. [ABSTRACT FROM AUTHOR]

A low-power transceiver for medical implant communication service is presented. The device consists of three subsystems, which perform wake-up signal reception, data-link binary frequency-shift keying (BFSK) reception, and transmission, respectively. A common antenna interface is reused in the three subsystems, reducing circuit complexity and number of external components. Super-regenerative architecture is used for wake-up reception, and gm-boosted common-gate stages are used to optimize receiver (RX) performance with low power consumption. The transmitter employs an all-digital frequency-locked loop to directly drive a class AB power amplifier. The transmitter can alternatively use an injection-locked power oscillator for lower bit rates and power consumption. The integrated circuit is designed and fabricated on a 0.18-\mu\m CMOS process. The wake-up RX achieves a -80-dBm sensitivity for a 50-kb/s signal and a 280-\mu\W dissipation. The BFSK RX achieves a -97-dBm sensitivity for a 75-kb/s signal and a 2-mW power consumption. Finally, the transmitter achieves an output power of -5 dBm for a power consumption of 2.9 mW. [ABSTRACT FROM AUTHOR]

This paper at first illustrates implementation aspects and measurement results of a subcomponent for a multistandard RF identification (RFID) transponder. It is intended to be a common reference cell, both for basic UHF requirements and advanced application fields like local positioning and wireless sensing. Different single circuit topologies shown in previous studies or literature and their applicability for that RFID system are evaluated. After that, measurement results of two final circuit configurations, including a newly designed RC oscillator with metal–metal capacitors, are discussed and compared. Layout aspects for reducing the process variations and low power consumption are demonstrated. Simulation results show border conditions for the power supply of the transponder on chip level. [ABSTRACT FROM AUTHOR]

A wireless biotelemetry system operates in vivo, which requires low power consumption for long-lasting operation, high output power for long transferable distance, and high throughput for incorporating many recording electrodes and transmitting raw brain signals. An implantable 2.4-GHz on–off keying (OOK) transmitter with high throughput and high energy efficiency for wireless biotelemetry systems has been designed in a 0.18-\mum CMOS process. To balance power consumption and output power, a complementary voltage-controlled oscillator for the proposed transmitter is employed. Power consumption of the transmitter is reduced by switching the oscillator on and off to generate an OOK modulated signal. The transient delay for the transmitter is derived and applied to implement a high throughput transmitter. Rat skin-mimic emulating the implant environment such as electrical properties of the skin is used to measure the proposed transmitter in vitro. To transmit 136 Mb/s of OOK data, the transmitter consumes 3 mW of dc power and generates an output power of -14 dBm. The transmitter achieves energy efficiency of 22 pJ/bit with an associated bit error rate of \1.7 \times \10^- 3 without using an error correction scheme. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a low power wideband mixer for multistandard receivers, covering global system for mobile communications, universal mobile telecommunications system, wireless local area network, Bluetooth, and ultra-wideband. The circuit topology is based on the folded technique with a current reuse shunt feedback RF input stage operating at a low supply voltage of 1 V. The mixer offers a peak gain of 12.8 dB, a 3-dB bandwidth from 1 to 10.5 GHz, and a minimum double-sideband noise figure of 7.6 dB. The input referred compression point is better than -15 dBm with an output referred intercept point of better than 5.75 dBm over the entire bandwidth. The mixer circuit was fabricated in a 65-nm standard CMOS process and draws 5 mA of dc current, leading to a power dissipation of only 5 mW. Gain and noise performance can be further increased when operating at nominal supply voltage of 1.2 V at the expense of an increasing power dissipation. [ABSTRACT FROM AUTHOR]

The simultaneous noise and impedance matching (SNIM) condition for a common-source amplifier is analyzed. Transistor noise parameters are derived based on the more complete hybrid-π model, and the dominant factors jeopardizing SNIM are identified. Strategies for narrowband and broadband SNIM (BSNIM) are derived accordingly. A dual reactive feedback circuit along with an LC-ladder matching network is proposed to achieve the BSNIM. It includes a capacitive and an inductive feedback, where the former utilizes the transistor parasitic gate-to-drain capacitance and the latter is formed by transformer coupling. This circuit topology has been validated in 0.18- and 0.13-μ m CMOS technologies for a 3-11-GHz ultra-wideband (UWB) and a 2.4-5.4-GHz multistandard application, respectively. The 3-11-GHz UWB low-noise amplifier is detailed as a design example. [ABSTRACT FROM AUTHOR]

An experimental demodulator suitable for ultra-low-voltage and low-power wireless applications is presented in this paper. To alleviate the stringent design constraints, discrete-time frequency-shift keying (FSK) is employed in this design. The proposed demodulator is composed of limiting amplifiers (LAs), lowpass filters (LPFs), and discrete-time quadricorrelators. For circuit implementations, negative-feedback source-degeneration gain cells are adopted in the LAs for low-voltage operations, while the LPFs are realized by a Sallen-Key structure with differential difference amplifiers for reduced power consumption and chip area. As for the quadricorrelators, delay cells are utilized in the discretetime differentiator and the base-band signals are finally detected for logic recognition. Using a standard 0.18-μm CMOS process, the proposed demodulator is implemented for demonstration. Operated at a 0.6-V supply voltage, the fabricated circuit consumes a dc power of 2.4 mW. With a data rate of! Mb/s and a modulation index of 0.32, the measured bit error rates for FSK and Gaussian FSK schemes are 0.333% and 1.036%, respectively, at an IF frequency of 2 MHz. [ABSTRACT FROM AUTHOR]

Abstract-We present a two-stage digitally controlled ring oscillator designed mainly for impulse-radio ultra-wideband (UWB) applications. Each basic stage utilizes a local positive feedback, allowing to achieve steady oscillation at low current consumption levels, and to extend the frequency tuning over an ultra-wide range. The frequency tuning is achieved via the control of the tail resistor in each stage. The circuit is fabricated in a 0.13-μm CMOS technology. It features full UWB coverage at slightly higher than 1.3-V supply voltage, -121.7-dBc/Hz phase noise at a 5.6-GHz carrier, and 10-MHz offset, and less than 5-mW power consumption for the digitally controlled oscillator core alone at 10.18-GHz maximum frequency under 1.3-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents design techniques for a low-voltage voltage-controlled oscillator (VCO) with a wide tuning range and low sensitivity to process, voltage, and temperature (PVT) variations. For wide tuning range, a switched tuning scheme is employed coupled with voltage-boosting techniques in a manner that improves the quality factor and tuning range of a switched capacitor array. To minimize the design overhead required for a robust VCO, an adaptive body-biasing technique is proposed, which relaxes the startup constraint and increases the VCO's immunity to PVT variations. The proposed VCO is implemented in 0.18-μm CMOS technology and operates at 2.4 GHz. It achieves phase noise of -117 dBc/Hz at 1-MHz offset and a tuning range 20% while consuming 365 μW of power. The figure-of-merit with the tuning range is -197 dBc/Hz, which is the lowest among recent state-of-the-art low-voltage VCOs. [ABSTRACT FROM AUTHOR]

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a Gm-boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-μm CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured Pin-1 dB and IIP.3 are -18 and -8.6 dBm, respectively. For the LNA with a Gm-boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW. [ABSTRACT FROM AUTHOR]

This paper introduces a low-power ultra-wideband true root-mean-square power detector with a 0.13-μm CMOS process operating from 125 MHz to 8.5 GHz. The detector utilizes the MOS transistor's square-law characteristic in the strong inversion region to obtain the power information of the input RF signal, and its exponential characteristic in the weak inversion region to realize the linear-in-decibel output. Measured dynamic ranges are 20 dB at 125 MHz and 18 dB at 8.5 GHz, respectively, with tolerances of ±0.5-dB error. WiMedia-Ultrawideband and wireless local area network 802.11a signals with different modulation techniques and data rates are measured. The integrated detector operates at 1.2-V supply voltage, and its static power consumption is 0.18 mW. [ABSTRACT FROM AUTHOR]

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-μm RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S11 of -19 dB while using 630 μA of dc current. The measured noise figure is 5.2 dB. [ABSTRACT FROM AUTHOR]

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-μm CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm2. [ABSTRACT FROM AUTHOR]

A 1-V wideband CMOS phase and power splitter (PPS) with an RLC network load and frequency compensation capacitor is proposed. Adopting the RLC network load and the frequency compensation capacitor, the gain and phase imbalances of the output can be improved and the wideband response can be achieved, respectively. Moreover, this architecture can not only offer high transfer power gain, but also adopts the tuning current source to overcome the power imbalance caused by process variation. An example with a differential phase condition (180°) has been designed and fabricated. Based on our measured results, in the frequency range from 3.5 to 6 GHz, the phase error is less than 7° and the power imbalance is less than 1.4 dB. For wireless local area network 802.lla applications in the frequency range from 5.15 to 5.35 GHz, the phase error is less than 0.6°, and the power imbalances are less than 0.27 dB, respectively. In addition, the transfer power gain is 9.66 dB under the power consumption of 15 mW and 1-V supply voltage. This architecture is different from the passive PPS circuit, and it has the advantages of no conversion loss and a small chip area with 0.8 mm × 0.7 mm. Compared with the conventional active PPSs, such as using the GaAs and BiCMOS process, this architecture implemented by the TSMC 0.18-μm CMOS process is competitive in cost and possesses the characteristics of low voltage and low power, and it is more easily integrated and suitable for system-on-a-chip applications. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage low-power high-speed superregenerative receiver operating in the 2.4-GHz industrial—scientific—medical band. The receiver uses an architecture in which, thanks to the presence of a phase-locked loop, the quench oscillator is operated synchronously with the received data at a quench frequency equal to the data rate. This mode of operation has several benefits. Firstly, the traditional problem of poor selectivity in this type of receiver is to a large extent overcome. Secondly, considerably higher data rates can be achieved than with classical receivers. Thirdly, the bit envelope can be matched to the superregenerative oscillator, which improves sensitivity. The receiver includes an RF front end optimized to support high quench frequencies at low supply voltages, responding to today's increasing demand for high speed and low power consumption. The prototype implemented is very simple and achieves a data rate of 11 Mb/s with a current consumption of 1.75 mA at a supply voltage of 1.2 V—an excellent tradeoff between cost, performance, and power consumption. [ABSTRACT FROM AUTHOR]

In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-μm deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the baseband analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low-power RF receiver/transmitter front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology. An RF receiver comprises a single-ended low-noise amplifier, a quadrature passive mixer, and a transimpedance amplifier. A current-mode passive mixer showing a very good 1/f noise performance is adopted to convert an RF signal directly to a baseband signal. Moreover, this type of passive mixer shows high-linearity performance, leading to overall RF receiver linearity improvement. A low-power, high-linearity transmitter front-end is implemented by using a passive mixer and two-stage driver amplifier in which the first stage is a conventional cascode amplifier and the second stage uses a folded cascode one. The receiver front-end achieves 30-dB voltage conversion gain, 7.3-dB noise figure with 1/f noise corner frequency of 70 kHz, -8-dBm input third-order intercept point, and +40-dBm input second-order intercept point. The transmitter front-end shows 12-dB power conversion gain, 0-dBm output power with 10-dBm output third-order intercept point, and -30-dB local-oscilator suppression. The receiver and transmitter front-end dissipate 3.5 and 3 mA from a 1.8-V supply, respectively. [ABSTRACT FROM AUTHOR]