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This paper presents a type of bandpass filter (BPF)-integrated single-pole double-throw (SPDT) switch using common shorted stepped-impedance resonator technique. The BPF-integrated ON-state with reverse-biased p-i-n diodes can be synthesized by classical coupled-resonator filter design theory, and the OFF-state with forward-biased p-i-n diodes is detuned which exhibits high OFF-state suppression (OSS). The transmission zeros due to the direct coupled feed, the cross-couplings and the cancelling effect of mixed electric and magnetic coupling are produced to improve the ON-state passband selectivity significantly. As examples, the third-order/fourth-order BPF-integrated SPDT switches at center frequency $f_{0} = 1$ GHz with ripple bandwidth of 110/100 MHz are designed, which show low insertion losses of 1.08/1.58 dB, sharp skirts, high roll-off rate of sidebands, high OSSs of 40.9/40.1 dB as well as high port-to-port isolation of 57.4/47.8 dB. Then, the switched 50- $\Omega $ matching circuits are in series with two output ports of above BPF-integrated SPDT switches, resulting in the absorptive OFF-state. The fabricated third-order/fourth-order BPF-integrated SPDT switches with absorptive OFF-state have the matched return losses of 30/28.2 dB, and their OSSs and port-to-port isolations are also improved.

This paper presents a design strategy to enhance the bandwidth of three-stage Doherty power amplifier (DPA) with operation upto 12-dB back-off. Based on the proposed strategy, a broadband 48-W DPA is designed and implemented using packaged CREE GaN transistors. The measured drain efficiency of 50%–61.8% at 12-dB back-off and 51.9%–66.2% at 6-dB back-off is obtained over the frequency range of 600–900 MHz. Over this 300-MHz band, the drain efficiency is between 51.1% and 78% at saturation. This corresponds to 40% fractional bandwidth. The three-stage DPA is also linearized with a three carrier 15-MHz WCDMA signal with a PAPR of 10.6 dB at various frequencies within operating band and shows the output signal qualifies spectral mask specifications.

Quasi-optical (QO) filter design is commonly based on the direct coupled bandpass filter topology with distributed resonator elements. Conventionally, prototypes with symmetrical impedance inverters are employed during synthesis, and as a result, this leads to resonators with custom lengths across the filter. This can be impractical from a QO filter implementation perspective, since spacers of arbitrary thickness may not be readily available. In this paper, we propose a novel impedance inverter equivalent network, which allows the development of prototypes where transmission lines across the filter structure to have predefined fixed lengths. Based on this technique, we developed a fourth-order QO filter prototype that composed of 2-D periodic arrays with subwavelength features. Its performance is verified with free-space measurement, and the measured results show good agreement with both full-wave and circuit simulation. Thus, it is shown that the proposed impedance inverter circuit can simplify the implementation of QO filters of higher order.

This paper presents an octave-bandwidth load modulated balanced amplifier (LMBA) that operates directly on a single modulated RF input. The architecture is based on the recently proposed LMBA technique, in which a control signal applied at the output isolation port of a balanced amplifier is used to modulate the apparent load impedance of the two devices comprising the balanced amplifier. In our approach, the injected control signal is used both as an active match and to dynamically load modulate the main devices to provide efficiency enhancement at back-off, thus extending the dynamic range compared to the original LMBA formulation. In this paper, we introduce a phase-compensation technique through which the active matching and load modulation tracks the frequency-dependent optimal loading trajectory of a packaged device. The result is a load-modulation power amplifier architecture able to perform an active, modulated match over an octave bandwidth. The technique is demonstrated over 1.8–3.8 GHz using packaged devices and an off-the-shelf hybrid coupler. The proof-of-concept octave RF-input LMBA has a peak CW output power of 44 dBm, with power added efficiency (PAE) over the 1.8–3.8 GHz operating frequency range of 37%–59% at peak power and 29%–45% at 6-dB output backoff. The RF-input nature of this architecture enables straightforward measurement with modulated signals; a W-CDMA signal at 3.8 GHz with 9-dB (measured) peak to average power ratio is demonstrated with adjacent channel leakage ratio of −30 dBc and average PAE of 18% for a 31-dBm average output power (2-dB backoff).

A broadband and highly efficient class-G supply modulated power amplifier (PA) system with 120-MHz instantaneous modulation bandwidth operating in the 1.8-GHz band is presented in this paper. The core element is the fast class-G supply modulator which switches the supply voltage of the RF PA between three discrete levels with a minimum pulse duration of 2.5 ns. Two designs for the drain bias interface between PA and modulator are evaluated where the best results are achieved for an implementation based on a $\lambda $ /4-wavelength RF-choke. Measurement results are presented for a 120-MHz contiguous carrier aggregated signal using eleven subcarriers with modulation bandwidths ranging from 5 to 20 MHz for each subcarrier. In combination with digital predistortion, the system achieves 38.5% PAE with −40-dB EVM and −46-dB ACLR for the 120-MHz multicarrier signal with a peak-to-average power ratio of 10 dB at the PA output and 39-dBm average output power. The total efficiency enhancement achieved by the class-G modulation is 13% points.

We designed a reconfigurable dual-band reflection amplifier with operation frequency bands over 1.8 GHz and/or 2.4 GHz. This one-port amplifier boosts the reflected signal over either of these two frequency bands or both as a dual-band reflection amplifier. The amplifier circuit consists of an FET transistor and two p-i-n diodes, which act as switches to form a reconfigurable system. The measured reflection gains at single 1.8 GHz and 2.4 GHz frequency bands are 17.6 dB and 16.75 dB, respectively. The dual-band operation frequency shows 11.2 dB and 15 dB gain at 1.8 GHz and 2.4 GHz, respectively. Then, we realized a bidirectional amplifier using a dual-band −3 dB 90° branch line coupler integrated with two of the proposed reconfigurable reflection amplifiers. This bidirectional amplifier is a two-port bilateral amplifier. The measured reflection gains show at least 10 dB transmission gains ( ${S} _{21}$ and ${S} _{12}$ ) at operation frequency bands. The proposed reconfigurable bidirectional amplifier is then used in a dual-band Van Atta array. The proposed active retrodirective system outperformed passive Van Atta array by 5 dB gain with only half the number of antenna elements. Each component is investigated analytically and analyzed by advanced design system. Fabricated circuits are measured and show good agreement with simulations.

This paper presents a Doherty power amplifier (DPA) based on asymmetric cells using an even input power drive and an appropriate peak fundamental current ratio (FCR) between the peaking amplifier and the carrier amplifier. Using an appropriate output combiner and an even input power drive for the DPA, not only better load modulation but also enhanced power gain can be achieved. After providing an analysis for the fundamental currents, a design guide for the proposed DPA using the peak FCR is presented. For verification, conventional and proposed DPAs were designed using GaN-HEMTs for the 2.14-GHz band. Using a downlink long-term evolution signal having a peak-to-average power ratio of 6.5 dB, comparably better performances were achieved than the conventional DPAs, such as a high power-added efficiency of 55.7% and a power gain of as high as 16.6 dB, at an average output power level of 36.9 dBm.

In this contribution, a gallium nitride-based 1 GHz Doherty amplifier with in situ waveform measurement capability is presented. With this measurement approach, the high frequency time-domain voltages and currents can be measured directly within the circuit. Therefore, directional couplers are integrated into the output matching network of the carrier and the peak amplifier. In contrast to other measurement techniques for investigating amplifiers under laboratory conditions, with this approach, a more in-depth investigation of realized power amplifiers can be carried out under operational conditions, e.g., for tuning. Especially, it is possible to characterize the interaction of the carrier and the peak amplifier. Hence, to the best knowledge of the authors the load modulation of a Doherty amplifier at the fundamental and the higher harmonics is measured for the first time.

A new interstage matching technique has been proposed and successfully applied to a ${D}$ -band amplifier in a 65-nm CMOS technology. The proposed technique is based on a simultaneous conjugate matching at the interstages of multistage amplifiers at two frequencies, resulting in an increased bandwidth. The six-stage amplifier designed based on this technique shows a peak gain of 13.8 dB at 113.7 GHz with a 3-dB bandwidth of 11.2 GHz (110.6–121.8 GHz) without balun loss compensation, while consuming a dc power of 40 mW. Measured noise figure shows a minimum value of 10.8 dB at 115 GHz. The output $P_{1\,\text {dB}}$ and the saturation output power $P_{\mathrm{ sat}}$ are −14 and −3 dBm, respectively. The circuit occupies an area of $1100 \times 550~\mu \text{m}^{2}$ .

A new biasing scheme is proposed for transistors used in power-amplifier applications. In the proposed biasing scheme, a constant current source is used as the power supply for the transistor’s output terminal. A whole new family of amplifier classes can be defined using this biasing scheme. Analytical equations are obtained and verified for current and voltage waveforms of a current-biased transistor for both resistive and tuned load impedances. Using the proposed current biasing scheme, the transistor presents completely different behaviors compared with the conventional voltage biasing scheme. These properties can be utilized for new design concepts and can provide new possibilities in the future designs and applications. Some of the differences between current-biased and voltage-biased amplifiers are discussed. One of the different behaviors shown by the current-biased transistor amplifiers is the reversed load modulation. Using this property of the current-biased amplifiers, a reversed modulation dual branch (RMDB) amplifier structure is proposed for ultra-wideband high efficiency at power back-off. Due to the reversed load modulation of current-biased transistors, a multibranch amplifier can be implemented to obtain high efficiency at power back-off without the need for an impedance inverter at the output of the current-biased amplifier. By using the proposed amplifier structure, a wideband RMDB amplifier was fabricated and tested exhibiting higher than 37% efficiency for long-term evolution (LTE) signals in 0.8–2.2-GHz bandwidth, which is equivalent to 93% fractional bandwidth.

This paper presents a method of improving efficiency for the two-stage Doherty power amplifier (DPA) using the optimized current of the peaking amplifier. The DPA has a two-stage structure for both the carrier and peaking amplifiers. The first stage of the peaking amplifier has an adjusted bias condition for a near Class-B operation, while the first stage of the carrier amplifier has a higher Class-AB operation. The gain expansion of the first stage due to its lower gate bias helps the second stage of the peaking amplifier to be biased for light Class-C operation and to have steeper turn-ON characteristics, which leads higher peak output power and higher back-off efficiency. The two-stage DPA was designed for the 2.655-GHz band. Using a downlink long-term evolution signal with a signal bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, the overall power gain of 25 dB and a peak output power of 54.2 dBm are experimentally obtained. Using an optimized shape of the peaking amplifier's current, a drain efficiency (DE) of 53% and an adjacent channel leakage power ratio of -30 dBc were obtained at an average output power of 47.8 dBm. A DE of 56.8% and an adjacent channel leakage power ratio of -25 dBc were also obtained at an average output power of 49.5 dBm.

Accurate offset line design of Doherty amplifier is investigated to compensate the phase variation of the carrier and peaking amplifiers. The offset line at the peaking amplifier not only blocks the power leakage to the peaking amplifier at the OFF-state, but also assists in the load modulation like the offset line at the carrier amplifier. However, with the conventional offset line, the load is not properly modulated due to the phase variation of the class C peaking amplifier. Since the offset lines at the carrier and peaking power amplifiers (PAs) properly eliminate the reactive parts during the Doherty load modulation, the offset lines can handle the phase variation also. To compensate the phase variation, additional lines are added at the carrier and peaking amplifiers for the proper load modulation. With the new offset line, the load of the peaking amplifier can be properly modulated and the efficiency at the high power region is increased. In addition, the efficiency at the low power region is also increased due to the larger load of the carrier amplifier at the power region. The enhanced performance is validated by the Doherty PA employing CGH40045 devices at 1.94 GHz, applying drain bias voltage of 50 V. For the long term evolution signal with a 6.5 dB peak-to-average power ratio, the Doherty amplifier with the new offset line delivers a drain/power-added efficiency of 57%/54.8% which is 3.5%/3.1% higher than that with the conventional offset line at an output power of 45.4 dBm with the linearity −48.3 dBc using digital predistortion linearization.

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

We present a linear two-stage power amplifier (PA) for UMTS terrestrial radio access (UTRA) applications. The PA has been designed using a standard 28-nm complementary metal–oxide–semiconductor process. It includes an on-chip input matching network, a predriver stage, and an on-chip output matching network. Additional process-voltage-temperature compensation circuits and electrostatic discharge protection have been implemented on-chip. A differential triple-stack transistor array acts as transconductance circuit and generates watt-level RF output power. Measured saturated output power is more than 31 dBm and peak power-added efficiency is 33% for sinusoidal operation at 1.8 GHz. When applying memoryless digital predistortion (DPD) for 3rd Generation Partnership Project (3GPP) UTRA test vectors, an adjacent-channel leakage ratio of $\leq -$ 33 dBc at $\pm$ 5 MHz for 26.5-dBm output power is achieved. A corresponding error-vector magnitude of $\leq$ 1.7% can be measured when using memoryless DPD.

This paper reports a fully integrated 40-nm CMOS power amplifier (PA) for E-band applications. A neutralized bootstrapped cascode amplifier (NBCA) topology is proposed to enhance the power gain and output power at millimeter wave (mm-Wave) frequencies while maintaining the stability. A broadband 4-way differential parallel-series power combiner is employed to further increase the output power. Besides, both interstage and input passive networks are optimized to improve the bandwidth and common-mode stability. Occupying 0.25 ${\rm mm}^{2}$ , the proposed PA achieves a measured output power of 22.6 dBm with 19.3% peak power-added efficiency $(PAE_{MAX})$ . The 2-stage PA has a measured power gain of 25.3 dB.

In this paper, a new Doherty amplifier architecture along with an analytical based design methodology is proposed. The proposed architecture uses novel three-port network as the output matching/combining network (OMCN). The three-port OMCN performs the power combining for any arbitrary output power ratios from the two transistors of the Doherty amplifier. It also performs the impedance matching from any arbitrary complex load impedance to the optimum impedances for both transistors at peak output power. Commonly in Doherty amplifiers, an optimum performance at peak power and a sub-optimum performance at power back-off are often obtained. Using the proposed output network, optimum performance can be reached at power back-off, as well as at peak power. Another three-port network is proposed for input matching/dividing network (IMDN) at the input of the proposed Doherty amplifier. The three-port IMDN is designed to perform the power division with any arbitrary division ratio, adjust the arbitrary phase difference between the input signals to the two transistors, and provide the impedance matching from any arbitrary complex source impedance to the optimal source impedances for the two transistors. To verify the provided theory, two prototype amplifiers are designed and tested. A 12-W amplifier is designed for a 50- $\Omega$ source and load impedances at 1 GHz. Another 12-W amplifier is designed at 1 GHz for complex source and load impedances. Both amplifiers have efficiency of higher than 50% at 7-dB output power range.

This paper presents the concept and the detailed analysis of a sequential power amplifier with Doherty-type active load modulation (SPA-D). By introducing a Doherty-type output combiner into the conventional sequential power amplifier (PA), highly efficient amplification over broadband and wide dynamic range for the reconfigurable output power back-off can be achieved. The proposed amplifier mimics both the sequential and the Doherty PAs by exploiting the active load modulation region that has not been considered in the design of Doherty amplifiers. A broadband SPA-D prototype having 8-dB output back-off power (OBO) is designed and implemented. The experimental results exhibit drain efficiencies of 50%–75% at 7–10-dB OBO and 57%–70% at peak power with Doherty-like behavior over 700-MHz bandwidth centered at 2.35 GHz. The ability to easily reconfigure the breakpoint is experimentally verified, providing a convenient means for optimizing the amplifier efficiency according to various wireless standards. In addition, by using a memoryless digital predistortion, the spectrum emission mask required for long-term evolution down link can be fulfilled, making it well suited for applications in modern wireless transmitters.

A microwave Doherty power amplifier (DPA) consists of a carrier amplifier (CA), a peaking amplifier (PA), and an impedance inverting network. In this paper, a novel DPA topology with neither the impedance inverting network nor offset lines is proposed. This topology enables the enhancement of amplifier bandwidth and achieves a more compact amplifier size. To remove the impedance inverting network and to realize high efficiency at large back-off power level, the output-matching network of the CA is designed to realize high performance both at a low signal power level in the off-state of the PA and at the saturated signal power level. A 1.9-GHz series-connected load Doherty power amplifier without an impedance inverting network is designed and fabricated using GaN HEMTs. The amplifier achieves a power-added efficiency (PAE) of 50% under a 6-dB output back-off from a 34-dBm saturated output power with a PAE of 59%. A maximum PAE higher than 44% is obtained over a frequency range of 1.63–1.98 GHz.

This paper presents a double input-double output bilateral low-pass equivalent amplifier behavioral model that takes into account input source and output load termination mismatches. The model is intended for the system-level simulation of amplifier chains subjected to wideband modulated signals, since it can predict the device's input and output scattered waves and their memory effects, in a wide range of voltage standing wave ratios (VSWR). In addition, the model extraction methodology, and its associated laboratory test bench are discussed, noting the limitations of conventional setups for behavioral model extraction and validation. The model is validated comparing the predicted and measured data of a real 15 W GaN based PA circuit attached to different loads. The obtained results show that, in terms of normalized mean square error, this model can provide ${-}30$ dB for VSWR ${ in comparison to a much poorer performance of the conventional single input-single output model.

This paper presents the design of a programmable gain amplifier (PGA) that serves as an interface between the receiver front-end and the baseband processor. The proposed PGA design is fabricated in a commercial 0.18- μm SiGe BiCMOS process with a topology consisting of two digitally variable gain amplifiers cascaded by a post amplifier and interconnected by differential wideband matching networks that presents an overall enhanced gain bandwidth product. By using the current mode exponential gain control technique, the proposed design achieves a broad 30-dB linear-in-decibel gain range, a gain-independent output 1-dB compression point better than -10 dBm, input/output return loss better than 13 dB, a ±0.75-dB gain flatness over a multi-decade frequency range from 2.5 MHz to 1.17 GHz, a measured in-band group-delay variation of 30 ps, a 35-mW power consumption, and a 0.25- mm 2 core die area.

In this paper, a surface acoustic wave (SAW)-less receiver (RX) front-end adopting switchable front-end architecture has been presented for second-generation/third-generation/fourth-generation cellular applications. Depending on the RX-transmitter (TX) frequency separation, a favorable down-mixing architecture is selected between a current-sampling mixer and a voltage-sampling mixer. The proposed switchable architecture meets the specification of an input-referred second-order intercept point (IIP2) for the SAW-less RX while minimizing the power consumption. The implemented RX front-end consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty-cycle passive mixer with IIP2 calibration circuitry, a baseband transconductor, and a trans-impedance amplifier. Fabricated in a 65-nm CMOS process, the SAW-less RX front-end provides conversion gain of 42 dB, and achieves noise figure of below 3.3 dB, out-of-band input-referred third-order intercept point of -2 dBm, and IIP2 of more than 56 dBm. It draws an average current of 14.8 mA from 1.2 V. The die area is 1.71 mm 2 .

This paper proposes an electronically reconfigurable Doherty amplifier capable of efficiently amplifying wireless signals with significant time varying average power. This paper outlines closed-form equations used to design an effective Doherty amplifier that can be driven with signals of variable power levels using a small number of electronically tunable devices. As a proof of concept, a reconfigurable Doherty amplifier prototype was designed and fabricated that efficiently amplified signals centered at 2.6 GHz with output average power levels equal to 35, 30, and 25 dBm. The measurement results obtained using continuous wave signals revealed power-added efficiencies of greater than 66%, at input power level adjustments of 21 and 16 dBm, and more than 62% when the average input power level setting was adjusted to 11 dBm. In addition, the reconfigurable Doherty amplifier, driven with a 20-MHz long-term evolution signal, was successfully linearized using a pruned Volterra series based digital predistrtion algorithm.

Constant input and output mismatch circles in the output load plane are introduced as the basis for low-noise amplifier design methodology. Optimum tradeoff between input and output matching levels results as the application of a design chart providing, at the same time, the corresponding stage transducer gain. The role of degenerative series feedback is studied and systematically embedded in the design procedure, thus providing a direct way to evaluate its optimum level.

In this paper, a new envelope amplifier (EA) scheme incorporating a linear regulator array is presented. The proposed EA achieves a higher efficiency over a wide envelope range utilizing multiple linear regulators. The linear regulators biased as multiple supply voltages are responsible for delivering a partial envelope current, ensuring high efficiency. A simulation revealed the superior performance efficiency of the proposed scheme in terms of the instantaneous envelope voltage compared with that of a conventional EA. Based on the simulation results, an envelope tracking (ET) amplifier consisting of the proposed EA was implemented using a commercially available 60-W gallium-nitride (GaN) device. The experimental results show that the implemented ET system has an overall efficiency of 47.8% and a gain of 14 dB at an average output power of 40.8 dBm. In this situation, the spectral performance is less than -49.5 dBc using the optimum digital predisotortion functionality.

One of the transformer neutralization conditions derived theoretically in previous publications is to make the coupling factor, k, of the transformer as close to one as possible, which is not easy to realize over millimeter-wave frequency range. To seek a method for neutralizing the transistor gate-drain capacitance to cope with the imperfect reverse isolation with the transformer coupling factor not necessarily being close to one, a voltage-current transformer feedback network is adopted in this paper. A phase noninverting transformer is added between gate and drain nodes of a transistor to form a voltage-current feedback. The neutralization condition of this network is derived. The effect of this network on the gain is predicted theoretically. The noise behavior of this network is also analyzed and compared theoretically with other transformer feedback structures reported in the millimeter-wave amplifier design. A Q-band three-stage amplifier using this network is designed to demonstrate the feasibility of this network. This amplifier is implemented in 90-nm low-power bulk CMOS technology. Measurement results show that this amplifier has the peak gain of 18.3 dB at 46 GHz and the reverse isolation better than 40 dB over the operation frequency range while consuming 20 mW at a supply voltage of 1.2 V, which verifies the unilateralization effect by using this network.

This paper presents a high-power high-efficiency wideband suboptimum Class-E RF power amplifier based on a packaged high-power GaN HEMT. It uses a simple double-reactance compensation and impedance transformation load network that includes device intrinsic capacitance, package parasitics, low-loss microstrip transmission lines, and lumped components. This load network makes the GaN HEMT operate in suboptimum Class-E from 900 to 1500 MHz (50% fractional bandwidth at 1200 MHz). The amplifier can operate both in continuous wave and pulsed modes over its full bandwidth without tuning. It delivers up to 180-W output power with up to 85% drain efficiency and PAE=81%. To the best of the authors' knowledge, the amplifier proposed in this work outperforms commercial grade amplifiers that operate in the same frequency band with similar output power levels. Direct applications for this amplifier include mobile satellite communications transmitters, envelope elimination and restoration digital audio broadcasting transmitters, and power stages for primary and secondary RADAR transmitters.

In this paper, a planar nine-way metamaterial power-combined amplifier implemented with microstrip grids, lumped capacitors and inductors, and power amplifiers is presented. The power-dividing/combining structure is a metamaterial lens composed of positive refractive index (PRI) material with right-handed unit cells and zero refractive index (ZRI) material with left-handed unit cells. A semi-circular interface is between PRI and ZRI materials. The infinite wavelength phenomenon in the ZRI material attains an equal magnitude and phase distribution to have an interconnection with the collinearly aligned amplifiers as a nine-way metamaterial power-combined amplifier with its input and output ports at the two focal points of a planar PRI–ZRI–PRI lens. An output power of 7.64 W with a combining efficiency of 85% is measured at 1.008 GHz. Through the field measurement to each unit cell, the dividing/combining phenomenon is experimentally verified and shown in a good agreement with simulation results. Furthermore, the graceful degradation characteristic of this power-combined amplifier is experimentally demonstrated.

This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

In this paper, we present a mixed-technology extended Doherty amplifier using asymmetrical voltage biasing with an LDMOS main device and a GaN auxiliary device to improve the power utilization factor of the amplifier. Moreover, in contrast to previous work, the amplifier can achieve reconfigurable back-off power ranges and an extended bandwidth without using a mixed-signal setup. The analysis also highlights the relationship between power utilization and the range of the reconfigurable back-off power level. Finally, we demonstrate that the proposed amplifier can be optimally configured for a given modulated signal to obtain the highest average efficiency. A 180-W mixed-technology prototype Doherty amplifier measured peak and back-off efficiencies greater than 50% when configured for 6, 8, and 10 dB of back-off power level at 790, 870, and 960 MHz under continuous-wave stimulus. The amplifier is highly linearizable when driven with 20-MHz long-term evolution and WCDMA signals, achieving adjacent channel power ratio of better than ${-}{\hbox{50}}$ dBc after digital pre-distortion linearization.

This paper investigates two novel triple-transistor Doherty power amplifier (DPA) designs. A compact fully differential DPA topology will be firstly introduced. Three active devices, two carriers, and one peaking are combined in a very judicious way to amplify the differential signal like what a typical Doherty amplifier does. Due to the reduction of transistor number from four for a classic differential DPA to three, the realization cost and layout dimension is reduced simultaneously. A second triple-transistor design, which amplifies an in-phase input signal and outputs a combined single-ended one, is introduced next. Similar to the differential design, a twin-carrier single-peaking configuration is applied. The functions of Doherty amplification and power combining are well integrated. Theoretical analysis will be given for a deep understanding of the operation principles regarding these two proposed architectures. To validate their effectiveness, prototypes corresponding to them are implemented based on Cree's GaN HEMT CGH40010. Experimental results demonstrate notably high drain efficiencies at saturation and 6-dB back-off regions for both of the designs.

This work describes a new power amplifier, PA, behavioral model intended to predict both the PA amplitude and phase input-output signal relationship and the average or instantaneous dc power consumption and thus average or instantaneous signal-dependent efficiency. Hence, contrary to other previously published PA behavioral models, such a model is not only capable of describing the complex low-pass equivalent fundamental zone output, but also the real low-pass current consumption output. In addition, a special attention is paid to accurately account for the multiple time-scale dynamics shown by modern GaN HEMT based high power amplifiers.

This paper derives the theory and presents measurements of a new power amplifier based on the Doherty power amplifier topology. It is theoretically shown that the proposed amplifier can simultaneously provide high efficiency at both full output power and at output power back-off, over a much improved bandwidth compared to the conventional Doherty power amplifier. It is also shown that the proposed amplifier allows reconfiguration of the efficiency in power back-off without the need of tunable elements.

This paper presents an envelope tracking power amplifier (ET PA) using a dual-mode supply modulator for handset application. The supply modulator has a combined structure with a linear amplifier and a switching amplifier. The dual-mode supply modulator operates in high-power mode and low-power mode by providing the supply voltage of the linear amplifier of 5 and 2.5 V, respectively. For 1.74-GHz long-term evolution signal with 10-MHz bandwidth, 6.44-dB peak-to-average power ratio, and 16-quadrature amplitude modulation, the ET PA delivers a power-added efficiency (PAE) of 39.8%, an evolved universal terrestrial radio access adjacent channel leakage ratio (E-UTRAACLR) of - 35.7 dBc, and an error vector magnitude (EVM) of 3.81% at an average output power of 27 dBm. The ET PA also delivers a PAE of 22.6% at an average output power of 18 dBm, which is 6.6% higher than that of the conventional ET PA and 13.1% higher than that of the standalone PA. The supply modulator is connected to a drive stage and a power stage of the PA simultaneously for further enhanced efficiency at a power back-off region. The dual-mode two-stage ET PA delivers a PAE of 38.1%, an E-UTRAACLR of - 32.9 dBc, and an EVM of 4.74% at an average output power of 27 dBm. The dual-mode two-stage ET PA also delivers a PAE of 26.3% at an average output power of 18 dBm, which is 7.8% higher than that of the conventional two-stage ET PA and 16.7% higher than that of the standalone PA.

This paper proposes a method for the experimental estimation of the stability margins in microwave amplifiers. The approach is based on measuring a closed-loop frequency response representing the linearization of the circuit about a steady-state solution. Critical poles of the amplifier are then obtained by applying conventional pole-zero identification techniques to the measured frequency response. As circuit parameters are modified, the evolution of these critical poles on the complex plane provides a practical way to assess the robustness of the design regarding its stability. Two types of common instabilities in microwave amplifiers are studied: low-frequency bias oscillations and parametric oscillations. For the low-frequency oscillations, the approach proposes the inclusion of an observation RF port into the amplifier bias path to experimentally obtain the critical poles of the circuit from a reflection coefficient measurement. Pole-placement techniques are then applied to increase the stability margin of detected critical resonances. For the parametric oscillations, pole-zero identification is applied to a frequency response obtained from a mixer-like characterization equivalent to the measurement of a “hot” reflection coefficient. The methodology is applied to two amplifier prototypes: an L-band field-effect transistor amplifier and a dual-mode WiFi-WIMAX amplifier that exhibit different kinds of unstable behavior.

In this paper, a novel dual-band transmission-line parallel Doherty amplifier architecture for active antenna arrays and base-station applications in next-generation communication systems is presented. The carrier and peaking amplifiers using GaN HEMT Cree CGH40010P devices are designed based on the reactance compensation technique to provide optimum Class-E impedance seen by the device output at the fundamental frequency across the wide frequency range achieving drain efficiencies over 73% across the frequency range from 1.7 to 2.7 GHz. In a single-carrier WCDMA operation mode with a peak-to-average ratio of 6.5 dB, high drain efficiencies of 40%-45% can be achieved at an average output power of 39 dBm with an ACLR1 of about -30 dBc at center bandwidth frequencies of 2.14 and 2.655 GHz.

In order to simplify and optimize the design process of stacked amplifiers, this paper presents a novel analytical method to dimension the input network for ideal output behavior. To verify this new structural design process, a fully integrated stacked power amplifier (PA) in 0.25-μm SiGe BiCMOS technology is proposed. The stacked architecture enables broadband matching networks, therefore the designed PA reaches a very high bandwidth of 800 MHz around 2 GHz. At 2 GHz, the small-signal gain is 23.8 dB. The output power in the 1-dB compression point and the saturated output power are 26.2 and 27.3 dBm, leading to a power-added efficiency (PAE) of 34% and 40%, respectively. Using a long-term evolution (LTE) modulated input signal without any predistortion, the amplifier reaches an average output power of 21 dBm and a PAE of 12%, fulfilling the LTE specifications in terms of adjacent channel leakage ratio and error vector magnitude.

A new Doherty amplifier configuration with an intrinsically broadband characteristic is presented based on the synthesis of key ideas derived from the analyses of the load modulation concept and the conventional Doherty amplifier. Important building blocks to implement the proposed Doherty amplifier structure are outlined, which include the quasi-lumped quarter-wave transmission line, as well as the Klopfenstein taper for broadband impedance matching. A 90-W GaN broadband Doherty amplifier was designed and fabricated and achieved an average peak output power of 49.9 dBm, an average gain of 15.3 dB, and average peak and 6-dB back-off efficiencies of 67.3% and 60.6%, respectively, from 700 to 1000 MHz (35.3% bandwidth). The amplifier is shown to be highly linearizable when driven with 20-MHz WCDMA and long-term evolution signals, achieving adjacent channel power ratio of better than -48 dBc after digital predistortion.

In this paper, a compensation technique for realizing a precise decibel-linear CMOS programmable gain amplifier (PGA) is described. The proposed PGA, employing an auxiliary pair, not only retains a constant current density but also offers a gain-independent bandwidth (BW). For verification, a compact PGA (0.1 mm2) is fabricated using a 0.13-μm CMOS process and measured. The measured gain control range is from -16 to + 32 dB with 6-dB steps, while the error deviation of the gain is less than 0.35 dB. A constant 3-dB BW of 60 MHz and an input P1dB of -35 to -5 dBm are obtained, while dissipating a lower power of 1.2 mW under a 1-V supply.

We discuss the design, realization and experimental characterization of a GaN-based hybrid Doherty power amplifier for wideband operation in the 3-3.6-GHz frequency range. The design adopts a novel, simple approach based on wideband compensator networks. Second-harmonic tuning is exploited for the main amplifier at the upper limit of the frequency band, thus improving gain equalization over the amplifier bandwidth. The realized amplifier is based on a packaged GaN HEMT and shows, at 6 dB of output power back-off, a drain efficiency higher than 38% in the 3-3.6-GHz band, gain around 10 dB, and maximum power between 43 and 44 dBm, with saturated efficiency between 55% and 66%. With respect to the state of the art, we obtain, at a higher frequency, a wideband amplifier with similar performances in terms of bandwidth, output power, and efficiency, through a simpler approach. Moreover, the measured constant maximum output power of 20 W suggests that the power utilization factor of the 10-W (Class A) GaN HEMT is excellent over the amplifier band.

Operational behaviors of the class-F and class-F-1 amplifiers are investigated. For the half-sinusoidal voltage waveform of the class-F-1 amplifier, the amplifier should be operated in the highly saturated region, in which the phase relation between the fundamental and second harmonic currents are out-of-phase. The class-F amplifier can operate at the less saturated region to form a half sinewave current waveform. Therefore, the class-F-1 amplifier has a bifurcated current waveform from the hard saturated operation, but the class-F amplifier operates as a switch at the saturated region for a second harmonic tuned half-sine waveform. To get the hard saturated operation, the fundamental load is very large, more than √2 times larger than that of the tuned load amplifier. The operational behaviors of the amplifiers are explored with the nonlinear output capacitor. Since the capacitor generates a large second harmonic voltage with smaller higher order terms, the class- F-1 amplifier with the nonlinear capacitor can deliver the proper half-sinusoidal voltage waveforms at a lower power, but the effect of the nonlinear capacitor is small for the class-F amplifier. The class-F-1 amplifier delivers the superior performance at the highly saturated operation due to its larger fundamental current and voltage generation at the expense of the larger voltage swing. The simulation results lead to the conclusion that the class-F-1 amplifier with the nonlinear capacitor is suitable topology for high efficiency. However, in the strict sense, the class- F-1 amplifier with the nonlinear capacitor is not the classical class-F-1 amplifier because the voltage-shaping mechanisms and the fundamental load are quite different. We call it the saturated amplifier since the amplifier is the optimized structure of the power amplifier operation at the saturated mode.

This paper presents a comprehensive theory of a dual-frequency complex load-matching technique based on transmission lines. The theoretical analysis is insightfully described, and the applicable regions of the design equations are specified. To substantiate the theory, a corresponding methodology is proposed to design a dual-band 10/24-GHz amplifier, which is fabricated by standard 0.13-μm 1P8M CMOS technology. This amplifier involves synthetic quasi-TEM transmission lines to build the dual-frequency matching circuits. The comparisons between simulations and on-wafer measurements are reported to establish the feasibility and flexibility of the presented technique in microwave applications.

A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage (VDD = 15 V) envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A WCDMA envelope-tracking RF PA at 2.14 GHz, including a GaN field-effect transistor RF stage, has an overall drain efficiency above 51%, with a normalized power root-mean-square error below 1.2% and an adjacent channel leakage ratio of -49 dBc at 5-MHz offset using memory-effect mitigation digital pre-distortion, at an average output power above 2 W and a gain of 10 dB.

Mathematical analysis of Doherty amplifiers have assumed many simplifications. Most notably, the peaking amplifier does not contribute power into the load and the peaking stage has an observed impedance of infinity. This paper will show that these simplifications impair the performance of a single-input Doherty amplifier and that phase tuning for compensation is needed to improve the overall system performance. The dual-input Doherty amplifier is capable of overcoming the limitations of power-dependent phase imbalance and phase compensation lines at the input of the peaking stage; however, the characterization of such an architecture is not straightforward. A new measurement technique is proposed to measure dc current, dc voltage, and output power levels to allow unique characterization of a dual-input Doherty amplifier. Phase compensation lines at the input of the peaking amplifier will be shown to be not required, as long as correct offset lines are calculated for both the carrier and peaking stage and that the λ/4 transmission-line length is not necessarily required for active load-pull. Results of a dual-input inverse load modulated Doherty amplifier are presented where the peaking stage delivers 10 dB less of maximum output power than the carrier, while still maintaining Doherty behavior. The peaking stage can therefore be implemented with a smaller device than the carrier.

A high-efficiency envelope tracking power amplifier for long-term evolution (LTE) handset mobile terminals is presented. The envelope amplifier consists of a wideband buffered linear amplifier as a voltage source and a hysteretically controlled switching amplifier as a dependent current source. The linear amplifier has a high current drive capability of approximately 500 mA while consuming only 12 mA of quiescent current. The impact of envelope shaping on system efficiency and stability is investigated. The envelope amplifier is implemented in a 0.15- μm CMOS process and tested with a GaAs HBT RF power amplifier. For a 20-MHz LTE signal with 6.6-dB peak-to-average power ratio, an overall efficiency of 43% is achieved at 29-dBm RF output power level with relative constellation error below 1.9% after digital pre-distortion.

A distortion reduction method for a newly developed GaN HEMT Doherty amplifier (DA) with a series-connected load operating at 1.8 GHz is presented. Differing from conventional DAs with shunt-connected loads, the newly developed DA with a series-connected load has high input impedance, resulting in low-loss impedance matching and high-efficiency power combining. A distortion cancellation mechanism and its condition are derived, where odd-order nonlinear factors of transistors are considered, so as to retain inherent distortion cancellation between a peaking amplifier and a carrier amplifier. The validity of the design method is demonstrated using the developed 1.8-GHz GaN HEMT DA with a series-connected load. The third-order intermodulation distortion of the DA is improved by more than 15 dB at output powers from 5 to 20 dBm, compared to the case giving priority to power efficiency. The developed amplifier delivers a power-added efficiency (PAE) of 31% at an output power of 24 dBm, corresponding to 10-dB input backoff from a saturated output power of 31 dBm with a PAE of 58%. The proposed distortion reduction method can also be applied to shunt-connected-load-type amplifiers of other devices.

To predistort the signal of an analog-predistortion power amplifier system, this paper proposes a variable gain amplifier (VGA) topology that gives an optimized linearity and bandwidth performance while having a continuous, linear-in-decibel gain control curve. The design employs a self-biased differential amplifier with a dynamic current source to provide gain and linearity. The overall VGA gain is then controlled by a highly linear variable attenuator connected at the output of the amplifier. This separated controlling stage allows the VGA to have a continuous and linear-in-decibel gain curve without sacrificing the bandwidth and linearity of its amplifier stage. A VGA designed with such topology has been fabricated in a standard 0.18- μm CMOS technology. Targeted for wideband code-division multiple-access applications, the VGA has a maximum gain tuning range from -13.5 to 13.5 dB, a bandwidth better than 1.8 GHz (380 MHz to 2.2 GHz), and a worst case input P1dB better than -5 and -3.6 dBm, respectively, at 850 MHz and 1.95 GHz. The post-attenuated structure also gives the VGA a noise figure as low as of 4.9 dB at 1.95 GHz. To our knowledge, the design demonstrates the best linearity performance and has other characteristics that are equivalent with other VGAs.

A comprehensive method of designing a broadband Doherty power amplifier is presented in this paper. The essential limitations of bandwidth extension of a Doherty power amplifier are discussed based on the proposed structure of the Doherty power amplifier, which also takes the output matching networks of both sub-amplifiers into account. The broadband matching is realized by applying the simplified real frequency technique with the desired frequency-dependent optimum impedances. GaN transistors were selected to implement the circuit structure.

This paper presents a modified parallel-circuit class-E amplifier that accommodates devices with larger output capacitances, recovering the class-E operating conditions. The finite inductor in the parallel circuit topology is replaced by a more suitable network composed of a series inductor and additional subharmonic resonators. Analysis of the class-E amplifier allows to determine the required frequency-domain response of this new network. Derivation of the circuit elements of the proposed network is shown in detail, and a design procedure for this modified class-E is provided. The analysis is validated by simulation and design of a test board. Measurements of the test board showed a drain efficiency of 80.7%, power-added efficiency of 78.6%, and output power of 4.91 W at 434 MHz, exhibiting levels of efficiency similar to that obtained by other amplifiers using the same device, but at much lower frequencies. According to the authors' knowledge, this study represents the first systematic approach to design class-E power amplifiers at UHF using devices with larger COUT by taking into account the use of arbitrary finite-feed class-E topologies.

This paper describes the analysis of an optimized envelope shaping function for the envelope tracking power amplifier (ET PA) and its implementation. The proposed shaping function, which is sweet spot tracking with crest factor reduction, improves the efficiency and output power of the power amplifier (PA), as well as its linearity. For an accurate simulation of the supply modulator, an equivalent model of the PA under the envelope shaping is suggested. To achieve high efficiency and wide bandwidth, the CMOS supply modulator has a hybrid structure of a switching amplifier and a linear amplifier. The fabricated ET PA delivers higher efficiency and better linearity than standalone PA for the wideband code division multiple access and long-term evolution signals.

A new supply modulator architecture for robust performance against the battery voltage variation is presented. The resulting modulator is an optimized power management integrated circuit (PMIC) for an envelope tracking (ET) power amplifier (PA). The basic topology of the PMIC is based on a hybrid switching amplifier combining a wideband class-AB buffered linear amplifier and a highly efficient switching-mode buck converter in a master-slave configuration. The additional boost converter regulates the supply voltage of the linear amplifier, while the supply of the buck converter is directly coupled to the battery. The proposed supply modulator achieves max/min efficiencies of 76.8/69.3% over the entire battery voltage range. The ET PA is operated at 4.5 V, providing higher output power, efficiency, and gain than at nominal 3.5-V design. The robust performance of the proposed PMIC is demonstrated.