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This article investigates the single-event effects on 16-nm bulk field-effect transistors (FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation. These upsets are analyzed and classified according to voltage, linear energy transfer of ions, data patterns, and fail bit patterns. The analysis suggested a characteristic charge collection mechanism attributable to the FinFET structure. Estimation of a unique sensitive area shape based on cross sections is also discussed. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) with an interleaved bitmap design is of special concern for space applications because the interleaving architecture improves the efficiency of error correction code for single-event upsets (SEUs) in a harsh radiation environment. However, most of the interleaving layout is kept unreleased from the manufacturer, and determining the interleaving parameters of an intact SRAM is a challenge for the radiation hardening system. This work proposed a theoretical decryption model of conventional interleaved bitmaps based on the principle of multiple-bit upset (MBU) correlation analysis. The decryption method was practically implemented with a commercial SRAM, and its unknown interleaving architecture was resolved by the spatial correlation and MBU distance upon SEU fault injection attack with 252Cf source. The disclosed interleaving architecture, the subbyte characteristics, and the bit subblock distribution of the device under test (DUT) are in good agreement with the bitmap obtained with SEU mapping of the microbeam. This work demonstrates the valid and robust SRAM layout decryption model and provides a viable approach for evaluating correction efficiency and component reliability in the radiation hardening system. [ABSTRACT FROM AUTHOR]

We study the radiation environment near the terahertz (THz) dump of the CERN Linear Electron Accelerator for Research (CLEAR) electron accelerator at CERN, using FLUktuierende KAskade in German (FLUKA) simulations and single-event upset (SEU) measurements taken with 32-Mbit Integrated Silicon Solution Inc. (ISSI) static random access memories (SRAMs). The main focus is on the characterization of the neutron field to evaluate its suitability for radiation tests of electronics in comparison with other irradiation facilities. Neutrons at CLEAR are produced via photonuclear reactions, mostly initiated by photons from the electromagnetic cascades that occur when the beam is absorbed by the dump structure. Good agreement is generally found between the measured single-event upset (SEU) rates and the expected values obtained from FLUKA simulations and the known SEU response of the ISSI SRAMs to neutrons, while one position is found to be potentially affected by photon-driven SEUs. [ABSTRACT FROM AUTHOR]

Impact of high total ionizing dose (TID) irradiation on stability of 65 nm static random-access memory (SRAM) cells is investigated in this article. The stability of 65 nm SRAM cells is measured not only by the SRAM array but also by the independent cell test structure. The test chip has been subjected to a TID irradiation of 200 Mrad(Si). Experimental results show a reverse data pattern imprinting effect, i.e., irradiated 65 nm SRAM cells are more inclined to the complementary TID data pattern, and the above asymmetry of irradiated 65 nm SRAM cells is due to the bias-dependent shift in threshold of the pull-down nMOSFETs constituting the SRAM cell. [ABSTRACT FROM AUTHOR]

The contribution of mymargin elastic scattering to upsets caused by 1–10-MeV terrestrial neutrons in a 40-nm bulk SRAM and the influence of cascade recoils are investigated using Geant4 simulations. It is shown that elastic scattering, rather than ($n$ , $p$) or ($n$ , $\alpha$), is a dominant mechanism, contributing ~66% of the total upsets induced by 1–10-MeV neutrons. The dominance is attributed to the major role it plays in upset cross sections below ~6 MeV, and the abundance of lower energy neutrons due to $E^{- 1}$ dependence characteristic of the terrestrial neutron differential flux below 10 MeV. After considering ionization energy deposition of cascade recoils in Geant4 simulations, remarkable rises in upset cross sections of 27%, 18%, and 9% are observed for reactor, 2.5- and 1–10-MeV neutrons, which are the consequence of cascade recoils induced by primary Si ions. In-depth TRIM calculations on the ionization energy deposition of incident Si ions and cascade recoils have been performed, revealing that the underlying mechanism is the reduction in the threshold energy of Si ions from ~50 to ~30 keV if cascade recoils are taken into account. [ABSTRACT FROM AUTHOR]

For advanced technology nodes, the static random access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high-energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for fin field-effect transistor (FinFET) inhibits the charge collection compared to the planar transistor structure. In this work, heavy-ion tests were conducted for 16-nm bulk FinFET dual-port SRAMs at two high linear energy transfers (LETs) of 60 and 85 MeV $\cdot $ cm2/mg. The non-saturating behavior of the SEU cross sections and event cross sections for a bit cell is observed even over the LET of 60 MeV $\cdot $ cm2/mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show that the single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high-energy particles. The parasitic bipolar effect (PBE) is also serious for 16-nm FinFET SRAMs as former planar SRAM, but the charge-sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this article will help designers estimate the error correcting code (ECC) and interleaving design parameters for radiation-hardened SRAM designs at the 16-nm FinFET process. [ABSTRACT FROM AUTHOR]

SRAM-based field-programmable gate array (FPGA) vendors typically integrate error correction codes (ECCs) into the configuration memory to assist designers in implementing scrubbing mechanisms. In most cases, these ECC schemes guarantee the correction of single- and double-bit errors per configuration frame but fail to correct upsets with higher multiplicity in a single frame caused by a single event. This phenomenon has been observed in modern commercial-off-the-shelf FPGAs. Bit interleaving schemes are used in some FPGA families to scatter the multiple upsets into more than one frame, but this does not fully resolve the problem of uncorrectable errors. In this article, we propose a configuration memory scrubbing approach for SRAM-based FPGA devices, which combines the embedded ECC logic with an interframe, interleaved parity code to build a mixed 2-D coding technique. The proposed technique improves the multiple-bit error correction capabilities of the on-chip ECC scheme while keeping the error correction latency and hardware cost low. The scrubbing concept has been validated under heavy-ion irradiation, where it succeeded in correcting all the single and multiple upsets observed during the radiation experiment. [ABSTRACT FROM AUTHOR]

The impact of transient ionizing radiation effects on a 4-Mb static random access memory (SRAM) circuit which has an input–output (IO) supply voltage and a core supply voltage was studied. The experimental results indicate that a longer time is required to restore minimal operating voltage for core supply voltage. Based on the 180-nm bulk CMOS technology, 3-D mode numerical simulations with technology computer-aided design (TCAD) show that the parasitic bipolar effect plays a significant role in discrepancy in the recovery process between supply voltages. This effect will be discussed in depth in this article, and the simulation results illustrate that the n-well contact has a great impact on the operation mode of parasitic bipolar. Meanwhile, the supply voltage disturbance mitigation methods are presented through improving power supply voltage and placing more n-well contacts. [ABSTRACT FROM AUTHOR]

This work analyzes the performance of the reduced precision redundancy (RPR) error mitigation technique using the fast Fourier transform (FFT) as a case study. To this purpose, several configurations of an FFT IP design were implemented in field-programmable gate array (FPGA) using reduced precision triple modular redundancy (RP-TMR) and tested under proton irradiation and fault injection. The cross section, the sensitivity to common-mode failures (CMFs), and the signal-to-noise ratio of these configurations were evaluated. The results of the radiation experiments and fault injection campaigns are in agreement and show that the RP-TMR technique may be used as an alternative to triple modular redundancy (TMR) if small errors can be tolerated, as it has a good performance in terms of error correction capabilities, area usage, and sensitivity to critical errors. [ABSTRACT FROM AUTHOR]

We conducted a real-time soft-error rate characterization of CMOS bulk 65-nm static random access memories (SRAMs) subjected to fusion neutrons during deuterium–deuterium (D-D) plasma operation at W–tungsten–Environment in Steady-state Tokamak (WEST). The test equipment, installed in the experimental hall at several locations of the tokamak, was irradiated during machine shots by a flux of particles dominated by primary 2.45-MeV neutrons. Real-time neutron metrology, neutron spectrometry, complementary characterization with monoenergetic neutrons, and Monte Carlo numerical simulations at both material and circuit levels have also been performed to analyze the experimental data. Our results suggest that higher energy neutrons, simultaneously produced by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, play a significant role in the radiation response of SRAMs for which multiple cell upsets are detected and cannot be attributed to D-D neutrons. [ABSTRACT FROM AUTHOR]

The effects of total ionizing dose (TID) on static random access memory (SRAM) physical unclonable functions (PUFs) are studied through X-ray and proton irradiation of commercially available SRAM. Negative shifts in the fractional Hamming weight (FHW) were measured with increasing TID, indicating a migration of bistable cells toward logic low. Additionally, positive shifts in the intra-die fractional Hamming distance (FHD) were measured and indicate changes to the virtual fingerprint of an SRAM PUF with TID, especially in devices that were dosed while holding data. Shifts in inter-die FHD were negligible, allowing individual SRAMs still to be easily identified based on the FHD between a known and unknown sample even after moderate amounts of TID. In some cases, SRAMs could still be identified by their PUFs after the devices had failed. In all cases, the irradiated SRAM devices retained their virtual fingerprint after recovery through annealing. [ABSTRACT FROM AUTHOR]

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat. [ABSTRACT FROM AUTHOR]

Pulsed-laser testing is used to accurately determine single-event latchup (SEL) thresholds for static random-access memories (SRAMs) with different body-tie-to-drain spacings on a mixed-signal application-specific integrated circuit (ASIC), a study that could not be completed using only broad-beam heavy-ion testing. Two distinct approaches were employed with the first approach, an empirical correlation method, exploiting the complementary nature of broad-beam heavy-ion and laser testing. Various single- and dual-port SRAMs exhibited SEL thresholds ranging from 1 MeV-cm2/mg to over 100 MeV-cm2/mg, with a dual-port device possessing the smallest body-tie-to-drain spacing being latchup immune at the highest available test conditions (>300 MeV-cm2/mg). These results have been used to inform a follow-on ASIC design resulting in a significant improvement in chip-level SEL sensitivity. The second approach, a calculational method, uses pulsed-laser measurements and charge-deposition modeling to predict linear energy transfer (LET) thresholds without heavy-ion data. This calculational approach agrees with the empirical approach and therefore shows promise as a predictive tool for SEL threshold estimation, but further validation is required. Overall, these approaches can be effective tools for evaluating SEL susceptibilities and mitigation strategies. [ABSTRACT FROM AUTHOR]

Static random access memories (SRAMs) are prone to a single-event upset (SEU), also known as soft errors, due to transient noise caused by a single strike of radiation. Beam testing has been extensively used to measure the SEU cross section of SRAMs as a function of the linear energy transfer (LET) of charged particle radiation. The evolution of the cross section as a function of LET is called the cross section curve, which plays a vital role in upset rate analysis for hardness assurance. Various analytical models have been developed to describe SRAM SEU cross section curves, and they have proven to be useful in reducing the cost of beam testing as well as revealing the physics behind test results. However, they involve arbitrary parameters, which make it challenging to predict cross section curves without any beam results. Moreover, the current method of analyzing cross section curves or the LET dependence of cross sections relies on a model different from that is used in the analysis of power-supply-voltage dependence, which is becoming increasingly important because of the demand for low-power operation. To overcome these problems, this article proposes a unified equation that describes both LET and the power-supply-voltage dependence of SRAM SEU cross sections. It comprises only parameters that are physically clear and familiar to SEU researchers. As well as giving possible constraints, comparisons with data from the literature suggest it can be applied to SRAMs fabricated in bulk and silicon-on-insulator (SOI) processes across generations from the early 1000-nm-scale to the current 10-nm-scale technology nodes. [ABSTRACT FROM AUTHOR]

An 8T cell is proposed to improve reliability and radiation tolerance of the static random access memory (SRAM) physical unclonable function (PUF) which is formed by adding two cascode pMOS transistors biased at the ON-state to standard 6T cell. Two custom SRAM PUFs in the same batch consisting of 6T cells and 8T cells using the 28 nm fully depleted silicon on insulator (FDSOI) process were used to evaluate the characteristics with respect to bit error rate (BER) and interchip Hamming distance (HD) with an increase in Co-60 total ionizing dose (TID), various supply voltages, ramp-up time, and temperature. According to the experimental result, the BER of the proposed SRAM PUF decreased by $2\times $ under various conditions with better radiation tolerance compared with the 6T one. Both kinds of SRAM PUF have similar interchip HD closed to 50%, but the proposed prototype has less variation, thanks to better reliability. When supply voltage, ramp-up time, and temperature conditions were set to 400 mV, 100 ms, and 25 °C, respectively, the proposed SRAM PUF can achieve the lowest BER of only 0.72%. Some design tips of reliable and rad-hard SRAM PUF are given as design guidance. [ABSTRACT FROM AUTHOR]

A silicon detector with a fast electronics chain is used for the dosimetry of protons in the range 0.5–5 MeV at the Centro Nacional de Aceleradores (CNA) 3 MV Tandem laboratory in Seville, Spain. In this configuration, measurements can be performed in pulsed mode, using a digitizer to record event-by-event proton energy depositions. The distributions of deposited energy were obtained thanks to a calibration with an alpha source. Measurements of flux and deposited energy are used to enable single event effect (SEE) testing on selected static random access memories (SRAMs). [ABSTRACT FROM AUTHOR]

In the aerospace industry, commercial-off-the-shelf (COTS) static random access memories (SRAMs) are a cost-effective solution for obtaining high performance at the system level, which is difficult to obtain using space-qualified components. In addition, the usage of dynamic voltage scaling (DVS) is commonly used in space environments, where low power consumption is a critical issue. This article presents an analysis of the sensitivity against single-event upsets (SEUs) of various COTS bulk SRAMs and advanced low-power SRAMs (A-LPSRAMs) against proton radiation when using DVS to save power. Experimental results will show clear evidence that the sensitivity to SEUs increases when the power is lowered. Two sets of successive technologies (130-, 90-, and 65-nm bulk SRAMs, and 150- and 110-nm A-LPSRAMs) are evaluated against 15-MeV protons and compared with results of 14-MeV neutrons presented in a previous work. Experimental data are finally compared with analytical simulations obtained by using the multiscales single-event phenomena predictive platform (MUSCA-SEP3) Monte Carlo tool to predict the effect of DVS on the SEE sensitivity on more modern technologies in the ITRS/IRDS roadmap. [ABSTRACT FROM AUTHOR]

Configuration random access memory (CRAM), which consists of the static random access memory susceptible to single event upset (SEU), configures all of the user logic in field-programmable gate array (FPGA). In this article, we evaluate the impact of SEU in CRAM on the image-based lane tracking for autonomous driving via neutron irradiation experiments. In the experiments, the cross section of bit upsets and its corresponding single event function interrupt (SEFI) in the logic function of image processing are measured. By using a virtual driving environment, we observe whether a bit upset finally induces a severe SEFI of the system failure. The system failure is observed by an abnormal behavior on the virtual autonomous car driving by lane tracking. Experimental results show the bit upset has a maximum probability of 23% to induce SEFI and finally 8% of the bit upsets lead to failures in lane tracking. All the SEFIs observed in irradiation experiments are reproduced in fault injections with the same bit address. The cross section of SEFI was estimated in fault injections with reasonable precision. Moreover, we evaluate the improvement of system reliability by the error correction against soft errors. Our evaluation result shows that the error correction within the period of two-frame processing time could reduce the 74% SEFI cross section, but it has little benefit for system failure cross section if an error happens during the period of the image processing. [ABSTRACT FROM AUTHOR]

On-detector digital electronics in high-energy physics (HEP) experiments is increasingly being implemented by means of static random access memory (SRAM)-based field programmable gate arrays (FPGAs), due to their reconfigurability, fast data processing, and transfer. Radiation-induced single-event upsets (SEUs) in the configuration hinder the correct operation, since they may alter the programmed routing paths and logic functions. In most data acquisition systems, data from clustered front-end modules are aggregated by a single board, which then transmits data to off-detector electronics for acquisition and triggering. In this work, we present a novel scrubber capable of correcting radiation-induced upsets in the configuration of SRAM-based FPGAs by majority voting across clustered modules. We designed it for the Aerogel Ring Imaging CHerenkov (ARICH) counter of the Belle II experiment at the KEK Laboratory, Tsukuba, Japan. We discuss the architecture of the system and its implementation in a Virtex-5 FPGA, in the aggregator board, for correcting the configuration of up to six Spartan-6 LX45 FPGAs, on pertaining front-end modules. We discuss results from neutron irradiation tests at the TRIGA reactor of the Jožef Stefan Institute, Ljubljana, Slovenia, which show that our solution corrects an average of 6.2 k upsets in each target FPGA before the failure of the scrubber. Moreover, with respect to the Xilinx soft error mitigation (SEM) controller, our design improved the mean time before failure of data readout by 30%. [ABSTRACT FROM AUTHOR]

The static random access memory (SRAM) of an ultralow power system-on-chip (SoC) was tested for single-event upsets (SEUs) using alpha particles and neutron beam sources. The measurements are compared to those of an SRAM-based field-programmable gate array (FPGA), built on a similar technology node. The results reveal opposite trends in the two devices regarding the upsets of the logic states, as well as differences in the dependence of SEU cross section (CS) on the operation voltage. The sensitivity of the SoC SRAM to multiple bit upsets with the different radiation sources is analyzed as well. The results demonstrate that the unique SoC design, which enables complete near/subthreshold operation, does not compromise the SoC bit upset tolerance compared to devices of similar technology node which operate at higher voltages. [ABSTRACT FROM AUTHOR]

Field-programmable gate arrays (FPGAs) are susceptible to radiation-induced effects that can affect more than one memory cell. Radiation-induced microsingle event functional interrupts (micro-SEFIs) are one of such events that can upset several bits at a time. These events need to be studied because they can overcome protection from techniques such as triple modular redundancy (TMR) and error correction codes (ECCs). Extracting these events from radiation data helps to understand if specific resources of the FPGA are more vulnerable and the extent of this vulnerability. This article presents a method based on statistics and fault injection to identify micro-SEFIs from beam-test data in the configuration memory and block RAM (BRAM) of SRAM-based FPGAs. The results show the cross section of these events for the configuration RAM (CRAM) and BRAM for three families of Xilinx SRAM FPGAs gathered throughout three neutron tests. This article also contains data from a fault injection campaign to uncover the possible CRAM source bits causing micro-SEFIs in memory look-up tables (LUTs) of Xilinx 7-series and Ultrascale devices. [ABSTRACT FROM AUTHOR]

This article presents an analysis of the multiple events [and more specifically, multiple-cell upsets (MCUs)] that may occur at successive generations of bulk CMOS static random access memories (SRAMs) operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS)/International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90- and 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various commercial-off-the-shelf (COTS) SRAMs manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45 down to 14 nm). [ABSTRACT FROM AUTHOR]

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V. [ABSTRACT FROM AUTHOR]

We present a study on the layout design of the rad-hard standard logical cells and fault-tolerant static random access memory (SRAM) cells. We used the previously developed layout-aware SPICE-based simulation technique to check the design patterns that involve sensitive node spacing and contact placement to increase the tolerance to multiple node upsets. The results of the simulations were transformed into layout design recommendations verified by the simulation and experimental data for SRAM cells with layout design supporting the recommendations. The results proved the efficiency of the proposed hardening measures. [ABSTRACT FROM AUTHOR]

Radiation-induced multiple-cell upsets (MCUs) are events that account for more than 50% of failures on triple modular redundancy (TMR) designs in SRAM field programmable gate array (FPGA). It is important to understand these events and their impact on FPGA designs to develop improved fault mitigation techniques. This article describes an enhanced fault injection (FI) method for SRAM-based FPGAs that injects MCUs within the configuration memory of an FPGA based on MCU information extracted from previous radiation tests. The improved FI technique uncovers 3 × more failures than is observable in conventional single-bit FI approaches. The results from several MCU FI experiments also show that injecting MCUs can replicate the failures observed in the radiation beam test and identify new failure mechanisms. [ABSTRACT FROM AUTHOR]

Characterizing low-energy neutrons (<10 MeV)-induced single-event upsets (SEUs) and multiple cells upsets (MCUs) is essential to validate the current standard for terrestrial soft error rate (SER) and investigate its enhancement. Following our preliminary analysis on the contribution of the low-energy neutrons to the total terrestrial SER at the nominal operating voltage of 1.0 V by Liao et al. (2020), this article newly presents and analyzes the data measured at the low operating voltage of 0.4 V. The dependence of SEU cross section on the neutron energy is similar between the operating voltages of 0.4 and 1.0 V, including onset energy of around 6 MeV. The existence of MCUs at 4.1-MeV neutrons was also confirmed at both the operating voltages. Based on the measurement, we approximate the dependence of SEU and MCU cross sections as Weibull functions of the neutron energy. The terrestrial SER of SEUs and MCUs was calculated by folding the Weibull function and the flux spectrum. The calculated result indicates that the SER originating from the low-energy neutrons is less than 6% in the terrestrial environment at New York and Tokyo City. We confirm that disregarding the flux of neutrons below 10 MeV in the acceleration factor calculation at accelerated neutron tests, which follows the current standard defined in JESD89, could give a reasonable SER estimation accuracy for both SEUs and MCUs. On the other hand, for covering the beams having an extremely high proportion of low-energy neutrons, considering the flux of neutrons above 6 MeV would be an option for better SER estimation. [ABSTRACT FROM AUTHOR]

In this article, we present Tool suIte for rAdiation Reliability Assessment (TIARA), an industrial version of a Monte Carlo single-event simulation platform, enabling fast and accurate soft error rate (SER) estimations. This tool is capable of simulating logic cells manufactured in several technologies such as fully depleted silicon on insulator (FD-SOI), FinFET, and planar bulk CMOS. Moreover, TIARA is able to handle many different types of radiations including by-products of neutron or proton spallation, heavy ions and alpha particles, representative of terrestrial and space environments. Three use cases are shown in this article to illustrate TIARA capabilities. The first one compares the error rate in Geostationary Earth Orbit (GEO) orbit of all flip-flop variants from a 28-nm FD-SOI library. Second one evaluates multiple-cell upsets as a function of simulated array size for static random access memory (SRAM) cells manufactured in a 40-nm bulk technology. The last one shows alpha and neutron SER results for SRAM designed in a bulk-FinFET technology. [ABSTRACT FROM AUTHOR]

The influence of ion track characteristics on single-event upsets (SEU) and multiple-cell upsets (MCUs) is investigated in 65-nm static randon access memory (SRAM) above the heavy-ion linear energy transfer (LET) threshold. The experimental results show that for the incident heavy ions with the same or similar LET but different energies, SEU cross section of low-energy ions is higher than high-energy ions when the LET values are located below the knee point of low-energy SEU event cross section curves. With the LET values increasing above the knee point, SEU cross section of high-energy ions is higher than low-energy ions. When the effective LETs of different-energy ions within the sensitive region are the same, MCU mean, MCU ratio, and MCU event cross sections of high-energy ions are greater than those of low-energy ions due to larger track radius. During the test evaluation of heavy-ion single-event effect (SEE) in nanometer devices, it may be advisable that the SEU LET threshold be obtained with low-energy ions and the SEU saturation cross section be obtained with high-energy ions. [ABSTRACT FROM AUTHOR]

Gas electron multiplier (GEM) detectors and activation foils have been used for dosimetry of thermal beamlines of a pulsed neutron source. The first is an active detector that performs measurements using the time-of-flight technique, taking advantage of the pulsed nature of the source. The same detector has been used successfully to measure the profiles of the beams. The second is a passive irradiation method that independently confirms the measured fluxes of equipment materials and mechanics analyzer (EMMA) and rotating analyzer crystal (X) spectrometer (ROTAX) beamlines of the ISIS neutron source. They feature different thermal spectra, the first being moderated with water (300 K) and the second with liquid methane (100 K). These two characterized beamlines have been used for the irradiation of microelectronics for single-event effect testing using a reference static random access memory (SRAM) module. It is shown that results are consistent and that a correction factor must be applied to scale the results on the cold beamline to the one at room temperature. [ABSTRACT FROM AUTHOR]

The distribution of single-event upsets (SEUs) in commercial off-the-shelf (COTS) static random access memory (SRAM) has generally been thought to be uniform in a device. However, process-induced variation within a device gives rise to variation within the cell-level electrical characteristic known as the data retention voltage ($V_{\mathrm{ DR}}$). Furthermore, $V_{\mathrm{ DR}}$ has been shown to directly influence the critical charge ($Q_{\mathrm{ C}}$) necessary for stored data to upset. Low-energy proton irradiation of COTS SRAMs exhibits a preference toward upsetting cells with lower $Q_{\mathrm{ C}}$. An electrical procedure is presented to map relative cell critical charge values without knowledge of the underlying circuitry, allowing customized device usage. Given cell-level $Q_{\mathrm{ C}}$ knowledge, a device can have its cells “screened” such that those with low $Q_{\mathrm{ C}}$ are not used to store data. This work presents the results such a screening process has on the SEU per bit cross section. [ABSTRACT FROM AUTHOR]

We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previous partially depleted technology generations (32 and 45 nm). The per-bit cross section is approximately an order of magnitude lower than the previous generations with a higher onset linear energy transfer (LET). No dependence on roll angle or input pattern was found. Tilt angle data follow the cosine law. Increasing the SRAM array supply voltage from the minimum tested 0.73 V to the maximum 1.08 V decreases SEE sensitivity by as much as 8%. Decreasing the p-well voltage from the nominal 0 V to the maximum −2 V increases the SEE cross section by as much as 2 ×. The n-well voltage has little effect on the SEE sensitivity due to the specifics of the transistor layout in the SRAM. Changing both the n- and p-well voltages simultaneously results in identical results as when only the p-well voltage was changed. [ABSTRACT FROM AUTHOR]

The history of integrated circuit (IC) development is another record of human challenges involving space. Efforts have been made to protect ICs from sudden malfunctions due to single-event effects (SEEs). These effects are triggered by only a single strike of particle radiation, such as an α-ray or cosmic ray, originating from our solar activity and galactic events including supernovas. This article explores how SEEs have evolved along with the progress in complementary metal-oxide-semiconductor (CMOS) digital IC technology, or device scaling, from the early micrometer-scale generations to the current nanometer-scale generations. For this purpose, focusing on basic digital elements, that is, inverters and static random access memories (SRAMs), this study collected more than 100 sets of data on four characteristic parameters of single-event upsets (SEUs) and single-event transients (SETs), both of which are undesired flips in digital logic states. The results show that all the examined parameters, such as the SEU critical charge, decrease with the device feature size. Analysis involving structure classification, such as bulk versus silicon-on-insulator (SOI) substrates and planar versus fin channels, reveals relationships between the examined SEE parameters and other device features such as the power supply voltage. All the data collected in this survey are explicitly given in tables for future exploration of IC reliability. [ABSTRACT FROM AUTHOR]

In this article, we investigate neutron-induced failures of the Galaxy S7 Edge smartphone (released 2016). Anomalous changes in the neutron-irradiated Galaxy smartphone are described in detail (e.g., device current increments up to 270 mA or overheating in the proximity of the WiFi module). The discussion of system failures includes not only visual observations, but also changes in the current and device temperature of the target smartphone. The system behavior associated with failure modes is also discussed in an effort to relate single-event effects to system malfunctions. Additionally, the test results are compared to similar studies of five products (released 2007–2015). In comparison to the failure rates among those products, the system-level failure-in-time (FIT) did not show a downward trend, although the FIT per megabit (FIT/Mbit) values of static random access memory (SRAM) declined as the technology node shrank. [ABSTRACT FROM AUTHOR]

In harsh radiation environments, it is well known that the angle of incidence of impinging particles against the surface of the operating devices has significant effects on their sensitivity. This article discusses the sensitivity underestimations that are made if particle isotropy is not taken into account, by means of an analytical study made with a single-event upset predictive platform. To achieve this goal, experimental results carried out with a commercial-off-the-shelf (COTS) bulk 130-nm nonvolatile static random access memory (SRAM) for various incident angles on 14.2 MeV neutrons are first discussed. Then, a modeling tool called multiscales single-event phenomena predictive platform (MUSCA-SEP3) is used to predict the sensitivity of this memory under the same environmental conditions. Predictions and experimental results will be cross-checked, and therefore, the feasibility of this tool will be demonstrated for testing any other incident angle. Finally, an isotropic environment and an XY SRAM array will be emulated with MUSCA in order to demonstrate that the asymmetrical cross sections that were observed experimentally for various incidence angles are due to the underlying asymmetry of the metalization/passivation layers within the device with respect to its active silicon. Conclusions will finally be drawn as for the importance of taking into account particle isotropy in radiation-ground tests. [ABSTRACT FROM AUTHOR]

This article presents an experimental study on the sensitivity of a commercial-off-the-shelf (COTS) bulk 65-nm static random access memory (SRAM) under 15.6 MeV proton irradiation when powered up at ultralow bias voltage. Tests were run on standby and while reading the memory. Results show obvious evidence indicating that decreasing the bias voltage below 1 V exponentially increases the number of observed errors. Single-bit upsets (SBUs) and multiple-cell upsets (MCUs) (mostly with vertical shapes according to the manufacturers’ layout) are reported and their behavior is analyzed in this article. Predictions on the single-event upset (SEU) sensitivity obtained with the multiscales single-event phenomena predictive platform (MUSCA-SEP3) modeling tool are also provided and compared with the experimental results. These are also compared with 14.2 MeV neutrons, showing a significant difference in the cross sections for both irradiation sources. Total ionizing dose (TID) tests and GEANT4 simulations were also run to check for the reason behind the difference in the cross section between these two particles. [ABSTRACT FROM AUTHOR]

Heavy-ion measurements are used to define a multiply nested sensitive-volume model for a 180-nm static random access memory (SRAM) test structure using the Monte Carlo radiative energy deposition (MRED) tool. We demonstrate that the fundamental assumptions of simple rectangular-parallelepiped (RPP) or integral-RPP models are inappropriate for single-event latchup (SEL) in this test structure, indicating that more advanced modeling is needed. We develop an MRED model that agrees well with latchup data at normal incidence and at roll and tilt angles of 60°. This process should facilitate estimates of SEL cross section and event rates for this and similar technologies in space environments. [ABSTRACT FROM AUTHOR]

The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from “1” to “0” were observed, whereas bit upsets from “0” to “1” were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism. [ABSTRACT FROM AUTHOR]

Multigigabit serial links implemented by means of static random access memory (SRAM)-based field-programmable gate arrays (FPGAs) are extensively used in trigger and data acquisition systems of high-energy physics experiments. Their usage is mostly in areas without radiation, due to the sensitivity of FPGA configuration memory to single-event upsets. In order to use these links in radiation environments, some mitigation techniques can be used. In this article, we present a bidirectional link running at 6.25 Gbps implemented in Xilinx Kintex-7 FPGAs. Transferred data are protected against radiation effects by means of a Reed–Solomon (RS) code and symbol interleaving. Logic features triple modular redundancy in critical blocks. The design includes a custom scrubber based on majority voting of configuration frames. Our custom protocol can vary the protection level of the RS code to cope with different rates of radiation-induced transmission errors, trading off the available bandwidth for reliability. We present the test results carried out using fault injection and a 62-MeV proton beam at the Istituto Nazionale di Fisica Nucleare (INFN) Laboratori Nazionali del Sud (Catania, Italy). We show the performance of the link in terms of mean time between failures and mean time between losses of lock. [ABSTRACT FROM AUTHOR]

This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mitigation techniques based on hardware redundancy and scrubbing. Results demonstrated an improvement of 3× in the cross section when scrubbing and coarse grain triple modular redundancy are used. The Rocket processor presented analogous sensitivity to radiation effects as the state-of-the-art soft processors. Due to the complexity of the system-on-chip, not only the Rocket core but also its peripherals should be protected with proper solutions. Such solutions should address the specific vulnerabilities of each component to improve the overall system reliability while maintaining the trade-off with performance. [ABSTRACT FROM AUTHOR]

The angular sensitivity of neutron-induced single-event upsets (SEUs) is studied in 12-nm FinFET SRAMs. Irradiation experiments are performed using a terrestrial environment-compatible source with varying incidence angles. The analyses of the occurrence rates of SEUs and multiple-bit upsets (MBUs) demonstrate that although the SEU rate decreases at grazing incidence, the MBU rate increases when the incidence direction is parallel to the word lines (WLs) of the SRAM array, as similarly observed in our previous experiments for 20-nm planar SRAMs. It is found that the angular response of multiple-cell upsets (MCUs) is different between the 12-nm FinFET and 20-nm planar SRAMs. The comparative analysis of the voltage dependence of the MCU ratio reveals that this difference is due to the different contribution of parasitic bipolar effects (PBEs), which are more significant in the 20-nm planar SRAMs. It is also indicated that in the 12-nm FinFET SRAMs, the contribution of PBEs is relatively large when the incidence angle is parallel to the WLs. Through the characterization of the MCU events, the validity of this picture is confirmed based on the voltage dependence of the pattern-wise MCU ratio with the consideration of the impact of PBEs on fail bit patterns. [ABSTRACT FROM AUTHOR]

A neutron irradiation test of static random access memories (SRAMs) was performed using a spallation neutron source at Materials and Life Science Experimental Facility (MLF) in the Japan Proton Accelerator Research Complex (J-PARC). The probability of neutron-induced single-event upsets (SEUs) was measured for 65-nm bulk and silicon on thin buried oxide (SOTB) SRAMs under neutron irradiation at the BL10 experimental facility. The measured SEU data were compared with the previous data of the same SRAMs which were measured at other irradiation facilities having different neutron spectra. The differences in the operating voltage dependence of the measured SEU probabilities are discussed with particular attention to the impact of irradiation side on SEUs. The particle and heavy ion transport code system (PHITS) simulation based on the simple sensitive volume model qualitatively reproduced the operating voltage dependence seen in the measured ratio of SEUs for the Bulk SRAM between the resin side and board side irradiations under different neutron fields. [ABSTRACT FROM AUTHOR]

A sensitivity characterization of a Xilinx Artix-7 field programmable gate array (FPGA) against 14.2-MeV neutrons is presented. The content of the internal static random access memories (SRAMs) and flip-flops was downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, block RAM (BRAM), or flip-flops. Single bit upsets (SBUs) and multiple cell upsets (MCUs) with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUlti-Scales Single Event Phenomena Predictive Platform (MUSCA SEP3) was used to make assessment of actual environments and an improvement of single event upset (SEU) injection test is proposed. [ABSTRACT FROM AUTHOR]

Muon-induced single event upset (SEU) is predicted to increase with technology scaling. Although previous works investigated the dependencies of muon-induced SEU cross sections on energy, voltage, and technology, the angle of incidence of terrestrial muons is not always perpendicular to the chip surface. Consequently, the impact of the angle of incidence of muons on SEUs should be evaluated. This study conducts negative muon irradiation tests on bulk and fully depleted silicon on insulator static random access memories at two angles of incidence: 0° (vertical) and 45° (tilted). The tilted incidence drifts the muon energy peak to a higher energy as expected. However, the SEU characteristics in the bulk device between the vertical and tilted incidences, including the voltage dependences of the SEU cross sections and multiple cells upset patterns, are similar despite the unexpected impact on the SEU cross section at an operating voltage of 0.4 V. [ABSTRACT FROM AUTHOR]

Negative and positive muon irradiation tests of static random access memories (SRAMs) were performed at Muon Science Innovation Channel (MuSIC) of Research Center for Nuclear Physics (RCNP), Osaka University. The muon-induced single event upset (SEU) cross sections for 65-nm bulk SRAMs were measured. The SRAM device was irradiated by the muon beams with average momenta ranging from 37.8 to 41.0 MeV/c at the beam exit. The incident muon fluence was measured using a one-by-one muon detection system with a plastic scintillator by taking advantage of the direct current (dc) muon beam and reliable absolute values of SEU cross sections were obtained. In addition to the measurement of the SEU cross sections, we measured muonic X-rays from the irradiated device to investigate the relation between the measured SEU cross section and the emission rate of muonic X-rays associated with the stopping position of the muons as a function of incident muon momentum. The result suggested that negative muons have a significant effect on SEUs by the emission of secondary light ions via negative muon capture reaction when negative muons stop near sensitive volumes (SVs) in SRAMs. [ABSTRACT FROM AUTHOR]

We take an initial look at hard single-event effects (SEEs) in power electronics and static random access memories (SRAMs) during space weather-induced extreme ground-level enhancement (GLE) events. We show that there is a significant risk of failure of silicon power metal–oxide–semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) at ground level during a 10 × February ’56 GLE. If the devices are not derated, then we find that 21% of power MOSFETs and 14% of IGBTs are, in the worst case, predicted to fail. The probability of failure increases to 68% and 52% during a once-in-a-10 000-year GLE for power MOSFETs and IGBTs, respectively. Silicon carbide devices show a lower failure rate by more than an order of magnitude, where only 2.8% are predicted to fail during a once-in-a-10 000-year GLE. It is clear that these events could disrupt critical infrastructure if mitigating precautions are not implemented. [ABSTRACT FROM AUTHOR]

We present the experimental results on the impact of transistor width modulation and power supply voltage variation on the α-soft error rate (SER) in a 65-nm CMOS 6T static random access memory (SRAM) obtained from an accelerated test experiment using an Am-241~α-source. Five 6T cells with various combinations of transistor widths were tested and the results show that nMOS and pMOS widths play a different role on SER. We also found that the transistor width modulation effectiveness is highly dependent on the power supply voltage. In particular, the results show that at around nominal voltages, widening all pMOS while keeping all nMOS minimum sized, is the best way to improve SER. However, at lower voltages the results become completely different, and the best option for an overall SER improvement is to keep all transistors minimum sized. [ABSTRACT FROM AUTHOR]

Triple modular redundancy (TMR) with repair is a commonly employed mitigation strategy used on SRAM field-programmable gate arrays (FPGAs) to reduce the effects of ionizing radiation and improve a circuit’s sensitive cross section. This article examines TMR circuits, where the I/O ports of the circuit have not been triplicated, but the internal circuitry has. Such circuits introduce single-point failures (SPFs) into the circuit that limit the neutron cross-sectional improvement offered by TMR to only 3× for the b13 benchmark circuit used in this article. This article proposes two different mitigation techniques to address SPFs, which alter the placement and routing of the circuit. These mitigation techniques reduce the neutron cross section by 26× over the unmitigated circuit while minimally affecting the circuit’s maximum clock frequency and resource utilization. [ABSTRACT FROM AUTHOR]

Single-event upset (SEU) hardness varies across dies, wafers, and lots—even just after fabrication and further across time. Mechanisms of postfabrication variations include total ionizing dose (TID) effects, which are caused by long-term radiation exposure. This synergistic effect of TID on SEU hardness is a particular concern in integrated circuits used in space and nuclear radiation environments. This article shows that an electrical parameter called the data-retention voltage is useful in dealing with such TID effects on the SEU hardness of static random access memories (SRAMs), which are known to be particularly radiation-sensitive. Experiments showed that TID-induced variations in SRAM SEU hardness, i.e., variations in SEU cross sections, were predicted by measuring the data-retention voltage. In addition, these variations were canceled out by adjusting the power supply voltage according to its interesting relationship to the data-retention voltage. Results suggest that it might be possible in flight to predict and cancel out SEU hardness variations caused by TID and other synergistic effects. [ABSTRACT FROM AUTHOR]

Radiation-induced multiple-cell upsets (MCUs) are a concern because they can overcome the protection of error correction code and triplicated designs. Extracting MCU data from radiation tests is helpful to perform more accurate fault injection tests, where MCUs could be simulated with the injection of bits based on the MCUs shapes, sizes, and frequencies. This article presents a statistical method to extract MCU shapes and frequencies from components with no information regarding their physical layout. The proposed method can be used to extract MCU information from BRAM and CRAM alike. The results show the MCU data for three families of Xilinx field-programmable gate arrays (FPGAs). [ABSTRACT FROM AUTHOR]

Single-event upsets (SEUs) were measured in thermal neutron-irradiated microcontrollers with 65- and 130-nm-node static random-access memories (SRAMs). The suspected upset mechanism is charge deposition from the energetic byproducts of 10B thermal neutron capture. Although elemental analysis confirmed that both microcontrollers contain 10B, only the 65-nm node microcontroller exhibited a strong response to thermal neutrons. Monte Carlo simulations were performed to investigate the effects of 11B enrichment on thermal neutron-induced SEUs in a 65-nm SRAM node when boron is present in the p-type well, p-type source and drain, or tungsten plug. Simulations indicate that the byproducts of 10B(n, α) 7Li reactions are capable of generating sufficient charge to upset a 65-nm SRAM. The highest amount of charge deposition from 10B(n, α) 7Li reaction byproducts occurs when natural boron is used to dope the p-type source and drain regions. Simulations also show that the SEU cross section is nonnegligible when 11B-enriched boron is used for doping. [ABSTRACT FROM AUTHOR]