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This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency single-phase T-type boundary conduction mode (BCM) microinverter. The conventional full-bridge BCM microinverter has achieved zero voltage switching (ZVS) and thereby improved the efficiency, but it suffers from high switching losses under light load conditions. The proposed T-type BCM microinverter reserves ZVS and uses a multilevel technique to further decrease the switching losses. The BCM operation with multilevel technique will have too low switching frequency when the grid voltage approaches half of the dc link voltage. To solve this problem, this paper adopts a third operation mode for the T-type switching leg to maintain the switching frequency above a minimum value. The corresponding mode transitions are also detailed to ensure a smooth operation. Because of the turn-offdelay of the freewheeling transistor, the actual lower current boundary deviates from the programmed one, which will distort output current. To address this issue, this paper also proposes a boundary compensation method. A prototype has been built for performance verification, which can test both full-bridge and T-type topology. Compared with the full-bridge BCM microinverter, the proposed T-type BCM microinverter has a higher efficiency over the whole load range. [ABSTRACT FROM AUTHOR]

This paper presents the digital implementation of a boundary controller with unipolar switching characteristic for single-phase voltage source full-bridge inverters. This paper expands the application of a second-order switching surface-based control method to unipolar switching of single-phase voltage source inverters (VSIs) using a finite-state machine. The finite-state machine has been formulated considering four different states of the inverter; positive,zero1, negative, andzero2. The second-order boundary control governs the current state of the system and provides proper switching action to keep the system within the desired reference. The control law is implemented digitally in F28m35x digital control card. A full-bridge inverter topology is used to achieve the three-level voltage switching. Various simulations and experiments were performed in a 550 VA, 120 V, 60 Hz VSI with a digitally implemented controller to verify the theoretical predictions. A high-quality voltage output was obtained for various loading conditions. The transient performance of the controller was investigated using a reference and load changes. A comparison of the implementation was made with the existing classical controllers to verify the fast-dynamic response of the system. [ABSTRACT FROM AUTHOR]

This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common-mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper, first, establishes the equivalent common-mode circuit of the proposed inverter. The impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a new high-efficiency photovoltaic (PV) converter for grid connection through a high-leg delta transformer. The converter is composed of a symmetrically connected boost converter and three half-bridge inverters. One of the three half-bridge inverters is connected to the boost converter, and the others are directly connected to the PV terminals. As a result, this circuit configuration enables to reduce the power losses in both boost converter and inverters. This paper also proposes a new cooperative control method between the symmetrically connected boost converter and inverter. The control method can reduce the average switching frequency to 75% of that in a conventional one, resulting in a great reduction in the switching power loss. Experimental results confirm that the proposed circuit configuration makes it possible to improve its European efficiency from 91.6% to 94.5%. Moreover, system performance is evaluated on the assumption of maximum power point tracking operation. [ABSTRACT FROM AUTHOR]

This paper comprehensively analyzes the stability of a grid-interfacing inverter with the LCL -filter in the discrete domain, where the LCL-filter, along with the controller, is modeled in a polar coordinate. System open-loop and closed-loop poles are analytically studied and expressed in the z -domain. Through the poles movement and distribution analysis, the relationship between system stability and the ratio of resonance frequency over sampling frequency is mathematically revealed and calculated as well as the system control gain limit. Moreover, this paper demonstrates that a grid-voltage feedforward regulator would significantly alter the inverter stability in a weak power system. By means of Jury stability criterion, the stability status under different filter resonance frequency is given. The selection of resonance frequency and filter parameters makes a considerable difference on system behavior. Finally, to improve the robustness against grid inductance variation, a conservative design recommendation of filter parameters and control gain is given. Through the tests on a laboratory-scale prototype, the theoretical analysis is validated by experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, a neutral point (NP) voltage balancing scheme suitable for three phase 5-level active NP clamped and T-type NP clamped (TNPC) inverters is discussed. Carrier-based pulsewidth modulation is used for the balancing of dc-link capacitors and floating capacitors (FC) in the inverter. The FC voltages are regulated with the help of redundant switching states of pole voltage levels and the dc-link capacitor voltages are controlled using zero-sequence voltage injection. Though the balancing approaches are different for dc-link capacitors and FCs, they are not decoupled from each other. This is due to the effect of certain redundant switching states used for FC balancing causing NP voltage variation. To address this issue, the redundant state time ratio is estimated online every sample and based on this dynamic time ratio, an optimal relationship between neutral current and zero-sequence voltage is established. It is found that the use of dynamic time ratio helps in achieving better transient performance than that of generally adopted fixed time ratio. Simulation and experimental results prove that the proposed balancing scheme works well under all operating conditions and exhibits fast and stable transient performance. [ABSTRACT FROM AUTHOR]

In order to provide high and extendable power levels for inductive power transfer (IPT) system, a parallel multi-inverter system based on modular inverter is presented. Various power requirements can be implemented by an adjustment of the number of paralleled inverters, which provides a high modularity. A master−slave scheme is employed for the switching-driver signals of parallel inverters, where one acts as a leader while others act as followers. Despite the master−slave scheme, the proposed circuit topology has natural robustness because of the equality in terms of the hardware configuration of each modular inverter. For proper parameters, the output phase (current lagging corresponding voltage) of an inverter is lower than the average of output phase of all inverters, when its output voltage lags behind others, and vice versa. Based on this approach, PI controllers are designed to implement phase synchronization for output voltages of all inverters. An IPT prototype supplied by the proposed parallel multi-inverter with three inverters was designed, built, and tested. Experiments show that the proposed parallel multi-inverter system has not only good circulating current suppression capacity but also excellent performance of phase synchronization. The maximum dc−dc efficiency was 94% at a 35.1 kW receiving power. This paper is accompanied by a Matlab/Simulink file demonstrating phase synchronization control. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

This paper analyzes the possibility of controlling the output voltage of a standalone single-phase inverter by directly controlling the output filter capacitor current without using a dedicated output voltage sensor. The plant modeling and controller design are presented. The proposed method depends on having the value of the output filter capacitance. A method to estimate the output filter capacitance is also presented. Rigorous analysis is done to show that the proposed sensorless scheme is largely insensitive to parameter variations and ensure that the output voltage is within specified regulations at utility level. It is also demonstrated in this paper that compared to the conventional voltage control scheme the proposed control scheme ensures an improved total harmonic distortion of the output voltage waveform. Experimental results presented validate the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-space vector control scheme for the open-end winding permanent magnet synchronous motor (OEW-PMSM) drive fed by the dual inverter with a single dc supply. Potential zero-sequence current in the open-end winding drive system has to be considered since it causes circulating current in the winding and leads to high current stress of power semiconductor devices and high losses. Zero-sequence current in open-end winding ac motor drives is usually caused by the zero-sequence voltage, and therefore switching combinations which do not produce zero-sequence voltage are used to synthesize the reference voltage in existing methods. But even so, the zero-sequence voltage can also be produced by the dead time of the inverter. In order to suppress zero-sequence current in the OEW-PMSM drive, a dual-space vector control scheme is proposed and a novel dual-inverter space vector pulse width modulation (PWM) with the zero-sequence voltage reference is employed to regulate system zero-sequence voltage in this paper. Compared with existing dual inverter PWM strategies, the novel algorithm build a regulation mechanism for the zero-sequence voltage. The proposed method is compared with the conventional vector control by simulations and experiments, and the results shown that the proposed scheme can suppress zero-sequence current effectively. [ABSTRACT FROM AUTHOR]

Based on the Z-source inverter, this paper proposes a novel commutation torque ripple reduction strategy for brushless DC motor (BLDCM). The proposed strategy employs the same modulation mode in both the normal conduction period and the commutation period, and the commutation torque ripple is reduced by regulating the shoot-through vector and active vector duty cycles. The proposed detection method acquires the end point of commutation by comparing the clamped terminal voltages with reference zero level, and the signal-noise-ratio of the detection is improved by avoiding the attenuation of the terminal voltages. Furthermore, a certain pulse width of the shoot-through vector can not only reduce the commutation torque ripple but also provide a new opportunity to detect the end point of commutation. Moreover, Z-source inverter provides the buck–boost ability for BLDCM drive system, then the dc voltage utilization can be improved, and the safety of the drive system can also be improved. In addition, this paper analyzes the terminal voltages during each vector. The experimental results verify the correctness of the theories and the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

SiC mosfets allow a higher frequency, lighter weight inverter over their Si counterparts for electric vehicle (EV) applications. However, using SiC-based EV traction inverters is likely to increase the shaft voltage in an ac motor drive system, which significantly affects the reliability of the system. This paper investigates the impact of high-speed switching of SiC devices and high switching frequency of SiC-based inverter on the common-mode voltage (CMV) and the shaft voltage. It is theoretically illustrated and experimentally demonstrated that the high switching frequency increases the amplitude of the shaft voltage, while the fast switching speed has limited influence on both CMV and the shaft voltage. Afterward, active zero state pulsewidth modulation (AZSPWM) and common-mode chokes are employed to mitigate the shaft voltage. The experimental results show that either the AZSPWM modulation scheme or common-mode chokes have the capability to minimize the shaft voltage. Better performance can be achieved by utilizing both techniques simultaneously. It is also observed that the high switching frequency enabled by the fast-speed SiC device is able to be helpful to the use of reduced shaft voltage technologies. [ABSTRACT FROM AUTHOR]

An LLC resonant converter would have light-load voltage regulation problems due to the effect of parasitic capacitances in a high-frequency range. In this paper, an energy feedback control method is proposed to improve the light-load regulation capacity by using synchronous rectifiers (SRs). The SR bridges are controlled ahead of the primary inverter bridges to deliver the energy from load to source, reducing the output voltage independent of the load. Then the desired voltage can be achieved even in no-load conditions by regulating the operation time of the energy feedback mode. The gain, voltage ripple, and efficiency performances of the proposed control method are discussed based on the precise analysis and an accurate model of the converter. Moreover, the light-load operations of the LLC resonant converter are analyzed deriving the critical load condition. Finally, the proposed control method is verified by the experiments of a 12 V/8 A LLC resonant converter prototype. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

In a low-voltage parallel inverter system, the active power, unbalanced power, and harmonic power generally cannot be properly shared among inverters with droop control due to the mismatch of output impedance. To address this issue, this paper proposes a two-stage adaptive virtual resistor (AVR) control scheme. In the first stage, a proportional-integral controller is applied to regulate the active power with the use of a synchronous maximum power bus (SMPB), and the reactive power is adjusted by means of aQ–ωdroop controller. In the second stage, all inverters switch to aP–Edroop control mode by introducing the AVRs at fundamental positive-sequence, negative-sequence, and harmonic frequencies. Not only can this method eliminate the active power, unbalanced power, and harmonic power-sharing errors, it can also reduce the voltage deviation caused by the droop control. Moreover, the synchronization between inverters can be guaranteed as long as the SMPB is present, without using voltage sensors at the point of common coupling. Simulation and experimental results are provided to verify the feasibility of this method. [ABSTRACT FROM AUTHOR]

For the purpose of increasing the reliability in a hostile environment, techniques of fault diagnosis have been reported for a three-phase voltage-source inverter (VSI). Based on the average current Park's vector method, this paper proposes a fuzzy-based fault diagnosis method for the VSI in the three-phase permanent-magnet synchronous motor drive. By utilizing the phase current information, the fault symptom variables are calculated by using the average current Park's vector method. The fuzzy logic approach is applied to process the fault symptom variables and obtain the faulty information of power switches. Compared with other fuzzy logic methods, the fuzzy logic design, fuzzy inputs, and fuzzy rules are different. The proposed fault diagnosis method can detect and locate not only the single or multiple open-circuit faults, but also the intermittent faults in power switches, which can improve the reliability of the motor drive system. The effectiveness of the proposed method is validated by both simulation and experiments. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

Local hardware clocks in physically distributed computation devices hardly ever agree because clocks drift apart and the drift can be different for each device. This paper analyzes the effect that local clock drifts have in the parallel operation of voltage source inverters (VSIs) in islanded microgrids (MG). The state-of-the-art control policies for frequency regulation and active power sharing in VSIs-based MGs are reviewed and selected, and prototype policies are then reformulated in terms of clock drifts. Next, steady-state properties for these policies are analyzed. For each of the policies, analytical expressions are developed to provide exact quantification of the impact that drifts have on frequency and active power equilibrium points. In addition, a closed-loop model that accommodates all the policies is derived, and the stability of the equilibrium points is characterized in terms of the clock drifts. Finally, the implementation of the analyzed policies in a laboratory MG provides experimental results that confirm the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new pulse width modulation (PWM) scheme and commutation method is presented for one phase loss operation of three-phase isolated buck matrix-type rectifier. With the proposed PWM scheme, the maximum allowable voltage gain for one phase loss operation can be achieved, which permits the continuous operation of the converter to deliver two-third of the rated power and regulate the output voltage with maximum output voltage drop less than 5% of nominal output voltage. In addition, with the proposed commutation method, a safe transition from one phase loss operation to normal operation and vice versa can occur with minimum commutation steps (two-step) under zero-voltage switching condition. The performance of the proposed PWM scheme and commutation schemes with one phase loss operation is evaluated and verified by simulations and experiments on a 5 kW prototype. [ABSTRACT FROM AUTHOR]

To develop thermoelectric power conditioning systems that are highly efficient over a wide range of input voltages and support medium-rated power, this paper introduces a hybrid resonant dc/dc converter using an active voltage-doubler rectifier. When the input voltage is higher than the preset nominal input voltage, the converter operates in the phase-shift full-bridge series-resonant converter mode, in which it achieves high efficiency by softly switching the primary-side switches and reducing the conduction loss. When the input voltage is lower than the nominal one, it operates in the resonant boost mode that boosts the resonant inductor current. By using the active voltage-doubler rectifier on the secondary side of the converter, we can build the converter with less number of active components. As a result, the proposed converter achieves, at low cost, high boost-ratio and high efficiency over a wide range of input voltages. A detailed analysis of the converter operation is presented along with the design procedure. At 35–55 V, a 600-W/360-V prototype of the proposed converter has been built and tested to demonstrate its effectiveness. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive super-twisting algorithm based sliding-mode observer (STA-SMO) for surface-mounted permanent magnet synchronous machine (PMSM) sensorless control, in which voltage source inverter (VSI) nonlinearity is taken into consideration. An adaptive algorithm for online tuning the sliding-mode coefficients of STA-SMO is proposed based on the existing stable conditions. Thus, position estimation error can be reduced by the proposed adaptive algorithm in wide-speed range. Furthermore, voltage distortion due to VSI nonlinearity is online compensated to improve the accuracy of PMSM model. Because mismatch between reference and actual voltage due to VSI nonlinearity may bring large rotor position and speed estimation error, especially in low-speed range where distorted voltages may become dominant compared to actual voltages. Thus, a STA-SMO with adaptive sliding-mode coefficients and accurate voltage value could be obtained. Finally, the effectiveness of the proposed adaptive STA-SMO with online VSI nonlinearity compensation is verified on a surface-mounted PMSM by experiments. [ABSTRACT FROM AUTHOR]

This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources, and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

For the purpose of reducing cost and volume, as well as to increase reliability in hostile environments, techniques of reconstructing three-phase current through a single current sensor have been reported for a three-phase alternating current motor vector control system. Based on the phase current reconstruction method, this paper proposes a novel open-circuit fault diagnosis method for the low-power voltage source inverter in the three-phase permanent-magnet synchronous motor drive. Other than sampling the single dc-link current sensor, the zero voltage vector sampling method (ZVVSM) is adopted to implement the fault diagnosis. By placing the single current sensor at a special position, ZVVSM is able to sample current during the two zero voltage vectors and reconstruct the three-phase currents. The reconstructed three-phase currents are used to generate the diagnostic variables that can detect and locate the faulty power switches. The PWM modulation strategy remains unchanged in this method and the reconstructed phase currents are with less waveform distortion and less harmonic contents, which are suitable for the fault diagnosis. The effectiveness of the proposed method is verified by experiments. [ABSTRACT FROM AUTHOR]

A quasi-Z-source inverter (qZSI) could achieve buck/boost conversion as well as dc to ac inversion in a single-stage topology, which reduces the structure cost when compared to a traditional two-stage inverter. Specifically, the buck/boost conversion was accomplished via shoot-through state which took place across all phase legs of the inverter. In this paper, instead of using traditional dual-loop-based proportional integral (PI)-P controller, a type 2 based closed-loop voltage controller with novel dc-link voltage reference algorithm was proposed to fulfill the dc-link voltage tracking control of a single-phase qZSI regardless of any loading conditions, without the need of inner inductor current loop. A dc–ac boost inverter with similar circuit parameters as a qZSI was used to verify the flexibility of the proposed controller. The dynamic and transient performances of the proposed controller were investigated to evaluate its superiority against the aforementioned conventional controller. The integrated proposed controller and qZSI topology was then employed in static synchronous compensator application to perform reactive power compensation at the point of common coupling. The effectiveness of the proposed approach was verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

In this paper, a new reference current generation method is proposed for effective harmonics mitigation and reactive power compensation of three-level neutral-point diode clamped inverter-based shunt active power filter (SAPF) under nonideal grid voltage conditions. The proposed method is named as dual fundamental component extraction algorithm. In operation, the proposed algorithm extracts at the same time, the desired fundamental current and voltage components for generating reference current and synchronization phases, respectively. As a result, the proposed algorithm is able to generate reference current that ensures in phase operation of SAPF with the operating power system, without depending on any phase-locked loop elements. Besides, the proposed algorithm employs self-tuning filter (STF) for accurate computation of the fundamental components. Design concept and effectiveness of the proposed algorithm are thoroughly studied and evaluated in MATLAB–Simulink. Additionally, a laboratory prototype utilizing TMS320F28335 digital signal processor is built to validate its feasibility. Encouraging findings obtained from both simulation and experimental works demonstrate effectiveness of the proposed algorithm under both ideal and nonideal grid voltage conditions. [ABSTRACT FROM AUTHOR]

In this paper, a control strategy for the parallel operation of three-phase inverters forming an online uninterruptible power system (UPS) is presented. The UPS system consists of a cluster of paralleled inverters with LC filters directly connected to an ac critical bus and an ac/dc forming a dc bus. The proposed control scheme comprises two layers: 1) a local layer that contains a “reactive power-to-phase droop” in order to synchronize the phase angle of each inverter and a virtual resistance loop that guarantees equal power sharing among inverters; and 2) a central controller that guarantees synchronization with an external real/fictitious utility, and critical bus voltage amplitude restoration. Improved transient and steady-state frequency, active, reactive, and harmonic power sharing, and global phase-locked loop resynchronization capability are achieved. Detailed system topology and control architecture are presented in this paper. Furthermore, a mathematical model was derived in order to analyze critical parameters effects on system stability. The proposed control approach has been validated by means of experimental results obtained for several case-study scenarios. [ABSTRACT FROM AUTHOR]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

This paper provides a theoretical discussion and comparison in energy balancing between a modular multilevel cascade inverter based on single-star bridge cells (SSBC) and that on single-delta bridge cells (SDBC). Attention is paid to applications involving asymmetric active-power generation in utility-scale grid-tied photovoltaic systems. Both qualitative and quantitative evaluation metrics to assess the energy-balancing capability are introduced and applied to both SSBC and SDBC inverters. As for the SSBC inverter, six zero-sequence voltage waveforms with different harmonic content enabling enhanced energy-balancing capability are analyzed and compared regarding their effectiveness. This paper also emphasizes on the SDBC as an alternative to the SSBC and highlights its superior operating characteristics under asymmetric active-power generation. [ABSTRACT FROM PUBLISHER]

Direct ac/ac topologies for ac-to-ac power conversion benefit from the absence of dc-link capacitors, and therefore, are highly reliable and have low cost as compared to the traditional voltage-source inverter (VSI)-based topologies. This paper deals with one of the more important tradeoffs considered in designing highly efficient converters: Losses. It is shown in this paper that the direct ac/ac converters have an inherently higher efficiency than their VSI-based back-to-back counterparts due to a dramatic reduction in switching losses (nearly 60%). Further, this paper compares the performance of three different device types (SiC MOSFETs, hybrid Si IGBT/SiC diode, and Si IGBTs) using wide-range device characterization that help to create detailed loss models. It is conjectured that traditional datasheets lack the level of detail needed for computing losses in direct ac/ac converters, and the availability of a multivalue voltage, current, and temperature-based loss profile is advocated. Using the obtained loss models, a comparison is drawn between the considered devices through simulations when operated in a 13-kV/1-MW direct ac/ac power flow controller, the controllable network transformer (CNT). The same loss-models are also used to compute losses in an experimental prototype of a 720-V, 10-kVA CNT and the results are compared with direct efficiency measurements. A similar computation is carried out for another experimental prototype at a 6.7-kV, 400-kVA, three-level, paralleled CNT. These experimental tests are used to confirm the validity of the analytical results presented in this paper. [ABSTRACT FROM AUTHOR]

A multilevel topology with medium-frequency ac link for medium-voltage grid integration of utility photovoltaic (PV) plants is discussed in this paper. A megawatt-scale PV plant is divided into many zones, each comprising of two series-connected arrays. Each zone employs a medium-frequency transformer with three secondaries, which interface with the three phases of the medium voltage grid. An insulated-gate bipolar transistor full-bridge inverter feeds the MF transformer. The voltages at the transformer secondaries are then converted to three-phase line frequency ac by three full-bridge ac-ac converters. Second line frequency harmonic power does not appear in the dc bus, thereby reducing the dc capacitor size. Cascading several such cells, a high-quality multilevel medium-voltage output is generated. A new control method is proposed for the cascaded multilevel converter during partial shading while minimizing the switch ratings. The proposed topology eliminates the need for line frequency transformer isolation and reduces the dc bus capacitor size, while improving the power factor and energy yield. This paper presents the analysis, design example, and operation of a 10-MW utility PV system with experimental results on a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents a simple controller integrating a new reactive current reference algorithm for enhancing the transient performance of static synchronous compensator (STATCOM). A multilevel cascaded inverter with separated dc capacitors which is driven by carrier-based pulse width modulation is used to implement the STATCOM. The voltage across each dc-link capacitor is regulated by the rotated switching swapping scheme. In this paper, the STATCOM is controlled to provide both reactive power (VAR) compensation and grid power factor correction at the point of common coupling with a dynamically varying reactive load system. The proposed algorithm enhances the transient performance of the closed-loop system with only proportional controller and minimizes the STATCOM reactive current ripples. STATCOM based on a five-level cascaded inverter is presented in this paper and the performance of the proposed controller is investigated through various simulation studies using MATLAB/Simulink software for both steady state and transient conditions. A laboratory prototype is also developed to verify the simulation results where a good match between simulation and experimental results is achieved. [ABSTRACT FROM AUTHOR]

Based on the Z-source inverter, this paper proposed a novel approach to zero-crossing point (ZCP) detections during the shoot-through vectors for sensorless brushless dc motor (BLDCM). The proposed approach separates the ZCP detections from speed adjustment, and makes the shoot-through vector not influence the motor speed-adjustment directly, while the zero-vectors and active-vectors are used exclusively to adjust the speed of BLDCM. With the proposed approach, the sensorless BLDCM can operate in a wide speed range without switching the detection points and the reference levels, and it is unnecessary to change the reference levels according to the PWM technique. The terminal voltages limited by diode can be directly compared with the reference zero level during the shoot-through vectors, so as to reduce the detection error caused by attenuation. Moreover, Z-source inverter not only provides boost voltage for sensorless BLDCM drive system, but also improves the utilization rate of dc source voltage and the safety of the drive system. In addition, this paper analyzed the terminal voltages of the floating phase during each vector. The experimental results verified the correctness of above theories and proved the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

Two-stage single-phase inverters have been widely used as they can achieve voltage matching and galvanic isolation between the input and output. Due to the pulsating output power of the downstream inverter, an ac current at twice the output frequency, which is called second harmonic current (SHC), arises in the input side of the downstream inverter. This SHC will penetrate to the front-end dc-dc converter, leading to reduced conversion efficiency. This paper first analyzes the propagation mechanism of the SHC and load transient response of two-stage single-phase inverters from the viewpoint of output impedance. Then, based on the current mode control and load current feed forward, two control methods to achieve low SHC in the front-end dc-dc converter and fast dynamic performance during load transient are proposed in this paper. Finally, a 2-kW two-stage single-phase inverter prototype has been constructed and tested, and the experimental results are provided to verify the effectiveness of the proposed control methods. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

Leakage current minimization is one of the most important considerations in transformerless photovoltaic (PV) inverters. In the past, various transformerless PV inverter topologies have been introduced, with leakage current minimized by the means of galvanic isolation and common-mode voltage (CMV) clamping. The galvanic isolation can be achieved via dc-decoupling or ac-decoupling, for isolation on the dc- or ac-side of the inverter, respectively. It has been shown that the latter provides lower losses due to the reduced switch count in conduction path. Nevertheless, leakage current cannot be simply eliminated by galvanic isolation and modulation techniques, due to the presence of switches' junction capacitances and resonant circuit effects. Hence, CMV clamping is used in some topologies to completely eliminate the leakage current. In this paper, several recently proposed transformerless PV inverters with different galvanic isolation methods and CMV clamping technique are analyzed and compared. A simple modified H-bridge zero-voltage state rectifier is also proposed, to combine the benefits of the low-loss ac-decoupling method and the complete leakage current elimination of the CMV clamping method. The performances of different topologies, in terms of CMV, leakage current, total harmonic distortion, losses and efficiencies are compared. The analyses are done theoretically and via simulation studies, and further validated with experimental results. This paper is helpful for the researchers to choose the appropriate topology for transformerless PV applications and to provide the design principles in terms of common-mode behavior and efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

Generally, single-stage buck–boost inverters consist of distinct circuits operating individually in buck/boost or positive/negative modes, the latter definitely leading to crossover distortion in the output current. This paper proposes a switching strategy that changes the bimodal operation of a single-stage buck–boost topology to a single-mode inverter. This is due to the consequent voltage gain that ensures that the output voltage polarity, apart from its magnitude, is an exclusive function of the duty ratio. Operational principle and salient hardware design are explained with the help of equivalent circuits. Details about the dynamic model are presented, based on which controller design is carried out for both stand-alone and grid-connected operation. Experimental results obtained from a 300-W, 110-V laboratory prototype are presented to validate the performance of the proposed switching strategy. [ABSTRACT FROM PUBLISHER]

In classical inverter control, load current (disturbance) decoupling control is often used to improve the control performance. Yet, in a recent state-space control structure for multiresonant controllers, the load current decoupling technique is less studied. Moreover, in the classical control, the load current decoupling only has one control degree of freedom. Therefore, in this paper, a load current decoupling control combed linear quadratic (LQ) regulation is investigated, the proposed control structure that manipulates α and β axes as a unified system is adopted to increase the control degree of freedom. The LQ control synthesizes the state feedback control law including gains of the resonant controllers. Two general criteria, namely H\infty norm and zero dynamic, are proposed as the design guideline for the load current decoupling control. The effectiveness and robustness of the proposed approach are validated through MATLAB/Simulink simulations and experiments with a 5-kVA testbed. The results prove that some favorable performances, for example, the fast recovering time, the small voltage drop, and the low total harmonic distortion, are achieved by the proposed approach compared to the classical dual-loop proportional-resonant (PR) control with load current decoupling and the optimal H\infty control. [ABSTRACT FROM AUTHOR]

This paper analyzes the use of the voltage distortions in pulse width modulation voltage-source inverters caused by the inverter switching for islanding detection purposes. The nonideal characteristics of the inverters, mainly due to the dead time needed to have safe commutations, produce fundamental frequency-dependent harmonics (−5th, 7th, …) in the output voltage. These harmonic order are, in principle, an unwanted effect, as they reduce the power quality. However, they can potentially be used for islanding detection purposes. The physical principles of the method would be the same as for high-frequency signal injection methods that have already been proposed, but without the need of injecting a high-frequency signal, behaving, therefore, as a passive islanding detection technique. [ABSTRACT FROM AUTHOR]

This paper presents a steady-state model of MMC for the second-order phase voltage ripple prediction under unbalanced conditions, taking the impact of negative-sequence current control into account. From the steady-state model, a circular relationship is found among current and voltage quantities, which can be used to evaluate the magnitudes and initial phase angles of different circulating current components. Moreover, in order to calculate the circulating current in a point-to-point MMC-based HVdc system under unbalanced grid conditions, the derivation of equivalent dc impedance of an MMC is discussed as well. According to the dc impedance model, an MMC inverter can be represented as a series connected R–L–C branch, with its equivalent resistance and capacitance directly related to the circulating current control parameters. Experimental results from a scaled-down three-phase MMC system under an emulated single-line-to-ground fault are provided to support the theoretical analysis and derived model. This new models provides an insight into the impact of different control schemes on the fault characteristics and improves the understanding of the operation of MMC under unbalanced conditions. [ABSTRACT FROM PUBLISHER]