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This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

This paper investigates the dependence of the supercapacitor Peukert constant on its terminal voltage, aging condition, and operating temperature. Recent studies show that the charge delivered by a supercapacitor during a constant current discharge process increases when the discharge current decreases if the discharge current is above a certain threshold, i.e., Peukert's law applies. By conducting extensive experiments using three supercapacitor samples with different rated capacitances from different manufacturers, this paper reveals that the Peukert constant increases when the initial voltage of the constant current discharge process is lower, the supercapacitor is more heavily aged, or the operating temperature is lower. The physical mechanisms accounting for the Peukert constant dependence are illustrated by analyzing an $RC$ ladder circuit model. When the supercapacitor terminal voltage is higher, the aging condition is lighter, or the operating temperature is higher, more charge is stored in the supercapacitor. Consequently, when the same discharge current is applied, the discharge time is longer and the branch capacitors are more deeply discharged. Therefore, the relaxation effects of the slow branches are reduced and the supercapacitor behaves more like a single capacitor rather than a distributed capacitor network, which ultimately leads to a lower Peukert constant. [ABSTRACT FROM AUTHOR]

The capacitance of sub-module capacitor has a great impact on the cost, size, and operation of the modular multi-level converter (MMC). However, the capacitance selected by the existing methods does not always meet the requirement in practice. To find out the reasons for this improper selection, the existing selection methods are analyzed in this paper. Based on the analysis, a new capacitance-selection method is proposed. In the new method, the problems of the existing methods are solved, and the calculation of capacitor voltage is based on a proposed capacitor-voltage model whose calculation error can be smaller than 0.1%. Furthermore, the Secant Method is used in the capacitance selection to quickly calculate the required capacitance. The new capacitance-selection method can be applicable to the MMC not having a circular operating region. In addition, this paper found that the capacitor voltage and the capacitor-voltage ripple reach their maximum values when the power-factor angles of the MMC are –π/2 and π/2, respectively, and the dc component in the capacitor voltage changes according to the operating condition of the MMC. Finally, the proposed selection method and theoretical analyses are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

In low-power applications of photovoltaic (PV) systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size, and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single dc-link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common-mode leakage current caused by parasitic capacitances of PV panels, whereas it is controlled with the unipolar sinusoidal pulsewidth modulation. Also, the results show that the common-mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the dc-link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a new non-isolated two-input single-output dc–dc converter with high voltage gain is proposed. In the proposed converter, there are two three-winding coupled inductors used to achieve a high voltage gain and ripple-free input currents. The proposed converter has two switches, and their control pulses are the same as the control pulses of the two-phase interleaved converters with a phase shift equal to $\text{180}^{\circ} $. The voltage stresses of switches and diodes are reduced and are always lower than the high output voltage. The proposed converter is extendable to a four-input single-output converter in which the switches have the control pulses the same as those in four-phase converters with phase shifts equal to $\text{90}^{\circ} $. In this paper, the proposed topology is analyzed in all operating modes, and the values of current and voltage stresses of all switches and diodes, voltage gain, and required conditions for input current ripple cancelation are calculated during a switching period. Finally, the accuracy performance of the proposed converter is reconfirmed through experimental results for 225- and 298-W prototypes. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

The use of LCL filters is a well-accepted solution to attenuate the harmonics created by the pulsewidth modulation. However, inherently LCL filters have a resonance region where the unwanted harmonics are amplified, which can compromise stability. Several techniques have been developed in order to tackle this issue. At first the use of passive damping, by intentionally increasing the resistance of the LCL filter components, is a simple, robust, and straightforward solution; however, it decreases the overall efficiency of the system, and hence in general is unwanted. Alternatively, active damping strategies, where the resonance damping is provided by the current controller, are of major interest. This paper analyzes the robustness of the closed-loop dynamics when different active damping techniques are implemented. The analyzed active damping techniques, which have been selected because of their readiness and simplicity, are: 1) filtered capacitor voltage feedforward and 2) second-order filters in cascade with the main current controller. The impedance/admittance stability formulation is used to model the system, which has been proven to be very convenient for the assessment of robustness. Experimental tests are provided in order to show the accuracy of the analysis and verify the findings. This paper proves that filtered capacitor voltage feedforward is a more robust and reliable solution than implementations based on cascade notch filters. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dc power electronic transformer (DCPET) topology for locomotive, ac/dc hybrid grid, dc distribution grid, and other isolated medium-voltage and high-power applications. Compared with conventional PET topology, the proposed DCPET has fewer power semiconductor devices and high-frequency isolation transformers, which can improve the power density and reliability. Fault handling or redundancy design can be achieved to further improve the reliability when some dc–dc modules break down. Also, input voltage sharing control can be omitted to simplify the control system and improve the stability. Meanwhile, soft switching is guaranteed for all the switches, which is beneficial to increase switching frequency and improve power density. In this paper, the principle, evolution, and control of the proposed DCPET are respectively presented and studied in detail. Finally, a prototype of the proposed DCPET is built and the experimental results verify the validity and superiority of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a practical strategy for utilizing the submodule (SM) redundancy of a modular multilevel converter (MMC) for its fault tolerance. This strategy provides a systematic framework for balancing the tradeoff between two conventional methods for using the active redundancy and, thus, achieves operational flexibility. One of the existing methods improves SM reliability owing to less voltage stress on the SM components by employing all of the SMs to form the ac or dc voltages (voltage-sharing mode). The other avoids transients by keeping the average SM voltage constant at the cost of slightly increased stress on the SM components (fixed-level mode), which, however, can be controlled to provide the grid-adaptive operation by reserving the energy of the SMs not in service. We, thus, develop a new redundancy management scheme by integrating these two methods and exploiting their technical benefits to meet the PQ requirements and MMC control performance. This research provides a theoretical basis and a technical guide to determining the number of SMs, which can further increase the voltage steps as per the MMC and grid conditions. This paper also connects the remaining PQ capability of the MMC at a particular operating point with the SM redundancy concept by defining a potential redundancy, especially useful when the physical redundancy is exhausted. The theoretical findings and efficacy of the proposed strategy are validated through PSCAD/EMTDC time-domain simulations followed by experiments using a nine-level single-phase MMC system. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

Power management integrated circuits (PMICs) with on-chip compensation are widely used to power multiple loads in mobile devices with increased power density. However, there are two issues for on-chip compensated PMICs. First, on-chip compensation reconfigurability is required to obtain the appropriate response in various passive components. Second, a converter for a processor requires adaptive voltage positioning (AVP) to reduce the output capacitor size. In this paper, a novel reconfigurable on-chip compensated current-mode buck converter with AVP is proposed to solve the aforementioned issues without requiring high-speed and high-resolution analog-to-digital converter (ADC). A reconfigurable accurate load line control scheme and on-chip compensation are proposed to achieve an accurate load line and AVP in various load lines and passive components. The control scheme, small-signal model, and circuit implementation are illustrated in this paper. The proposed buck converter was implemented into an integrated circuit to verify the analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new soft-switching bridgeless single-phase power factor correction (PFC) converter is presented and analyzed. Employing an auxiliary switch, the input current dead angle that is the main drawback of the existing buck-type PFCs is omitted, and thus, the power factor (PF) is improved, which is the main contribution of the paper. Proposed PFC converter operates under discontinuous conduction mode (DCM) and draws sinusoidal input current from power supply inherently. All switches and diodes are turnedonandoffunder soft switching, which leads to low switching losses and elimination of diode reverse recovery problems. Also, minimum numbers of semiconductor devices are in the power flow path that reduce the conduction losses. A 120-W laboratory prototype is implemented and experimental results verify the validity of theoretical analysis and show efficiency of 92.1%. In addition, total harmonic distortion (THD) of 3.3% is achieved and the input current harmonics complies with IEC61000-3-2 Class D requirements. [ABSTRACT FROM AUTHOR]

Power converters and electric motor drives when tightly regulated behave as constant power loads. These loads are different from resistive loads and have destabilizing negative impedance characteristics, which impact a system's stability. A boost converter is intrinsically nonlinear and is a nonminimum phase system at the output voltage with respect to the control input. The linear approximation of this boost converter loaded with a constant power load has a zero and poles in the right half of the $s$ -plane, making the system unstable and very difficult to control. Control techniques that employ some form of system inversion cannot be implemented for a nonminimum phase system. This paper describes a technique to modify the nonminimum phase boost converter to a minimum phase for a constant power load, further implementing the input–output linearization technique to stabilize the system. This paper also provides a methodological analysis of the problem followed by the proposed solution. Furthermore, it verifies the analysis of the proposed solution through simulation and experimental results. [ABSTRACT FROM AUTHOR]

A high step-up dc–dc converter is proposed in this paper. The presented converter benefits from some advantages such as high voltage gain and continuous input current, which makes it suitable for the renewable energy applications. The presented converter is based on the SEPIC converter. However, the converter voltage gain is improved by employing a coupled inductor and two voltage multipliers. A passive clamp circuit is also added to the proposed converter that increases the voltage gain and reduces the voltage stress on the main switch. Thus, a switch with low $R_{{\text{DS(on)}}}$ will be needed that decreases the conduction loss. Besides, the voltage stress on the output diode in the proposed converter is reduced, which alleviates reverse recovery problem. The steady-state analysis of the proposed converter is discussed in this paper. The analysis is verified with experimental results under the output power of 245 W. [ABSTRACT FROM AUTHOR]

This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common-mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper, first, establishes the equivalent common-mode circuit of the proposed inverter. The impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. [ABSTRACT FROM AUTHOR]

In high-power applications, parallel-operated T-type three-level pulse width modulation (PWM) rectifiers (T3LPRs) are widely employed to improve the power capacity and system reliability. For parallel-operated T3LPRs, there are two important issues need to be properly addressed: 1) the neutral-point potential (NPP) balancing, and 2) the zero sequence circulating current (ZSCC) between the common ac and dc bus. In this paper, the fluctuation of NPP in a T3LPR and the generative mechanism of ZSCC in parallel-operated T3LPRs are first investigated. The zero sequence voltage (ZSV) difference between the parallel-operated T3LPRs is identified as the main excitation source of the ZSCC problem. Meanwhile, the disconnection of the neutral point and the control effect difference of NPP balancing in each T3LPR also affect the ZSCCs within the parallel-operated T3LPRs. To adjust the ZSV of T3LPRs, the dwell time of the positive small voltage vector in each switching period of the converter, which is usually adjusted to balance the NPP, is also required to be controlled to suppress ZSCC. Therefore, in this paper, to avoid the possible conflict, an improved modulation mechanism is designed to guarantee simultaneous ZSCC suppression and NPP balancing. The neutral points of each T3LPR are connected. Then, by adjusting the dwell time of the positive small voltage vector, the charging time of two dc capacitors is adjusted to balance the NPP, and the ZSV differences between different T3LPRs are adjusted to suppress ZSCCs. To avoid the control effect difference of independent NPP balancing in different T3LPRs, all T3LPRs share the same value marking the difference between two dc capacitor voltages. Thus, a communication with a greatly reduced baud rate requirement is needed for NPP balancing to transfer the difference between the two dc capacitor voltages. Moreover, no extra circuit is needed for ZSCC suppression. These approaches make the proposed improved space vector PWM strategy much more practical and easy to employ. The proposed method is verified with experiments on two 3-kW T3LPR prototypes. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new structure of nonisolated boost dc–dc converters based on voltage-lift technique is proposed. In comparison with conventional nonisolated boost dc–dc converters, the proposed converter generates higher voltage gain. In this paper, the relations between voltage and current of all elements in continuous conduction mode and discontinuous conduction mode are calculated as well as voltage gain in each mode. Then, the critical inductance and stress of switch current are extracted. Finally, the validity of given theories is examined by using the experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes a new battery cell voltage equalization approach using multiple-receiver wireless power transfer (WPT) working at megahertz (MHz). Compared with existing multiwinding transformer, the MHz multiple-receiver WPT system is advantageous in terms of saved weight and space, ease of implementation, and improved safety. In this paper, the unique operating principle of the WPT-based equalization is first explained, through which equalization currents are naturally determined by the battery cell voltage distribution. The currents are also analytically derived. This facilitates the discussion on power amplifier (PA) design. Performance analysis is then provided to investigate the influences of system parameters on the efficiency and equalization ability of the proposed WPT-based equalization system, and thus guide following design and implementation. Considering the uncertainty in PA load due to the random cell voltage distribution, a current-model Class $E$ PA is designed that enables approximately constant PA output current. Experimental results show that the proposed multiple-receiver WPT-based battery cell equalization system can achieve high overall system efficiency (above 71%) when equalizing six lithium-ion battery cells under loosely coupling ( $k$ = 0.065). A good match between the experimental and calculation results also validates the correctness of the theoretical discussion. [ABSTRACT FROM PUBLISHER]

This paper documents a new three-switch, isolated boost dc–dc converter. The major features of the proposed converter are as follows: 1) continuous input current; 2) reduced one active switch, one additional diode, and one additional capacitor; 3) unchanged primary and secondary voltage waveforms of the transformer when the duty cycle is changed; and 4) removal of the snubber circuit. This paper presents the operating principles, analysis, parameter design guidelines, and simulation results for the proposed converter. To verify the performance of the proposed converter, a 400 W prototype was constructed with a 40–60 V dc input. A PID controller was used to maintain the dc output voltage at 400 V. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

An extended-duty-ratio (EDR) boost converter is studied extensively in this paper for high voltage gain applications with a wide input (and/or output) voltage range. The EDR is a unique combination of an interleaved, multiphase boost converter and switched capacitor configuration that achieves high voltage gain with significantly lower switch voltage stress and switching losses compared to conventional high-gain solutions. Most of the switches in the multiphase EDR experience only a fixed fraction of the output voltage ($1/M, 2/M$ , etc., where $M$ is the number of phases). Through extensive analysis over a wide operating range, it is shown here that the EDR boost converter has inherent current sharing among the phases only in a limited range of duty ratio— $(M-1)/M \leq D \leq 1$. As the duty ratio reduces beyond this range as required in wide input voltage applications, inherent current sharing property is lost. In this paper, techniques to ensure current sharing under all operating zones without requiring current sensors are presented. Instead of having equal duty ratio for each phase, it is adjusted for each phase according to the operating region of the converter. Extensive analysis is presented to derive the required duty ratio changes for the different phases. The proposed concept is validated with experimental results from a 250 W, 3-phase EDR boost, and GaN-based hardware prototype. [ABSTRACT FROM AUTHOR]

Conventional single-phase power-factor-correction (PFC) rectifiers with active power decoupling capability typically require more than three active switches in their circuits. By exploring the concept of power-buffer cell, a new single-stage PFC rectifier with two active switches, one inductor and one small power-buffering capacitor is reported in this paper. The proposed converter can achieve high-power factor, wide output voltage range, and power decoupling function without using electrolytic capacitor. Additionally, an automatic power decoupling control scheme that is simple and easy to implement is proposed in this paper. The operating principle, control method, and design considerations of the proposed rectifier are also provided. A 100-W prototype with ac input voltage of 110 Vrms and a regulated dc output voltage ranging from 30 to 100 V has been successfully designed and practically tested. The experimental results show that with only a 15 μF power-buffering film capacitor, the proposed converter can achieve an input power factor of over 0.98, peak efficiency of 93.9%, and output voltage ripple of less than 3%, at 100-W output power. [ABSTRACT FROM PUBLISHER]

DC/DC converters connected in series or parallel allow low power devices to be used in high power conversions. The input series output series (ISOS) connection is suitable for situations where both the input and output sides are high voltage fields. To ensure that each module shares voltage with the other, this paper proposes an active output voltage sharing (AOVS) control scheme. The scheme introduces sharing control in the output side so that the isolation is not needed between the input and output sides in the control loop. The AOVS control scheme, consisting of a common output voltage loop and individual output voltage sharing loop, has a master–slave structure. To improve the reliability and realize a hot-plug, this paper also provides an automatic master–slave form of the AVOS control scheme. A simulation of the frequency and time domains is used to verify the accuracy of the small signal model, and an ISOS-connected prototype consisting of three forward converters is made to test the steady and dynamic characteristics of the proposed scheme. [ABSTRACT FROM AUTHOR]

A new static synchronous compensator (STATCOM) based on the diode-clamped modular multilevel converter (DCM2 C) is proposed in this paper. In this converter topology, the capacitor voltage is clamped by using a low power rating diode in each submodule. The quantity of voltage sensors is significantly reduced and is free from the number of voltage levels. Furthermore, the voltage balancing control method becomes very simple and the capacitor voltage balance speed is fast. Based on the structure of modular multilevel converter, the DCM2C-STATCOM has the capability of Var compensation and negative-sequence current compensation. The topology characteristics and compensation control method of DCM2C-STATCOM are investigated in this paper. Experimental results obtained from a laboratory prototype validate that the capacitor voltage of the proposed DCM2C-STATCOM can be well balanced and the Var and negative-sequence current compensations are effective. [ABSTRACT FROM AUTHOR]

This paper presents an intensive discussion on a high-voltage direct-current (HVDC) long-distance transmission system combining two modular multilevel double-star chopper-cells (DSCC) converters with dc power cables. Hereinafter, each converter is referred to simply as a DSCC converter, or just as a DSCC for more simplicity. Such an HVDC transmission system is required to provide low-voltage-ride-through (LVRT) capability to enhance system availability. This paper proposes a practical LVRT control characterized by the use of power-line communications between the two DSCC converters. The validity and effectiveness of the LVRT control is verified not only by simulated waveforms obtained from the software package “PSCAD/EMTDC” but also by experimental waveforms from a three-phase 200-V, 400-Vdc, 10-kW, 50-Hz downscaled system with 300-m-long dc power cables. [ABSTRACT FROM AUTHOR]

This paper proposes a dc-link voltage shaping method for a cascaded H-bridge (CHB) static synchronous compensator (STATCOM). A recently proposed low capacitance-STATCOM system, which intentionally operates with large voltage ripples on the dc-link capacitors, offers the advantage of superior harmonic performance. However, the capacitor voltage ripples decrease when operating at below-rated reactive current, which removes the aforementioned harmonic performance benefit of this system. In addition, such harmonic performance benefit is only achieved in capacitive operation mode. In order to expand the operating region where advantageous voltage ripples are present, a new voltage shaping method is proposed. The proposed method uses a CHB multilevel converter coupled with simple dc–dc converters to shape voltage ripples on the dc-link capacitor regardless of its operating point. This is achieved by controlling the average current of the dc–dc converter using model predictive control. The concept is best applied to an enhanced STATCOM, or E-STATCOM, application in which the STATCOM is integrated with either a renewable energy source or energy storage system. The operational principle of the proposed approach is validated via simulation and experimental results on a five-level single-phase CHB STATCOM. [ABSTRACT FROM AUTHOR]

Multilevel converters are widely applied in medium voltage (MV) drive systems due to the attractive features, such as the ability to use devices with lower voltage ratings, high equivalent switching frequency, etc. Recently, a multilevel topology, named seven-level hybrid clamped (7L-HC), is proposed for MV drives. It has a competitive number of devices, showing the potential to build low-cost 7L converters. However, to ensure the wide frequency range operation and power quality of MV drives, its dc-link capacitors and floating capacitors must be controlled properly with balanced voltages. In this paper, an active voltage balancing method is proposed for the 7L-HC converter. This method can effectively balance all the capacitor voltages under a wide frequency range. The method is embedded in the PWM procedure without modifying the control strategies. Simulation and experimental results are provided to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a voltage multiplier topology that is a hybrid between a Cockcroft–Walton multiplier and a Dickson charge pump. The Cockcroft–Walton structure exhibits significant output voltage drop under load as the number of multiplier stage increases. This is because all coupling capacitors are connected in series. Dickson charge pump mitigates this issue by connecting all capacitors in parallel. But this solution comes at the expense of large capacitor voltage stress at the last multiplier stage. The proposed hybrid structure arranges some capacitors in parallel and others in series, thereby achieving low output voltage drop and low capacitor voltage stress at the same time. We develop a model that predicts hybrid multiplier's performance and validates it experimentally. We also demonstrate a 60–2.25 kV dc–dc converter based on a 16-stage hybrid voltage multiplier which achieves a voltage gain of 12.8 while keeping the highest capacitor voltage stress to 660 V. [ABSTRACT FROM AUTHOR]

An isolated bidirectional dc–dc converter, which combines parallel-connected two-level converters (TLCs) on the medium-voltage side and a modular multilevel converter (MMC) on the high-voltage side, namely a TLC-MMC converter, is a promising candidate for the interconnection of medium-voltage direct current (MVDC) and HVdc grids. Different from typical phase-shift controlled isolated bidirectional dc–dc converters, transformer currents of a TLC-MMC converter are regulated by the MMC in a closed-loop manner in order to achieve extremely low switching losses and low total device rating of power-semiconductor devices in TLCs. This paper addresses the dedicated operation technique and the voltage-balancing control of the TLC-MMC converter. The MMC in the TLC-MMC converter operates with six-step phase voltages and sinusoidal phase currents. Such an operation makes the MMC present remarkable differences to ac–dc applications. The direct-modulation technique, which is the most-used technique performed to MMCs in line-frequency ac–dc power conversion, has been concluded not applicable to the MMC in a TLC-MMC converter due to the significant sixth-order oscillation resulted in the dc-link voltage. Thus, the indirect-modulation technique is employed, and consequently a closed-loop voltage-balancing control is mandatory for the MMC. Possible measures for voltage balancing have been explored, and effective voltage-balancing control with a simplified implementation is proposed. Validity and effectiveness of the proposed control strategy have been verified by both simulations and experiment using a downscale prototype. [ABSTRACT FROM AUTHOR]

In this paper, a dual half-bridge LLC resonant converter with magnetic control is proposed for the battery charger application. The primary switches are shared by two LLC resonant networks, and their outputs are connected in series. One of the LLC resonant converters is designed to operate at the series resonant frequency, which is also the highest efficiency operating point, and the constant output voltage characteristic is achieved at this operating point. The second LLC resonant converter adopts magnetic control to regulate the total output current and voltage during both constant current charge mode and constant voltage charge mode. Meanwhile, the function decoupling idea is adopted to further improve the system efficiency. The significant amount of the power is handled by the LLC resonant converter operating at the series resonant frequency, whereas the second LLC resonant converter fulfills the responsibility to achieve closed-loop control. By carefully designing the resonant networks, the zero-voltage switching for primary switches and zero-current switching for secondary diodes can be achieved for whole operation range. A 320-W experimental prototype is built to verify the theoretical analysis, and the maximum efficiency is measured about 95.5%. [ABSTRACT FROM AUTHOR]

Load-independent output characteristics of inductive power transfer (IPT) systems are increasingly popular in battery charging. This paper proposes a novel variable-parameter T-circuit (VT) for an IPT system charging a battery with constant current (CC) or constant voltage (CV) output. The VT can transfer a CC/CV input to a CC or CV output by using an ac switch and a passive component (inductor or capacitor). An IPT system with a VT for CC–CV charging can reduce the number of passive components and ac switches. Besides, the proposed VT merits more design freedom of charge current/voltage with the constraints imposed by the loosely coupled transformer parameters compared to that of the traditional one. In addition, there are three kinds of VTs for various IPT charging systems with different requirements. A 400 W laboratory-scale prototype with a 150 mm air gap was built to verify the theoretical analyses. Both electronic load and lead-acid battery are utilized to verify the charging profile of the proposed method. The experimental results of the IPT system indicate that the fluctuation of the charging current in CC mode is less than 2%, and the change rate of charging voltage in CV mode is within 2.9%. The maximum overall efficiency 93.93% of the charging system is achieved from a dc 110 V input to a dc 100 V output. [ABSTRACT FROM AUTHOR]

This paper proposes a constrained modulated model-predictive control (M $^{2}$ PC) scheme for an LC-filtered voltage-source converter (VSC). To tackle the coupling effects of the state variables in a second-order LC filter, a dual-objective cost function (CF) is used to explicitly track both capacitor voltage and inductor current references, which can achieve an improved voltage quality. To handle the state and control input constraints of VSCs, a constrained M $^{2}$ PC scheme is proposed with an “online post-correction” constraint-handling technique. First, the unconstrained optimal voltage vector (OVV) is derived. It is generated by seeking the minimum analytical solution of the CF offline, simplifying the online implementation. Then, an “online post-correction” strategy is employed by reconsidering the constraints to correct the precalculated OVV online, which guarantees the future states within the allowed range. Finally, the corrected OVV is synthesized by the space vector modulation, resulting in a fixed switching frequency and low harmonics. Compared with the typical constrained model-predictive control, the presented scheme has the advantages of improved steady-state performance, flexible constraint-handling ability, and lower computational cost. Additionally, design procedures for weighting factor selection in the CF are given. Comparative experiments are investigated to verify the presented control strategy. [ABSTRACT FROM AUTHOR]

In the no-load condition, LLC converter usually fails to regulate its output voltage although it operates at a high switching frequency. Till now, it is hard to obtain the exact relationship between design parameters and the maximum switching frequency for no-load regulation capability. In this paper, a specific criterion for no-load regulation of LLC converter is provided, without using active components or other modulation schemes. By analyzing the macroscopic switching period and microscopic switching transition in the no-load condition, it is shown that not only the peaking resonant current during the switching transition, but also the resonant tank design affect the no-load regulation of the LLC converter, which affects the no-load regulation capability. Furthermore, the relationship among design parameters is analyzed and the design guideline is also provided to achieve no-load regulation at the specified maximum switching frequency. To verify the effectiveness of the proposed design, 400 V input and 50 V/200 W output prototype is built and tested. [ABSTRACT FROM AUTHOR]

Unidirectional current H-bridge modular multilevel converter (UCH-MMC) is a variant of full-bridge MMC and uses fewer semiconductor devices. The operating area and operation mode of UCH-MMC differ from those of conventional half-bridge MMC (HB-MMC) because of the unidirectional current and bipolar voltage of UCH-MMC arms. Thus, analyzing the energy storage requirement (ESR) of UCH-MMC differs from that of HB-MMC. This paper proposes a model for calculating the ESR of UCH-MMC. The ESR of the UCH-MMC under the entire operating area is analyzed. A modified operating scheme that dynamically trims the sub-module capacitor voltage to allow the low capacitance operation under the entire operating area is proposed. Results verify that the UCH-MMC has much lower ESR than HB-MMC. Evaluation results also show that the cost and volume of the UCH-MMC are much lower than those of HB-MMC because of the low ESR. The low ESR of UCH-MMC was verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

The three-level full-bridge (TLFB) dc−dc converter has been widely used in high-voltage, high-power applications. In the experimental test, the neutral-point voltage deviation appears; moreover, it has also been found out that if the flying capacitors are introduced, the input capacitor voltages could realize self-balance even if no active balancing solutions are adopted. In the previous publications, the role of flying capacitors is generally considered to extend the range of soft switching; however, the self-balance ability has not been mentioned or investigated in any publications thus far. In order to fill this gap, this paper provides the detailed mode operation analysis of the TLFB converter and reveals the cause of the imbalance. In addition, the mechanism of the self-balance ability provided by the flying capacitors is explained in detail, which gives a deep insight into the converter. At last, the influence factor of the voltage error in steady state has been analyzed, and the specific expression of the voltage error is also derived. The feasibility of the theoretical analysis is verified by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a neutral point (NP) voltage balancing scheme suitable for three phase 5-level active NP clamped and T-type NP clamped (TNPC) inverters is discussed. Carrier-based pulsewidth modulation is used for the balancing of dc-link capacitors and floating capacitors (FC) in the inverter. The FC voltages are regulated with the help of redundant switching states of pole voltage levels and the dc-link capacitor voltages are controlled using zero-sequence voltage injection. Though the balancing approaches are different for dc-link capacitors and FCs, they are not decoupled from each other. This is due to the effect of certain redundant switching states used for FC balancing causing NP voltage variation. To address this issue, the redundant state time ratio is estimated online every sample and based on this dynamic time ratio, an optimal relationship between neutral current and zero-sequence voltage is established. It is found that the use of dynamic time ratio helps in achieving better transient performance than that of generally adopted fixed time ratio. Simulation and experimental results prove that the proposed balancing scheme works well under all operating conditions and exhibits fast and stable transient performance. [ABSTRACT FROM AUTHOR]

A conventional asymmetrical half-bridge (AHB) converter is one of the most promising topologies in low-power applications because of the zero-voltage switching (ZVS) of all switches and the small number of components. However, when it operates with an asymmetrical duty ratio, it has a large dc-offset current in the transformer, which increases the size and core loss of the transformer. Moreover, because the dc-offset current decreases ZVS energy for one of the half-bridge switches, it has low efficiency in a light load condition. In addition, because most of the output current is concentrated in high-voltage-rating diodes that have large forward voltage drops, large conduction loss occurs in the secondary rectifier. To solve these problems, a new AHB converter with a coupled inductor rectifier (CIR) is proposed in this paper. By adopting the CIR structure in the AHB converter, the proposed converter not only eliminates the dc-offset current in the transformer, but it also has equalized current stress in the rectifier diodes. As a result, the proposed converter achieves high efficiency in entire load condition, compared to an AHB converter with a full-bridge rectifier. The effectiveness and feasibility are verified with a 250–400 V input and 100 V/200 W output prototype. [ABSTRACT FROM AUTHOR]

Without active control, the voltage fluctuations of the dc-link and flying capacitors in a 4-level hybrid-clamped converter (4L-HCC) become excessively large in low-frequency operation. This paper studies the switching state redundancy inherent in a 4L-HCC and proposes a new capacitor voltage balancing and stabilizing method to minimize the dc-link and flying capacitor voltage fluctuations. A straightforward algorithm is developed based on a logic table to select the suitable switching states. Verified by simulation and experimental testing results, the new method and algorithm virtually eliminate all the big voltage fluctuations of capacitors at low and zero frequencies, greatly enhancing the robustness and reliability of a 4L-HCC. The capacitor size can be reduced by more than 80% compared with the conventional method. [ABSTRACT FROM AUTHOR]

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ($C_{F}$) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100 μA to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved. [ABSTRACT FROM AUTHOR]

This paper proposes a three-phase, five-level, non-regenerative pulsewidth modulated rectifier using only two active switches (minimum required) per phase, which drastically reduces gate driver requirement and hardware complexity. It draws sinusoidal input current at close to unity power factor. All the semiconductor devices are rated at only one fourth of the dc-link voltage, and none of them requires any transient voltage balancing snubber. A total of 8 out of the 14 diodes per phase undergo soft switching transition under all operating conditions, which increases its efficiency. No extra hardware circuitry for balancing the flying capacitors (FCs) or the dc-link mid-point voltage are required, which further reduces hardware complexity and increases the conversion efficiency. The proposed topology does not need any sophisticated startup procedure for charging the FCs either, which solves the problem of semiconductor overvoltage during starting. A 3-kW laboratory prototype is built to experimentally verify the proposed topology. The maximum efficiency obtained from the prototype is 98.7%, and it is always more than 96% for the load range from 15% to its rated. [ABSTRACT FROM AUTHOR]

Synchronous rectification (SR) for LLC resonant converters has been developed to enhance the power conversion efficiency and achieve high-power-density design. Conventional SR driving strategies can be categorized as current-driven methods, $v_{\text{DS-ON}}$ sensing methods, and alternative approaches. The current-driven methods widely adopt current transformers (CTs) to sense the rectifier current and generate the SR driving signals. The CTs are lossy and bulky, which is unfavorable to high-power-density design. The $v_{\text{DS-ON}}$ sensing methods remove the current sensors by sensing the voltage across the on-state resistor of the SR mosfet, yet the sensed signal is small and prone to be offset by the inductive voltage induced from parasitic components. Most alternative approaches avoid sensing noise-sensitive signals; however, the operating range is narrow due to the limited information from the converter. This paper proposes an SR driving strategy based on the resonant capacitor voltage (RCV) to address those issues. The RCV SR driving strategy does not require current sensors. The sensed RCV is insensitive to the parasitic effects. In addition, the RCV strategy controls the SR on-time effectively over a wide range of operating frequency and loading conditions. Simulation and experimental results of a 650-W/24-V LLC converter are presented to validate the effectiveness of the proposed RCV strategy. Compared with the conventional $v_{\text{DS-ON}}$ sensing method, the on-time error caused by the parasitic effect is greatly reduced, which improves the power conversion efficiency and reduces the SR mosfet temperature. [ABSTRACT FROM AUTHOR]

In this paper, instantaneous pulse power compensator (IPPC) method is proposed to achieve power pulsation decoupling function for single-phase inverter applications. A smaller capacitor is placed in series with the traditional dc-link capacitor, and this smaller capacitor voltage is controlled using pulse currents to cancel out the dc-link voltage ripple. Unlike twice-line-frequency power decoupling method, the proposed IPPC method can compensate the pulsating power with all the orders harmonics on the dc-link line, not only the second-order component. Both modeling and simulation results show that IPPC method can achieve nearly zero voltage ripple for the dc-link capacitor since the pulse current is fully compensated. Whereas twice-line-frequency power decoupling method has limit in voltage ripple reduction, especially in small dc-link capacitance conditions. The experimental results based on a full-bridge topology decoupling circuit and a single-phase inverter application show consistent results with simulation results. A 16% reduction of the prototype size, i.e., 16% higher power density with only ∼1% efficiency penalty can be achieved by the proposed IPPC method when compared to the second-order power decoupling method. [ABSTRACT FROM AUTHOR]

A hybrid modular multilevel converter (MMC) consists of both half-bridge submodule (HBSM) and full-bridge submodule (FBSM) in each arm. It has several advantages over other MMC topologies, such as low system loss, reduced cost of the system, but still maintains fault ride-through capability against a solid dc-side fault. However, the hybrid MMC may have a difficulty of submodule (SM) voltage balancing under variation of its dc-bus voltage. Since the voltage unbalance of SMs results in SM capacitor overvoltage and low reliability of the system, the voltage of SMs, which can be also represented as energy of SMs, should be balanced at all time. In this paper, to extend the narrow adjustable range of dc-bus voltage due to the voltage/energy unbalance, new feedback and feedforward energy balancing controllers with revised sorting algorithm are proposed. The feedback control ensures the zero steady-state error, while the feedforward control provides fast dynamic response in the energy balancing control. By applying the proposed control scheme, the hybrid MMC can keep the voltage balance between HBSMs and FBSMs in wider range of dc-bus voltage. The full-scale computer simulation results and down-scale experimental results demonstrate the validity of the proposed control scheme. [ABSTRACT FROM AUTHOR]

When providing ac output, modular multilevel converters (MMCs) experience power fluctuation in the phase arms. The power fluctuation causes voltage ripple on the module capacitors, which grows with the output power and inversely to the output frequency. Thus, low-frequency operations of MMCs, e.g., for motor drives, require injecting common-mode voltages and circulating currents, and strict dc voltage output relative to ground is impossible. To address this problem, this paper introduces a novel module topology that allows parallel module connectivity in addition to the series and bypass states. The parallel state directly transfers power across the modules and arms to cancel the power fluctuations and hence suppresses the capacitor voltage ripple. The proposed series/parallel converter can operate at a wide frequency range down to dc without common-mode voltages or circulating currents; it also allows sensorless operation and full utilization of the components at higher output frequencies. We present detailed simulation and experiment results to characterize the advantages and limitations of the proposed solution. [ABSTRACT FROM AUTHOR]

Generating dense multilevel voltage space structure using polygons of higher sides is one of the novel and elegant method to suppress low-order harmonics and to obtain refined sinusoidal voltages using voltage source inverters for variable frequency drive application without passive filters. Apart from the advantages of conventional multilevel inverter topologies, schemes generating polygonal voltage space vector structure can equip full dc-bus utilization, low switching frequency strategies to eliminate low-order harmonics, and increased linear modulation range. In this paper, an induction motor drive scheme generating a highly dense multilevel 24-sided polygonal voltage space vector structure using a single dc source, which can eliminate harmonics till 23rd order from phase voltages, is presented. Cascaded power circuit topology with a flying capacitor inverter fed with a dc source and two low voltage floating capacitor fed H-bridge inverters is used. Detailed experimentally validated results, under scalar as well as indirect rotor field oriented control of induction motor are provided. Studies on voltage ripple and reactive energy in various floating capacitors, harmonic performance of output voltage for wide range of speed operation, are also included. [ABSTRACT FROM AUTHOR]

This paper proposes a method for fault-tolerant operation of medium voltage modular multilevel converters (MMCs) with phase-shifted carrier (PSC) modulation. The existing methods need to recalculate and reconfigure all the carriers every time a submodule (SM) fails. However, the proposed method combines the sorting voltage balancing control and the PSC modulation to avoid breaking the symmetry and balance of the carriers. Therefore, the modulation stage in the proposed method can be kept the same and the output voltage of the MMC can remain unchanged without causing voltage mismatch. Moreover, considering the modulation margin and the physical redundancy configuration, two fault SM replacing strategies, i.e., optimal dynamic performance and optimal electrical stress are proposed as well as their respective control structures. Compared with the normal operation of the MMC, the proposed fault-tolerant operation method has only slightly changed the control system and thus the added calculation burden and control complexity can be ignored, which is extremely beneficial for the practical implementation. The effectiveness and performance of the proposed operation method are carefully verified by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a generalized design framework for three-phase Vienna rectifiers to handle the neutral point voltage balance issue. On the basis of the design framework, it is convenient to construct various neutral point voltage balancing methods with the guarantee of stability. As demonstration, three representative neutral point voltage balance approaches are presented by choosing different zero-sequence voltages. A comprehensive comparison among the three approaches is given in the aspects of input current quality, capacitor voltage fluctuation, and system efficiency. The comparison results provide guidance for constructing the most appropriate approach based on the specific requirement. Finally, simulation and experimental results verify the correctness and effectiveness of the presented approaches and the related performance analysis. [ABSTRACT FROM AUTHOR]

A conventional phase-shifted full-bridge (PSFB) converter is one of the most promising topologies in high-efficiency and high-power applications because of its small RMS current, inherent zero-voltage switching capability, and clamped voltage stress of the primary switches. However, when the PSFB converter operates with a small duty ratio, a large freewheeling current of an output inductor flows in the primary side, and it causes a large circulating current. In addition, it has a large voltage stress in the rectifier diodes due to a voltage ringing between parasitic components. To solve these problems, a new PSFB converter with a coupled inductor rectifier (CIR) is proposed in this paper. By adopting the CIR structure in the PSFB converter instead of the full-bridge rectifier, the proposed converter eliminates the freewheeling current in the primary side, which significantly reduces the primary circulating current. In addition, the two rectifier diodes of the CIR do not have voltage ringing. As a result, the proposed converter not only reduces the conduction loss in the primary side, but can also use two diodes in the rectifier with a low voltage rating. The effectiveness and feasibility were verified with a 320–400 V input and 56-V/12.8-A output prototype. [ABSTRACT FROM AUTHOR]

This paper presents a modified negator-based switched-capacitor (NSC) dc–dc converter to achieve fine-grained voltage conversion ratios. Based on a concept of reconfiguring several 2:1 switched-capacitor (SC) converters in series and parallel at the last stage, the proposed asymmetrical shunt SC (ASSC) converter provides more controllable variables of forward gain and feedback gain to decide different power path interconnections and increase the available conversion ratios, with a little sacrifice of its slow switching limit output impedance. The switching loss of the bottom-plate parasitic capacitance in the ASSC converter is less than the switching loss of the NSC topology because the two moderate voltages instead of the power rail are fed to the last stage 2:1 SC unit and reduce the voltage swing. The bottom-plate swapping prototype further reduces the parasitic loss at high conversion ratios. To handle a large number of conversion ratios in closed-loop regulation, the ASSC converter uses the fast optimum ratio searching (FORS) technique, which evaluates the transient voltage drop to quickly search for target ratios and reduce the transient recovery time. A three-stage ASSC converter achieving 187 conversion ratios is fully integrated in the test chip, which is fabricated in 0.25-μm CMOS process with an active area of 7.14 mm2. Furthermore, 2389 conversion ratios can be derived in theory for a four-stage ASSC converter. The proposed reconfigurable SC converter provides an output voltage range of 0.4 to 2.8 V under no load conditions, and greater than 80% power efficiency at an output voltage level of 0.9 to 1.5 V over a load range of 3 to 9.5 mA. Due to the FORS technique, the measured transient recovery time is reduced from 7 to 1.5 μs in case of load current step of 7 mA. [ABSTRACT FROM AUTHOR]