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This paper presents the digital implementation of a boundary controller with unipolar switching characteristic for single-phase voltage source full-bridge inverters. This paper expands the application of a second-order switching surface-based control method to unipolar switching of single-phase voltage source inverters (VSIs) using a finite-state machine. The finite-state machine has been formulated considering four different states of the inverter; positive,zero1, negative, andzero2. The second-order boundary control governs the current state of the system and provides proper switching action to keep the system within the desired reference. The control law is implemented digitally in F28m35x digital control card. A full-bridge inverter topology is used to achieve the three-level voltage switching. Various simulations and experiments were performed in a 550 VA, 120 V, 60 Hz VSI with a digitally implemented controller to verify the theoretical predictions. A high-quality voltage output was obtained for various loading conditions. The transient performance of the controller was investigated using a reference and load changes. A comparison of the implementation was made with the existing classical controllers to verify the fast-dynamic response of the system. [ABSTRACT FROM AUTHOR]

This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common-mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper, first, establishes the equivalent common-mode circuit of the proposed inverter. The impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new high-efficiency photovoltaic (PV) converter for grid connection through a high-leg delta transformer. The converter is composed of a symmetrically connected boost converter and three half-bridge inverters. One of the three half-bridge inverters is connected to the boost converter, and the others are directly connected to the PV terminals. As a result, this circuit configuration enables to reduce the power losses in both boost converter and inverters. This paper also proposes a new cooperative control method between the symmetrically connected boost converter and inverter. The control method can reduce the average switching frequency to 75% of that in a conventional one, resulting in a great reduction in the switching power loss. Experimental results confirm that the proposed circuit configuration makes it possible to improve its European efficiency from 91.6% to 94.5%. Moreover, system performance is evaluated on the assumption of maximum power point tracking operation. [ABSTRACT FROM AUTHOR]

In this paper, a neutral point (NP) voltage balancing scheme suitable for three phase 5-level active NP clamped and T-type NP clamped (TNPC) inverters is discussed. Carrier-based pulsewidth modulation is used for the balancing of dc-link capacitors and floating capacitors (FC) in the inverter. The FC voltages are regulated with the help of redundant switching states of pole voltage levels and the dc-link capacitor voltages are controlled using zero-sequence voltage injection. Though the balancing approaches are different for dc-link capacitors and FCs, they are not decoupled from each other. This is due to the effect of certain redundant switching states used for FC balancing causing NP voltage variation. To address this issue, the redundant state time ratio is estimated online every sample and based on this dynamic time ratio, an optimal relationship between neutral current and zero-sequence voltage is established. It is found that the use of dynamic time ratio helps in achieving better transient performance than that of generally adopted fixed time ratio. Simulation and experimental results prove that the proposed balancing scheme works well under all operating conditions and exhibits fast and stable transient performance. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

This paper analyzes the possibility of controlling the output voltage of a standalone single-phase inverter by directly controlling the output filter capacitor current without using a dedicated output voltage sensor. The plant modeling and controller design are presented. The proposed method depends on having the value of the output filter capacitance. A method to estimate the output filter capacitance is also presented. Rigorous analysis is done to show that the proposed sensorless scheme is largely insensitive to parameter variations and ensure that the output voltage is within specified regulations at utility level. It is also demonstrated in this paper that compared to the conventional voltage control scheme the proposed control scheme ensures an improved total harmonic distortion of the output voltage waveform. Experimental results presented validate the proposed scheme. [ABSTRACT FROM AUTHOR]

An LLC resonant converter would have light-load voltage regulation problems due to the effect of parasitic capacitances in a high-frequency range. In this paper, an energy feedback control method is proposed to improve the light-load regulation capacity by using synchronous rectifiers (SRs). The SR bridges are controlled ahead of the primary inverter bridges to deliver the energy from load to source, reducing the output voltage independent of the load. Then the desired voltage can be achieved even in no-load conditions by regulating the operation time of the energy feedback mode. The gain, voltage ripple, and efficiency performances of the proposed control method are discussed based on the precise analysis and an accurate model of the converter. Moreover, the light-load operations of the LLC resonant converter are analyzed deriving the critical load condition. Finally, the proposed control method is verified by the experiments of a 12 V/8 A LLC resonant converter prototype. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

In a low-voltage parallel inverter system, the active power, unbalanced power, and harmonic power generally cannot be properly shared among inverters with droop control due to the mismatch of output impedance. To address this issue, this paper proposes a two-stage adaptive virtual resistor (AVR) control scheme. In the first stage, a proportional-integral controller is applied to regulate the active power with the use of a synchronous maximum power bus (SMPB), and the reactive power is adjusted by means of aQ–ωdroop controller. In the second stage, all inverters switch to aP–Edroop control mode by introducing the AVRs at fundamental positive-sequence, negative-sequence, and harmonic frequencies. Not only can this method eliminate the active power, unbalanced power, and harmonic power-sharing errors, it can also reduce the voltage deviation caused by the droop control. Moreover, the synchronization between inverters can be guaranteed as long as the SMPB is present, without using voltage sensors at the point of common coupling. Simulation and experimental results are provided to verify the feasibility of this method. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

Local hardware clocks in physically distributed computation devices hardly ever agree because clocks drift apart and the drift can be different for each device. This paper analyzes the effect that local clock drifts have in the parallel operation of voltage source inverters (VSIs) in islanded microgrids (MG). The state-of-the-art control policies for frequency regulation and active power sharing in VSIs-based MGs are reviewed and selected, and prototype policies are then reformulated in terms of clock drifts. Next, steady-state properties for these policies are analyzed. For each of the policies, analytical expressions are developed to provide exact quantification of the impact that drifts have on frequency and active power equilibrium points. In addition, a closed-loop model that accommodates all the policies is derived, and the stability of the equilibrium points is characterized in terms of the clock drifts. Finally, the implementation of the analyzed policies in a laboratory MG provides experimental results that confirm the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new pulse width modulation (PWM) scheme and commutation method is presented for one phase loss operation of three-phase isolated buck matrix-type rectifier. With the proposed PWM scheme, the maximum allowable voltage gain for one phase loss operation can be achieved, which permits the continuous operation of the converter to deliver two-third of the rated power and regulate the output voltage with maximum output voltage drop less than 5% of nominal output voltage. In addition, with the proposed commutation method, a safe transition from one phase loss operation to normal operation and vice versa can occur with minimum commutation steps (two-step) under zero-voltage switching condition. The performance of the proposed PWM scheme and commutation schemes with one phase loss operation is evaluated and verified by simulations and experiments on a 5 kW prototype. [ABSTRACT FROM AUTHOR]

In this paper, a control strategy for the parallel operation of three-phase inverters forming an online uninterruptible power system (UPS) is presented. The UPS system consists of a cluster of paralleled inverters with LC filters directly connected to an ac critical bus and an ac/dc forming a dc bus. The proposed control scheme comprises two layers: 1) a local layer that contains a “reactive power-to-phase droop” in order to synchronize the phase angle of each inverter and a virtual resistance loop that guarantees equal power sharing among inverters; and 2) a central controller that guarantees synchronization with an external real/fictitious utility, and critical bus voltage amplitude restoration. Improved transient and steady-state frequency, active, reactive, and harmonic power sharing, and global phase-locked loop resynchronization capability are achieved. Detailed system topology and control architecture are presented in this paper. Furthermore, a mathematical model was derived in order to analyze critical parameters effects on system stability. The proposed control approach has been validated by means of experimental results obtained for several case-study scenarios. [ABSTRACT FROM AUTHOR]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

This paper provides a theoretical discussion and comparison in energy balancing between a modular multilevel cascade inverter based on single-star bridge cells (SSBC) and that on single-delta bridge cells (SDBC). Attention is paid to applications involving asymmetric active-power generation in utility-scale grid-tied photovoltaic systems. Both qualitative and quantitative evaluation metrics to assess the energy-balancing capability are introduced and applied to both SSBC and SDBC inverters. As for the SSBC inverter, six zero-sequence voltage waveforms with different harmonic content enabling enhanced energy-balancing capability are analyzed and compared regarding their effectiveness. This paper also emphasizes on the SDBC as an alternative to the SSBC and highlights its superior operating characteristics under asymmetric active-power generation. [ABSTRACT FROM PUBLISHER]

Two-stage single-phase inverters have been widely used as they can achieve voltage matching and galvanic isolation between the input and output. Due to the pulsating output power of the downstream inverter, an ac current at twice the output frequency, which is called second harmonic current (SHC), arises in the input side of the downstream inverter. This SHC will penetrate to the front-end dc-dc converter, leading to reduced conversion efficiency. This paper first analyzes the propagation mechanism of the SHC and load transient response of two-stage single-phase inverters from the viewpoint of output impedance. Then, based on the current mode control and load current feed forward, two control methods to achieve low SHC in the front-end dc-dc converter and fast dynamic performance during load transient are proposed in this paper. Finally, a 2-kW two-stage single-phase inverter prototype has been constructed and tested, and the experimental results are provided to verify the effectiveness of the proposed control methods. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

In classical inverter control, load current (disturbance) decoupling control is often used to improve the control performance. Yet, in a recent state-space control structure for multiresonant controllers, the load current decoupling technique is less studied. Moreover, in the classical control, the load current decoupling only has one control degree of freedom. Therefore, in this paper, a load current decoupling control combed linear quadratic (LQ) regulation is investigated, the proposed control structure that manipulates α and β axes as a unified system is adopted to increase the control degree of freedom. The LQ control synthesizes the state feedback control law including gains of the resonant controllers. Two general criteria, namely H\infty norm and zero dynamic, are proposed as the design guideline for the load current decoupling control. The effectiveness and robustness of the proposed approach are validated through MATLAB/Simulink simulations and experiments with a 5-kVA testbed. The results prove that some favorable performances, for example, the fast recovering time, the small voltage drop, and the low total harmonic distortion, are achieved by the proposed approach compared to the classical dual-loop proportional-resonant (PR) control with load current decoupling and the optimal H\infty control. [ABSTRACT FROM AUTHOR]

This paper presents a steady-state model of MMC for the second-order phase voltage ripple prediction under unbalanced conditions, taking the impact of negative-sequence current control into account. From the steady-state model, a circular relationship is found among current and voltage quantities, which can be used to evaluate the magnitudes and initial phase angles of different circulating current components. Moreover, in order to calculate the circulating current in a point-to-point MMC-based HVdc system under unbalanced grid conditions, the derivation of equivalent dc impedance of an MMC is discussed as well. According to the dc impedance model, an MMC inverter can be represented as a series connected R–L–C branch, with its equivalent resistance and capacitance directly related to the circulating current control parameters. Experimental results from a scaled-down three-phase MMC system under an emulated single-line-to-ground fault are provided to support the theoretical analysis and derived model. This new models provides an insight into the impact of different control schemes on the fault characteristics and improves the understanding of the operation of MMC under unbalanced conditions. [ABSTRACT FROM PUBLISHER]

In signal injection sensorless drives, the injection voltage cannot be reduced under a certain value. The lower limit of the injection voltage is mainly enforced by the inverter nonlinearity that causes distortion of the injection voltage and degradation of the position estimation performance. After analyzing the inverter nonlinearity during the voltage injection, it is revealed that parasitic capacitances of insulated-gate bipolar transistors have positive effects on inverter output linearity and sensorless control. Based on this analysis, this paper proposes a method to reduce the injection voltage by connecting additional capacitors to the output terminals of the inverter. Simulation and experimental results are provided to verify the effectiveness of the proposed idea. In the experiments, using the capacitor-integrated inverter, it is shown that the injection voltage can be reduced by more than half without degrading the position estimation performance. [ABSTRACT FROM AUTHOR]

This paper describes a variable-speed motion-sensorless control system for permanent-magnet synchronous generator (PMSG) connected to grid via back-to-back inverters for wind energy generation. The grid-side inverter control system employs proportional-integral (PI) current controllers with cross-coupling decoupling and line-voltage feedforward disturbance compensation. Also, a D-module filter is used to robustly extract the line voltage positive sequence followed by a phase-locked-loop (PLL) based observer to estimate the positive-sequence angle for control, including the case of asymmetric voltages and automatic seamless transfer method from grid connected to stand alone and vice versa. In stand-alone mode, a voltage control scheme with selective harmonic compensation is employed. The PMSG motion-sensorless control system uses an active power controller and a PLL-based observer to estimate the rotor position and speed without using the electromotive force (EMF) integration and initial rotor position. The paper investigates and validates the ride-through performance of this proposed system during asymmetric power grid-voltage sags, transition from grid connected to stand alone and vice versa and voltage harmonics compensation. While some of the aforementioned issues have been treated rather individually in previous conference publications of the authors, the present paper integrates them into a comprehensive control system of PMSG. [ABSTRACT FROM AUTHOR]

In this paper, a novel technique to balance the voltage of the two split dc capacitors of a 3-Level neutral-point-clamped inverter using triangular carrier pulse width modulation is presented. This technique, suitable for reactive power compensation and for inverters operating with a relatively low switching frequency, consists in adding a square wave at six times the output frequency. Subsequently, this paper presents a comparison with two already known strategies in which a sinusoidal waveform at two and six times the output frequency are injected. The current contribution to the midpoint of the dc bus is then analyzed for different modulation indexes and operating conditions. Based on this analysis, a small-signal averaged model, suitable for control design purposes is presented. Finally, simulation and experimental results on a 690-Vac, 120-kVA test bench that validate the theory are shown. [ABSTRACT FROM AUTHOR]

Various applications, like in underground mines and oil and gas industries, require remote operation of vector-controlled medium-voltage variable speed drives via a long motor feeder. The use of voltage source inverters in such cases leads to motor overvoltage and harmonic quality problems. The current source inverter (CSI) is ideally matched to these applications because of its motor-friendly voltage output. Speed sensorless operation is mandatory due to the long motor feeder. Although the model reference adaptive system (MRAS) is a powerful and proven speed estimation tool, its implementation in long motor feeder drives faces many challenges. Among them, and addressed in this paper, are inherent dc offset in its stator model, the need for actual motor voltage and current values, and oscillations in the estimated speed due to errors in the motor current measurement signals. In this paper, a sensorless CSI vector-controlled drive, suitable for long motor feeder applications, is studied. Improved speed estimation is achieved by proposing 1) a modified dc-offset eliminator for an MRAS speed estimation and 2) a compensation technique for motor current's measurement errors. Intensive experimental results, for a low-voltage scaled model, along with simulations validate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

Indirect matrix converter (IMC) is an alternative for ac/ac energy conversion, usually operated with a voltage stepped-down gain of only 0.866. For applications like distribution generation where voltage-boost functionality is required, the traditional style of operating the IMC is therefore not appropriate. Like most power converters, the operation of the IMC can surely be reversed to produce a boosted gain, but so far its relevant control principles have not been discussed. These challenges are now addressed in this paper with distributed generation suggested as a potential application. Simulation and experimental results for validating various performance aspects of the proposed control schemes can be found in a later section of this paper. [ABSTRACT FROM AUTHOR]

Multilevel inverters are receiving more attentions nowadays as one of preferred solutions for medium- and high-power applications. As one of the most popular hybrid multilevel inverter topologies, the five-level active-neutral-point-clamped inverter (5L-ANPC) combines the features of the conventional flying-capacitor type and neutral-point-clamped (NPC) type inverter and was commercially used for industrial applications. In order to further decrease the number of active switches, this paper proposes a seven-switch 5L-ANPC (7S-5L-ANPC) topology, which employs only seven active switches and two discrete diodes. The analysis has shown a lower current rating can be selected for the seventh switch under high power factor condition, which is verified by simulation results. The modulation strategy for 7S-5L-ANPC inverter is discussed. A 1 kVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method. [ABSTRACT FROM AUTHOR]

The inductor current ripple under hysteresis current control is sensitive to system as well as controller parameters, which often deviates from the desired band. Thus, a phase-locked-loop (PLL) is employed to regulate the switching frequency over the operating range. Digital platform drastically simplifies this using an all-digital PLL (ADPLL) and offers the controller-tuning flexibility for improved performance. However, the use of uniform voltage-sampling often leads to multilimit cycle instability. This paper proposes a mixed-signal hysteretic current controller (MSHCC) with the digital voltage-loop and the analog current-loop. A digital-to-analog converter is sufficient to generate time-multiplexed current references. This achieves robust stability and parameter-insensitive current ripple by sampling the error-voltage at the rising edge of the high-side gate signal. Stability analysis is carried out using discrete-time models. The proposed MSHCC can be configured to either of the peak, average, or valley current-mode techniques along with the flexibility to adjust the switching frequency using an ADPLL for real-time energy-optimization. The proposed scheme is implemented using an FPGA device and tested on a buck converter prototype. The MSHCC scheme can be extended to a multiphase buck converter. [ABSTRACT FROM AUTHOR]

This paper presents a robust model-based active damping control in natural frame for a three-phase voltage source inverter with LCL filter. The presence of the LCL filter complicates the design of the control scheme, particularly when system parameters deviation is considered. The proposed control method is addressed to overcome such difficulties and uses a modified converter model in a state observer. In this proposal, the converter model is modified by introducing a virtual damping resistor. Then, a Kalman filter makes use of this model to estimate the system state-space variables. Although the state estimates do not obviously match the real world system variables, they permit designing three-current sliding-mode controllers that provide the following features to the closed loop system: 1) robust and active damping capability like in the case of using a physical damping resistor; 2) robustness because the control specifications are met independently of variation in the system parameters; 3) noise immunity due to the application of the Kalman filter; and 4) power loss minimization because the system losses caused by the physical damping resistor are avoided. An interesting side effect of the proposed control scheme is that the sliding surfaces for each controller are independent. This decoupling property for the three controllers allows using a fixed switching frequency algorithm that ensures perfect current control. To complete the control scheme, a theoretical stability analysis is developed. Finally, selected experimental results validate the proposed control strategy and permit illustrating all its appealing features. [ABSTRACT FROM AUTHOR]

This paper presents a pulse width modulation strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15-kW motor drive prototype to validate the method effectiveness. Taking into account deadtime compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range. [ABSTRACT FROM AUTHOR]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

This paper investigates the problem of fluctuation of the neutral-point potential (NPP) in a three-level NPC inverter with a capacitor-voltage loop. The phase pulse width duty cycle disturbance pulse width modulation (PWM) method is proposed to suppress the NPP fluctuation efficiently. Based on the basic carrier-based phase-disposition PWM method, the average pulse neutral-point current model is established. Then, the frequency, amplitude, and equivalent initial phase of the NPP fluctuation are analyzed based on the current model. According to the alternating error of the dc-link capacitor voltages, a capacitor-voltage loop with a quasi-proportional resonant (PR) controller is presented. The control variable, which varies with the modulation index, phase current, load power factor, etc., can be obtained from the quasi-PR controller. Finally, an experimental three-level NPC inverter is described and the validity and feasibility of the proposed method are verified by experimental results. [ABSTRACT FROM AUTHOR]

Differential-mode buck-boost inverters have merits such as reduced switch number, ability to provide voltages higher or lower than the input voltage magnitude, improved efficiency, reduced cost and size, and increased power density, especially in low-power applications. There are five buck-boost inverters that can provide flexible output voltage without the need of a large electrolytic input side capacitor, which degrades the reliability of inverters. The continuous input current of these inverters is appropriate for maximum power point tracking operation in photovoltaic and fuel cells applications. Three of the five inverters can be isolated with high-frequency-link transformers where the common-mode leakage current can be mitigated. However, the performance and control of such converters have not been discussed in detail. In this paper, the five possible single-stage three-phase differential-mode buck-boost inverters with continuous input current are investigated and compared in terms of total losses, maximum ripple current, total harmonic distortion, and device and passive element ratings. In addition, the possible methods are presented for eliminating the input third-order harmonic current, resulting from the stored energy in the passive elements, as well as the output second-order harmonic currents. The ability for isolating the input and output sides of the inverters with a small–high frequency transformers is discussed. A changeable-terminal 2.5-kW bidirectional inverter is used to validate the design flexibility of the inverter topologies, when digital signal processor-controlled. [ABSTRACT FROM AUTHOR]

Three-phase inverters with an output LC filter are commonly used to provide sinusoidal voltages with low-harmonic distortion. Constraint on peak filter current is often desirable to protect the components from potential damage. In case of constraints, implicit and explicit model-predictive control (MPC) are some of the feasible controller options. The conventional implicit MPC requires a large number of computations, whereas explicit MPC cannot directly incorporate real-time changes in model parameters, while still being computationally expensive than some of the other control schemes, e.g., hysteresis, dead beat control, etc. In this paper, we propose a new approach to solve the optimization problem in implicit MPC that has a computational complexity approximately five times less than that of explicit MPC. We have been able to achieve lower computational requirements by exploiting the inverter model and the structure of constraints. [ABSTRACT FROM AUTHOR]

The paper presents an analysis on the output current ripple in zero common-mode voltage (ZCMV) PWM control of multilevel inverters. The modulation strategy for common-mode voltage (CMV) elimination in multilevel inverters is based on the “three zero common-mode vectors” principle. The space vector diagram, which consists of vectors of ZCMV, is fully explored by properly depicting the base voltage vectors and their corresponding active switching vectors. The switching patterns are limited to those of three switching states each of which is symmetrically distributed. Based on the PWM process simplified to that of a two-level inverter with three allowable switching states and the degree of freedom existing in the switching states arrangement, a novel carrier-based pulsewidth-modulated (PWM) method with optimized output current ripple is proposed. Compared to the existing PWM methods which utilize the same kind of switching patterns, the proposed PWM method has reduced considerably the rms current ripple and total harmonic distortion (THD) of the output current in a wide region of the modulation index. The effectiveness of the proposed method is validated by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

A family of isolated buck–boost dc/dc converter for wide input-voltage range is proposed in this paper, and the full-bridge (FB) boost converter, being one of the typical topologies, is analyzed. Due to the existence of the resonant inductor (including the leakage inductor), the FB-boost converter can only adopt the two-edge-modulation (TEM) scheme with the FB cell being leading-edge modulated and the boost cell being trailing-edge modulated to minimize the inductor current ripple over the input-voltage range, and a phase-shift-control-scheme-based TEM with the use of the market available controller IC such as UC3895 is proposed, which realizes phase-shifted control for the FB cell to achieve zero-voltage switching. In order to improve the reliability and efficiency of the FB-boost converter, a three-mode dual-frequency control scheme is proposed, in which the FB-boost converter operates in boost, FB-boost and FB modes in low, medium and high input voltage regions, respectively, and for which the expression of the inductor current ripple is derived in this paper. As the input voltage in the FB-boost mode is close to the output voltage, the inductor current ripple in this mode is much smaller than that in the other modes, and the switching frequency of the boost cell in this mode can be lowered to one-(2N+1)th of the preset switching frequency to reduce the switching loss, and hence, to improve the efficiency. A 250–500 V input, 360 V output, and 6 kW rated power prototype is fabricated to verify the effectiveness of the design and control method. The average efficiency over the input-voltage range is 96.5%, and the highest efficiency attained is 97.2%. [ABSTRACT FROM AUTHOR]

This paper introduces a new concept of optimal utilization of a unified power quality conditioner (UPQC). The series inverter of UPQC is controlled to perform simultaneous 1) voltage sag/swell compensation and 2) load reactive power sharing with the shunt inverter. The active power control approach is used to compensate voltage sag/swell and is integrated with theory of power angle control (PAC) of UPQC to coordinate the load reactive power between the two inverters. Since the series inverter simultaneously delivers active and reactive powers, this concept is named as UPQC-S (S for complex power). A detailed mathematical analysis, to extend the PAC approach for UPQC-S, is presented in this paper. MATLAB/SIMULINK-based simulation results are discussed to support the developed concept. Finally, the proposed concept is validated with a digital signal processor-based experimental study. [ABSTRACT FROM AUTHOR]

In many modern energy conversion systems, a dc voltage, which is provided from a sustainable energy source or energy storage device, must be boosted and converted to an ac voltage with a fixed amplitude and frequency. In this paper, a switching pattern based on the concept of the conventional space-vector pulsewidth-modulated (SVPWM) technique is developed for single-stage, three-phase boost-inverters using the topology of current-source inverters. The six main switching states, and two zeros, with three switches conducting at any given instant in conventional SVPWM techniques are modified herein into three-charging states and six discharging states with only two switches conducting at any given instant. The charging states are necessary in order to boost the dc input voltage. The developed switching pattern was experimentally verified through a laboratory-scaled three-phase 500-W boost inverter and the results are presented in this paper. [ABSTRACT FROM AUTHOR]

The high penetration level of power electronics interfaced distributed generation (DG) systems creates great ancillary services potential through the DG interfacing converters, such as the grid unbalanced voltage compensation. However, the unbalanced voltage compensation may cause adverse effects on the DGs' operation, such as output active power oscillation and dc-link voltage variations. Moreover, since the compensation is realized through the available rating of DGs' interfacing converters, it is equally important to consider the effectiveness of control strategy for unbalanced voltage compensation. Considering these challenging issues, two grid unbalanced voltage compensation strategies for three-phase power electronics interfaced DG systems are proposed in this paper. Especially, the first control strategy aims at minimizing the DG's active power oscillation and reducing the adverse effects of unbalanced voltage compensation on DG's operation. The second control strategy focuses on the effectiveness of unbalanced voltage compensation by controlling DG's negative sequence current to be inphase with the grid negative sequence current. Performances of the two proposed control strategies under different grid conditions and DG operating conditions are studied, and recommendations for appropriate control strategy utilization under various conditions are provided. Finally, validity of the proposed strategies is verified by both simulations and experimental results. [ABSTRACT FROM AUTHOR]

When the faulty cells of a nonregenerative cascaded H-bridge inverter are bypassed, it is necessary to inject a zero-sequence voltage into the inverter phase voltages so as to achieve the maximum balanced line-to-line voltage. However, the injected zero-sequence voltage may lead to a back flow of real power (BFRP) in at least one phase so that the dc voltage will rise to an intolerable level. To solve the problem, this paper proposes a new method of generating zero-sequence voltages. This method can not only maximize the available output voltage but also suppress the BFRP effectively. The zero-sequence voltage is always limited to an appropriate range to achieve the maximum output voltage through linear modulation. Closed-loop control is used to minimize the fundamental component of the zero-sequence voltage so that the power is less likely to flow back. Compared with the conventional methods, the proposed method allows the inverter to drive a load with a lower power factor not inducing BFRP or degrading the output voltage capability. As a result, the probability of overvoltage on the dc side is reduced. The experimental results show that the proposed method is effective and feasible. [ABSTRACT FROM AUTHOR]

When faced with distorted grid voltage, more harmonics will appear in the output currents of the grid-connected inverters. The grid-voltage feedforward strategy, as the most direct solution to compensate the harmonics, however, is seriously affected by the errors in the grid-voltage feedforward loop, such as delays. This issue is more significant for high-power inverters, where the switching frequency is relatively low (< 5 kHz), and the grid-interface inductance is small (< 0.5 mH). The errors mainly include the signal distortion caused by the conditioning circuits, the control delay of the digital controller, and the zero-order hold (ZOH) characteristic of pulse width modulation (PWM). In this paper, several improvements have been made to reduce the signal distortion and compensate the delays. A second-order Butterworth low-pass filter in the conditioning circuit is carefully designed with the maximum flat magnitude response and the almost linear phase response to avoid distorting the measured grid voltage. Furthermore, based on the conventional repetitive predictor, an open-loop simplified repetitive predictor is proposed to compensate the delays in the grid-voltage feedforward loop. Three predictive steps are achieved by the open-loop simplified repetitive predictor to compensate the delays: one step for the delay caused by the conditioning circuit, the second step for the control delay of the digital controller, and the third step for the ZOH characteristic of PWM. The effectiveness of the improved grid-voltage feedforward strategy are experimentally validated on a 250-kVA solar power generation system, where the current harmonics are effectively attenuated. In addition, the inverter starting current is suppressed. [ABSTRACT FROM AUTHOR]

Integration of distributed generation (DG) such as photovoltaics (PV) represents a challenge for the traditional operation of distribution power systems. As the installed power of DGs grows, grid codes are being modified to involve DGs in the provision of ancillary services. This includes the ability to ride-through large disturbances. In this paper, the behavior of a single-stage PV system under unbalanced voltage conditions is studied, and a fault ride-through control scheme is proposed which is able to support the grid through the injection of reactive power. Furthermore, adjustable power quality is enabled as a tradeoff between power ripple and current harmonics. The control scheme makes use of a current controller based on the space vector Fourier transform concept. No rotational transformation is required, and zero steady-state error is ensured when tracking distorted current references. The controller was tested in detailed PSCAD/EMTDC computer simulations, and implemented in a real grid-connected PV system to demonstrate its performance under unbalanced voltage conditions. [ABSTRACT FROM PUBLISHER]

Under voltage sags, grid-tied photovoltaic inverters should remain connected to the grid according to low-voltage ride-through requirements. During such perturbations, it is interesting to exploit completely the distributed power provisions to contribute to the stability and reliability of the grid. In this sense, this paper proposes a low-voltage ride-through control strategy that maximizes the inverter power capability by injecting the maximum-rated current during the sag. To achieve this objective, two possible active power situations have been considered, i.e., high- and low-power production scenarios. In the first case, if the source is unable to deliver the whole generated power to the grid, the controller applies active power curtailment to guarantee that the maximum rated current is not surpassed. In the second case, the maximum allowed current is not reached, thus, the control strategy determined the amount of reactive power that can be injected up to reach it. The control objective can be fulfilled by means of a flexible current injection strategy that combines a proper balance between positive- and negative-current sequences, which limits the inverter output current to the maximum rated value and avoid active power oscillations. Selected experimental and simulation results are reported in order to validate the effectiveness of the proposed control strategy. [ABSTRACT FROM PUBLISHER]

The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

In single-phase photovoltaic (PV) system, there is double-frequency power mismatch existed between the dc input and ac output. The double-frequency ripple (DFR) energy needs to be buffered by passive network. Otherwise, the ripple energy will flow into the input side and adversely affect the PV energy harvest. In a conventional PV system, electrolytic capacitors are usually used for this purpose due to their high capacitance. However, electrolytic capacitors are considered to be one of the most failure prone components in a PV inverter. In this paper, a capacitance reduction control strategy is proposed to buffer the DFR energy in single-phase Z-source/quasi-Z-source inverter applications. Without using any extra hardware components, the proposed control strategy can significantly reduce the capacitance requirement and achieve low input voltage DFR. Consequently, highly reliable film capacitors can be used. The increased switching device voltage stress and power loss due to the proposed control strategy will also be discussed. A 1-kW quasi-Z-source PV inverter using gallium nitride (GaN) devices is built in the lab. Experimental results are provided to verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper investigates a dynamic voltage restorer (DVR) composed of two conventional three-phase inverters series cascaded through an open-end winding (OEW) transformer, denominated here DVR-OEW. The DVR-OEW operating with either equal or different dc-link voltages is examined. The proposed topology aims to regulate the voltage at the load side in the case of voltage sags/swells, distortion, or unbalance at the grid voltage. A suitable control strategy is developed, including space-vector analysis, level-shifted PWM and its equivalent optimized single-carrier PWM, as well as the operating principles and characteristics of the DVR. Comparisons among the DVR-OEW and conventional configurations, including a neutral-point clamped converter-based DVR, are furnished. The main advantages of the DVR-OEW compared to the conventional topologies lie on: 1) reduced harmonic distortion, 2) reduced converter losses, and 3) reduced voltage rating of the power switches. Simulated and experimental results are presented to validate the theoretical studies. [ABSTRACT FROM AUTHOR]

Single-phase inverters must include an energy storage device, typically a high-voltage bus capacitor, to match the inverter constant input power to its pulsating output power. Because of its increased cost, the size of this bus capacitor must be minimized. However, when the bus capacitor is small, the bus voltage includes a high ripple at the ac line second harmonic frequency, which causes harmonic distortion. The bus voltage controller must filter this ripple, while regulating the bus voltage efficiently during transients, and must therefore balance a tradeoff between two conflicting constraints, low-harmonic distortion and high bandwidth. This paper analyzes this tradeoff, and proposes a new control method for solving it without using addition hardware. Instead of reducing the distortion by lowering the loop gain, the new controller employs a digital FIR filter that samples the bus voltage at an integer multiple of the second harmonic frequency. The filter presents a notch that removes the second harmonic ripple, enabling a design that operates with zero distortion and high bandwidth simultaneously, and is suitable for inverters with small bus capacitors. The proposed controller is tested on a microinverter prototype with a 300-W photovoltaic panel and a 20-μF bus capacitor. [ABSTRACT FROM PUBLISHER]

Single-phase power conversion such as pulse width modulation rectifier, grid connected PV inverter system, static synchronous compensator all can be implemented by an H-bridge inverter and a large electrolytic dc capacitor to absorb the ripple power pulsating at twice the line frequency (2ω ripple power). This paper proposed a dc capacitor-less inverter for H-bridge with minimum voltage and current stress. By adding another phase leg to control an ac capacitor, the 2ω ripple power can be absorbed by the capacitor and theoretically 2ω ripples to the dc capacitor can be eliminated completely. The H-bridge and the addition phase leg can be analyzed together as an unbalanced three phase system. By adopting space-vector pulse width modulation control and choosing the optimum ac capacitance and the voltage reference, the voltage and current stress of the switches can be minimized to the same as the conventional H-bridge. The size of capacitor is reduced by ten times compared to the conventional H-bridge system. Simulation and experimental results are shown to prove the effectiveness of the proposed dc capacitor-less inverter and active power decoupling method. [ABSTRACT FROM AUTHOR]

Nowadays, use of multilevel inverters in high-power applications clearly can be seen. High quality and lower distortion of the output voltage and low blocking voltage of semiconductor switches are being presented as the major privileges of the multilevel inverter compared to the traditional voltage source inverter. In this paper, a new topology of multilevel inverter is proposed as fundamental block. The proposed topology is generalized using series connection of the fundamental blocks. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes. A great perfection in voltage levels number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter, a detailed study of losses and peak inverse voltage (PIV) of the proposed multilevel inverter is given. Also, in continuation, a comparison between the proposed topology and the traditional one and a recently developed topology is carried out. Finally, a computer simulation using MATLAB/Simulink is presented and a laboratory prototype implementation verifies the results. [ABSTRACT FROM AUTHOR]