Search

Enhancement of dc bus voltage utilization for a five-level inverter with single dc source and capacitor-fed H-bridge (CHB) units is investigated in this paper. A carrier-based modulation technique is used for boosting the dc bus utilization, which is established by providing detailed mathematical analysis. The five-level inverter used here is realized by cascading a CHB unit to each phase of a three-level neutral point clamped inverter. The increase in dc bus voltage utilization owes to the pole voltage redundancies offered by CHB units. The floating capacitors of H-bridge units are balanced within a quarter fundamental cycle using the switching state redundancies of pole voltage levels. The aforementioned modulation technique allows the inverter to enhance the dc bus utilization from 0.577 $\text{V}_{\text{dc}}$ to 0.63 $\text{V}_{\text{dc}}$ under unity power factor. This enhancement is obtained in the linear modulation range without increasing the dc bus voltage, and thus, the inverter can operate without the presence of low-order harmonics in its phase voltages. The strength of this paper lies in its detailed mathematical analysis for finding out the limiting modulation index and power factor condition in the light of floating capacitor voltage balancing issue. Simulation as well as experimental verification of the modulation scheme is carried out on an induction motor drive under various operating conditions. It is shown that this carrier-based modulation technique is suitable for any single source inverter topology with one CHB unit per phase. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents the digital implementation of a boundary controller with unipolar switching characteristic for single-phase voltage source full-bridge inverters. This paper expands the application of a second-order switching surface-based control method to unipolar switching of single-phase voltage source inverters (VSIs) using a finite-state machine. The finite-state machine has been formulated considering four different states of the inverter; positive,zero1, negative, andzero2. The second-order boundary control governs the current state of the system and provides proper switching action to keep the system within the desired reference. The control law is implemented digitally in F28m35x digital control card. A full-bridge inverter topology is used to achieve the three-level voltage switching. Various simulations and experiments were performed in a 550 VA, 120 V, 60 Hz VSI with a digitally implemented controller to verify the theoretical predictions. A high-quality voltage output was obtained for various loading conditions. The transient performance of the controller was investigated using a reference and load changes. A comparison of the implementation was made with the existing classical controllers to verify the fast-dynamic response of the system. [ABSTRACT FROM AUTHOR]

This paper introduces a new bidirectional single-phase inverter topology. The proposed topology has three ports: a dc port, an ac port, and a ripple port. The ac and dc ports are bidirectional to support rectifier or inverter operation. A small inductor, which is of alternating current, exchanges power between different ports of the single-phase system. The proposed topology is capable of accomplishing voltage step-up or step-down, suppressing the ripple power, and performing inversion or rectification operation in one stage of power conversion. The proposed configuration offers an active decoupling function, which not only eliminates the double-frequency ripple power at the dc port but also achieves minimum capacitance requirements to minimize the size of the decoupling capacitor. This facilitates the use of a very small thin-film capacitor, which offers a much longer life-cycle and higher reliability compared with a bulky electrolytic capacitor. A control approach is also developed to regulate the dc-port and ac-port currents and manage the ripple power through proper distribution of power between each port. Moreover, a very small capacitor can be placed in parallel with the inductor to reinforce the proposed configuration with soft-switching operation, which enhances the overall efficiency and minimizes the voltage stress over the semiconductor devices. This converter is capable of accommodating an arbitrary number of dc or single-phase ac sources and/or loads configuring a multiple-input multiple-output inverter without introducing any additional passive elements or sacrificing the performance of the inverter. The primary focus of this paper is dc-to-ac conversion mode of operation, in spite of the fact that it can easily be configured to serve as a rectifier. Experimental and simulation results are presented to validate the operation of the proposed topology and its control strategy. [ABSTRACT FROM AUTHOR]

This paper presents an inverter topology named the multi-source inverter that aims to connect several independent DC sources to the same AC output using a single stage of conversion. This power converter has been developed for applications, such as electrified powertrains. Compared to the conventional hybrid powertrains that use a DC/DC converter to provide an adaptable voltage to the load, the multi-source inverter can drive a traction motor from variable DC voltages without the use of an additional power converter. Hence, the high power DC/DC converter can be dissociated from the traction mode and its use will be restricted to the engine $^{\prime }$ s start-up and regenerative braking, allowing a significant reduction of its power rating from tens of kWatts to a few kWatts. The overall efficiency of the electrified traction drive can also be improved due to the single conversion stage between the battery and the motor. In this paper, the multi-source inverter topology is introduced and its different operating modes are determined through the study of the inverter circuit. Closed-loop control simulations and experiments with a scaled-down prototype and an induction motor were performed to validate the effectiveness of the proposed topology and concept. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

This paper presents a generalized power-decoupling control scheme using a multiport isolated bidirectional converter for a multilevel inverter, which has multiple dc links inside. In the proposed method, a single power-decoupling capacitor is needed for all the dc links in the multilevel inverter cell. First, a prototype of the power-decoupling concept of individual H-bridge cells in the multilevel inverter is proposed, using a separate power-decoupling circuit. Then, a more advanced one-step power-decoupling method is proposed. The lifetime and reliability of the multilevel inverter is improved as film capacitors replace the large capacitance electrolyte capacitors. A multi-input ports/single output voltage-fed dual half-bridge converter (MDHB) is used for the power-decoupling circuit. A steady-state analysis for the peak and root mean square of the MDHB current is carried out for the loss breakdown. The currents are functions of the switching frequency, phase shift, leakage inductance, turn ratio, and output voltage, which make the multiport transformer design complex. A design methodology is proposed, which takes into account the design of the copper and core losses as functions of the switching frequency and number of turns. Furthermore, a special winding method for the input port is illustrated to obtain identical leakage inductances for the uniform current distribution in the multiport transformer. The proposed MDHB employs a current-sensorless power-decoupling control that contributes to the spontaneous ripple rejection of all the dc links without individual link current information, as well as to the cost and size reduction. Hence, the ripple-rejection controller is independent of the control configuration of the multilevel inverter, and also available for universal applications of various inverter topologies. Since the primary-input ports of MDHB share a single magnetic core for interfacing the ripple power to the unified secondary ripple capacitor, the controller design becomes difficult in considering the dynamic interaction among the ports, along with the average-voltage control loop design. In this paper, the dynamic analysis and controller design procedure of the circuit is also presented. The power decoupling is achieved even when the ripple frequency is other than the double frequency of the inverter output, since the single-pole transfer function of the small-signal model of the MDHB allows sufficient phase margin, along with high bandwidth. The proposed power-decoupling method for the multilevel inverter is validated with the help of simulation and 1.2-kW hardware prototype experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new type dc/ac inverter named: hybrid-coupling grid-connected inverter (HGCI) for photovoltaic active power generation with power quality conditioning, which consists of a full-bridge three-phase dc/ac inverter coupling to the power grid in series with a thyristor-controlled LC filter. Compared with the conventional inductive-coupling grid-connected inverter (IGCI) and capacitive-coupling grid-connected inverter (CGCI), the proposed HGCI has distinct characteristics of wide operational range and low dc-link operating voltage. Based on these prominent characteristics, the system cost and operational cost can be reduced. Moreover, it can transfer the active power and compensate reactive power, unbalanced power, and harmonic power simultaneously. In this paper, the analysis of the structure, parameter design, and control method of the HGCI is proposed and presented. Finally, simulation and experimental results are provided to verify the effectiveness and performance of the proposed HGCI in comparison with the IGCI and CGCI. [ABSTRACT FROM AUTHOR]

Fast-switching power converters are a key enabling technology for the more electric aircraft (MEA), but the generated electromagnetic interference (EMI) poses significant challenges to the electrification effort. To meet the stringent aerospace EMI standards, passive filters are commonly employed, despite the weight and size constraints imposed by the MEA. Alternatively, the EMI source, i.e., the high dv\text/ dt and di\text/ dt slew rates, can be addressed through waveform-shaping techniques. For example, while most soft-switching converters can reduce switching loss, they do so by switching the semiconductor devices in a slower and smoother manner, resulting in the attenuation of high-frequency harmonics. This paper examines the auxiliary commutated pole inverter (ACPI) topology, and its first contribution is the attenuation of the high-frequency content of its EMI source, that is, the output voltage, in a predictable manner, through the active control of the resonant circuit. This is achieved by first, discussing the time-domain characteristics of trapezoidal and S-shaped pulse-trains that lead to attenuated high-frequency harmonic content, and second, by analyzing the equivalent LC circuit of the ACPI. The design of the inverter is then focused on the active control of the resonant parameters, for a predetermined and enhanced output voltage high-frequency response. The second contribution of this paper is the comparison of the EMI performance of hard switching and of three soft-switching modes, fixed-timing control, variable-timing control, and capacitive turn-offs, and how this informs important metrics such as power efficiency, current stress, and implementation complexity. Finally, the third contribution is on the trade-offs that arise when the primary design goal is enhanced EMI performance as opposed to switching loss reduction. A 5-kW, 3-phase ACPI prototype is used for validating the high-frequency content attenuation at source. It is shown that the ACPI can achieve a 37 dB harmonic attenuation of its output voltage at 4 MHz, compared to a hard-switched inverter. [ABSTRACT FROM AUTHOR]

To support the development of high-frequency ac microgrids in terms of compact design, high-voltage gain and low total harmonic distortion (THD), a buck–boost dual-leg-integrated step-up inverter is proposed in this paper. The inverter is formed by integrating a buck–boost converter into a conventional single-phase full-bridge inverter by sharing the upper switch and the body diode of the lower switch in both bridge-legs. Consequently, the component count is significantly reduced over the step-up inverter counterparts. In addition, to address the drawbacks of hybrid modulation methods adopted by existing dual-leg-integrated inverters, such as double-variable control, and high THD of output voltage/current at high input voltage and heavy load conditions, unipolar frequency doubling sinusoidal pulse width modulation scheme is adopted in this inverter. As a result, the modulation ratio M becomes the only control variable to regulate the output voltage/current and the control is simplified. The THD of the proposed inverter output can remain low throughout the entire input voltage range and load power range. This paper presents the topology derivation procedure, operation principle, and steady-state characteristics of the proposed inverter. To validate the effectiveness of theory, experimental results of a 400 W hardware prototype, where the output voltage frequency is at 500 Hz, are reported. [ABSTRACT FROM PUBLISHER]

This paper presents the tradeoff study of heat sink and output filter volume of a GaN HEMT based single-phase inverter. The selected topology is three-level active neutral point clamped (ANPC) inverter, and the main aim is to explore the benefits of the GaN HEMTs at 600 V blocking class on the system level efficiency, and power density under the wide range of operating conditions. The paper starts by introducing the inverter topology, selected pulse width modulation scheme and followed by the device features, static, and dynamic characterization and continues with presenting and discussing the results of extensive experimental and analytical characterization. After this, the impact of GaN HEMTs on inverter volume is discussed in terms of heat sink and output filter volume analysis under different switching frequency and heat sink temperature conditions. The calculation of heat sink volume and single stage LC output filter volume are presented with respect to experimental results of the single phase prototype. The findings from static, dynamic characterization, and single phase prototype results clearly show that GaN HEMT has excellent switching performance under wide load current and heat sink temperature conditions. The high performance of the inverter leads to reduction of the combined total volume, including output filter and heat sink volume. [ABSTRACT FROM AUTHOR]

This paper analyzes the benefits of the active damping applied to transformerless three-phase grid-connected photovoltaic (PV) inverters using modified LCL (MLCL) filter for leakage current reduction. In comparison with passive damping techniques, the active damping can reduce the MLCL filter resonance peaks, improving the dynamic performance of the control system without addition of power losses. Besides these classical advantages, this paper demonstrates that the active damping also contributes for PV leakage current reduction, preserving the high-frequency attenuation of the MLCL filter. Additionally, an active damping for the inverter common-mode circuit is also proposed, reducing the low-frequency leakage current caused by the common-mode signal used to extend the inverter modulation index. Experimental results are given to demonstrate the leakage current reduction and the grid current control for a 10 kW PV inverter. [ABSTRACT FROM PUBLISHER]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

A novel control strategy for single-phase current-source inverters connected to an ac grid is proposed in this paper. The control strategy aims to inject maximum power to the grid under transient and steady-state conditions by the tracking of sinusoidal references. This paper presents the modeling and the design of the control strategy based on the exact linearization of the inverter model. Results are obtained by computational simulation and validated experimentally. By using error performance indexes in the analysis of the results, it is demonstrated that the proposed controllers achieve correct tracking of the sinusoidal reference while keeping a low switching frequency, which helps to minimize the commutation losses. [ABSTRACT FROM PUBLISHER]

This paper presents a reduced component count five-level inverter topology based on the stacked cell approach to multilevel inverters. The proposed topology utilizes the fundamental properties of three-phase voltages to reduce the number of switches and flying capacitors to cut size, weight and costs while facilitating higher reliability, simpler wiring and lesser electromagnetic interference. The operational aspects of the topology such as circuit structure, modulation and capacitor balancing are explained, followed by an account of device stresses and reliability. A discussion of certain additional features such as fault tolerant operation, loss steering and common-mode elimination addresses the usefulness of the topology in practical situations. A comparison of the proposed topology with existing methods in terms of several parameters is then used to highlight its merits and features. Finally, experimental results obtained using an induction motor drive incorporating the topology are given, so as to validate the feasibility of the proposed approach. [ABSTRACT FROM AUTHOR]

In order to provide high and extendable power levels for inductive power transfer (IPT) system, a parallel multi-inverter system based on modular inverter is presented. Various power requirements can be implemented by an adjustment of the number of paralleled inverters, which provides a high modularity. A master−slave scheme is employed for the switching-driver signals of parallel inverters, where one acts as a leader while others act as followers. Despite the master−slave scheme, the proposed circuit topology has natural robustness because of the equality in terms of the hardware configuration of each modular inverter. For proper parameters, the output phase (current lagging corresponding voltage) of an inverter is lower than the average of output phase of all inverters, when its output voltage lags behind others, and vice versa. Based on this approach, PI controllers are designed to implement phase synchronization for output voltages of all inverters. An IPT prototype supplied by the proposed parallel multi-inverter with three inverters was designed, built, and tested. Experiments show that the proposed parallel multi-inverter system has not only good circulating current suppression capacity but also excellent performance of phase synchronization. The maximum dc−dc efficiency was 94% at a 35.1 kW receiving power. This paper is accompanied by a Matlab/Simulink file demonstrating phase synchronization control. [ABSTRACT FROM AUTHOR]

There have been several advanced topologies proposed by the community for micro-inverter applications. However, many such applications suffer from unwanted second-order harmonic current ripple at dc input. Moreover, in the absence of suitable passive filter or ripple compensator, the second-order harmonics ripple may propagate into the dc source. This results in several problems to the system, related to system efficiency, life, cost, size, reliability, and stability. This paper proposes an adaptive sliding-mode controller to shape the output impedance of the boost-circuit of quasi-switched boost inverter such that the propagation of the ripple from dc link to the dc-input source is resisted. The quasi-switched boost inverter is one of the advanced and suitable topologies for the micro-inverter applications. The adaptive nature of the proposed controller improves the transient performance of the system at the line–load transients unlike some existing solutions, which affects dynamics adversely to achieve ripple mitigation objective. The controller ensures voltage regulation within ${5\%}$ at dc link. The proposed control technique is verified using a lab-prototype of 500 W quasi-switched boost inverter. [ABSTRACT FROM AUTHOR]

In this paper, a technique of variable-turns-ratio high-frequency link inverter is proposed to provide a simple method to achieve multi-level outputs for the isolated single-stage high-frequency link inverters. By dynamically adjusting the turns ratio of transformer, five-level (±2, ±1, and 0) outputs can be achieved to improve the current quality. The single transformer, compared with the existing two-level high-frequency link inverter, is employed in the structure and only a few auxiliary devices are added, where the added circuit operates at low frequency and the power density is refined. Based on this technique, the single-stage active clamped forward grid-connected inverter with variable turns ratio is taken as an example to better illustrate the analysis process and a 1000-W prototype is designed and established to evaluate the output performance. The conducted simulation results and prototype tests verify the feasibility of the proposed single-stage variable-turns-ratio high-frequency link grid-connected inverter. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Increasing demands for power supplies have contributed to the population of high-frequency ac (HFAC) power distribution system (PDS), and in order to increase the power capacity, multilevel inverters (MLIs) frequently serving as the high-frequency (HF) source-stage have obtained a prominent development. Existing MLIs commonly use more than one voltage source or a great number of power devices to enlarge the level numbers, and HF modulation (HFM) methods are usually adopted to decrease the total harmonic distortion (THD). All of these have increased the complexity and decreased the efficiency for the conversion from dc to HF ac. In this paper, a nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS. It makes full use of the conversion of series and parallel connections of one voltage source and two capacitors to realize nine output levels, thus lower THD can be obtained without HFM methods. The voltage stress on power devices is relatively relieved, which has broadened its range of applications as well. Moreover, the proposed nine-level inverter is equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified. The circuit structure, modulation method, capacitor calculation, loss analysis, and performance comparisons are presented in this paper, and all the superior performances of the proposed nine-level inverter are verified by simulation and experimental prototypes with rated output power of 200 W. The accordance of theoretical analysis, simulation, and experimental results confirms the feasibility of proposed nine-level inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-space vector control scheme for the open-end winding permanent magnet synchronous motor (OEW-PMSM) drive fed by the dual inverter with a single dc supply. Potential zero-sequence current in the open-end winding drive system has to be considered since it causes circulating current in the winding and leads to high current stress of power semiconductor devices and high losses. Zero-sequence current in open-end winding ac motor drives is usually caused by the zero-sequence voltage, and therefore switching combinations which do not produce zero-sequence voltage are used to synthesize the reference voltage in existing methods. But even so, the zero-sequence voltage can also be produced by the dead time of the inverter. In order to suppress zero-sequence current in the OEW-PMSM drive, a dual-space vector control scheme is proposed and a novel dual-inverter space vector pulse width modulation (PWM) with the zero-sequence voltage reference is employed to regulate system zero-sequence voltage in this paper. Compared with existing dual inverter PWM strategies, the novel algorithm build a regulation mechanism for the zero-sequence voltage. The proposed method is compared with the conventional vector control by simulations and experiments, and the results shown that the proposed scheme can suppress zero-sequence current effectively. [ABSTRACT FROM AUTHOR]

Impedance-source networks are an increasingly popular solution in power converter applications, especially in single-stage buck–boost power conversion to avoid additional front-end dc–dc power converters. In the survey papers published, no analytical comparisons of different topologies have been described, which makes it difficult to choose the best option. Thus, the aim of this paper is to present a comprehensive analytical comparison of the impedance-source-based buck–boost inverters in terms of passive component count and semiconductor stress. Based on the waveform of the input current, i.e., with or without a transformer, and with or without inductor coupling, the impedance-source converters are classified. The main criterion in our comprehensive comparison is the energy stored in the passive elements, which is considered both under constant and predefined high frequency current ripple in the inductors and the voltage ripple across the capacitors. Two-level and multilevel solutions are described. The conclusions provide a “one-stop” information source and a selection guide of impedance-source-based buck–boost inverters for different applications. [ABSTRACT FROM PUBLISHER]

In several electrical dc–ac power conversions, the ac output voltage is higher than the input voltage. If a voltage-source inverter (VSI) is used, then an additional dc–dc boosting stage is required to overcome the step-down VSI limitations. Recently, several impedance source converters are gaining higher attentions [1], [2], as they are able to provide buck-boost capability in a single conversion stage. This paper proposes the merging of the boost stage and the VSI stage in a single stage dc–ac power conversion, denoted as split-source inverter (SSI). The proposed topology requires the same number of active switches of the VSI, three additional diodes, and the same eight states of a conventional space-vector modulation. It also shows some merits compared to Z-source inverters, especially in terms of reduced switch voltage stress for voltage gains higher than 1.15. This paper presents the analysis of the SSI and compares different modulation schemes. Moreover, it presents a modified modulation scheme to eliminate the low frequency ripple in the input current and the voltage across the inverter bridge. The proposed analysis has been verified by simulation and experimental results on a 2.0-kW prototype. [ABSTRACT FROM PUBLISHER]

Pulse-width-modulated (PWM) converters have been widely applied for power processing, and they are typically the stems of other types of converters, such as quasi-resonant, Z-source, and switched-inductor hybrid converters. Development of PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM converters include buck, boost, buck–boost, Ćuk, single ended primary inductive converter (SEPIC), zeta, Z-source, quasi-Z source, etc. Many attempts have been proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting, and inverse operation of PWM converters. The PWM converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), therefore can be synthesized systematically according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridge transfer gains to converter topologies and provide readers a comprehensive understanding of PWM-converter evolution from the original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and zeta converters all with the same transfer gain of $D/(1 - D)$ are proved to be equivalent to the buck–boost converter with an extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are developed. [ABSTRACT FROM AUTHOR]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, a new hybrid modulation fault-tolerant control of an open-end winding linear vernier permanent-magnet (OEW-LVPM) motor is proposed. By using a floating capacitor inverter, the proposed OEW-LVPM motor drive can continue operation under open-circuit fault condition. The OEW-LVPM motor fed by dual-inverter system consists of two inverters, which are connected to both ends of the motor windings, including a dc power named as main inverter (MI) and a floating capacitor called as capacitor inverter (CI). When one switch is broken in the CI, the CI topology will be restructured to a three-phase four-switch inverter. Then, an improved six-step modulation is investigated in the MI to reduce the switching frequency, while the conventional modulation is applied in the CI. Thus, the MI can provide all the active power, and the CI is only used to supply the reactive power. The proposed fault-tolerant control method is simulated and the experiments with the OEW-LVPM motor drive are also accomplished to verify the feasibility. [ABSTRACT FROM AUTHOR]

Transformerless photovoltaic (PV) grid-connected inverters have become more and more popular in distributed PV power generation systems due to the advantages on high efficiency, low cost, and small size. However, common-mode (CM) current in the transformerless PV inverters can result in serious electromagnetic interference and insecurity, which will further reduce the reliability of the PV inverter systems. In this paper, an improved H5 topology, namely H5-D topology, is proposed, in which a clamping diode is added on the basis of H5 topology to eliminate the CM voltage fluctuation in H5 topology. Further, the PSIM simulation results of the H5-D topology and H5 topology are given and compared, especially, the performance of H5-D topology for CM current suppression is presented and analyzed concretely. Finally, the experimental prototypes of the H5-D topology and H5 topology are built and tested, and the experimental results validate the advantages of the H5-D topology. The proposed H5-D topology provides a new practical topology for distributed PV grid-connected power generation systems. [ABSTRACT FROM AUTHOR]

Cascaded multilevel inverter (CMI) is one of the most popular multilevel inverter topologies. This topology is synthesized with some series-connected identical H-bridge cells. CMI requires several isolated dc sources which brings about some difficulties when dealing with this type of inverter. This paper addresses the problem by proposing a switched-capacitor (SC)-based CMI. The proposed topology, which is referred to as switched-capacitor single-source CMI (SCSS-CMI), makes use of some capacitors instead of the dc sources. Hence, it requires only one dc source to charge the employed capacitors. Usually, the capacitor charging process in a SC cell is companied by some current spikes which extremely harm the charging switch and the capacitor. The capacitors in SCSS-CMI are charged through a simple auxiliary circuit which eradicates the mentioned current spikes and provides zero-current switching condition for the charging switch. A computer-aid simulated model along with a laboratory-built prototype is adopted to assess the performances of SCSS-CMI, under different conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

Model predictive control (MPC) for modular multilevel converter (MMC) systems has drawn attention among researchers in recent years due to its straightforward implementation, ability to control multiple objectives in a single cost function, and excellent dynamic response. Even though MPC seems promising for the MMC, it suffers from an excessive increase in computational complexity when the number of submodules (SMs) per arm (N) is increased. The computational load can be reduced by decoupling the SM capacitor voltage control from the cost function and balancing them in an external voltage sorting algorithm. In this paper, a further reduction of computations in the MPC is achieved by the preselection of control options that can satisfy the control objectives in the next sampling time. The preselection algorithm generates a greatly reduced number of control options to be computed by a straightforward MPC loop at each sampling time. In addition, the MPC together with the preselection algorithm can generate $2N+ 1$ output voltage levels in the MMC while maintaining a low $dv/ dt$ in the output voltage and suppressing the circulating currents in MMCs with considerable number of SMs. The steady-state and dynamic performance of the MMC operating with the proposed method is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

Reliability of power inverters is of dominant importance in various applications, including industrial, military, aerospace, and commercial applications. Therefore, developing fault tolerant (FT) power inverters is extremely needed from the viewpoints of system availability and avoiding harmful consequences. Tolerating various types of faults, preserving full output ratings after the fault, and being cost-effective represent the main challenges for most of existing FT solutions. In this paper, a new FT single-phase five-level inverter topology is proposed. The proposed topology can effectively tolerate both of single or multiple switches faults whether they are of open- or short-circuit fault types. Moreover, the proposed topology does not deteriorate system efficiency in postfault operation compared to the previously developed FT solutions. Evaluation of the effectiveness and robustness of the proposed topology is verified in both of simulation and experimental environments. Different case studies are investigated in order to cover various types and locations of switches’ faults. Moreover, comprehensive comparisons are provided to validate the superiority of the proposed topology over the previously addressed techniques. [ABSTRACT FROM AUTHOR]

A sawtooth carrier-based sinusoidal pulse width modulation (SC-SPWM) technique for asymmetrical six-phase two-level inverters is proposed in this paper, which could reduce both the peak-to-peak amplitude and the changing frequency of the common-mode voltage (CMV). The intersection-plotting method reveals that the mirror symmetrical sawtooth carriers for two three-phase groups can help optimize the distribution of overlapping areas, which is the CMV reduction mechanism of SC-SPWM. Additionally, the Fourier analysis is employed to quantitatively evaluate the modulation index and harmonic performance of SC-SPWM compared with the conventional SPWM and two phase-shifted SPWM methods. Also, further analysis demonstrates that dead time does not affect the reduction of CMV in a noticeable way. Finally, both simulation and experimental results coincide with the theoretical analysis that the proposed SC-SPWM shows the best performance in reducing the CMV amplitude and changing frequency among these four SPWM methods, though it leads to a higher phase current distortion. [ABSTRACT FROM AUTHOR]

Three-level converters typically feature low switching loss and small filter size. In order to realize a high-power-density design for three-level converters, SiC MOSFETs may be selected instead of using Si insulated-gate bipolar transistors. However, all-SiC-MOSFET-based converters suffer from extremely high total cost. In this paper, a SiC MOSFET and Si device hybrid active neutral-point-clamped (ANPC) converter is proposed. It consists of four Si active switches and only two SiC MOSFETs. Thus, it has lower total cost compared to the all-SiC-MOSFET-based ANPC converter. Furthermore, a dedicated modulation scheme is proposed to completely move all the switching events from Si devices to SiC MOSFETs by using redundant switching states. As a result, the switching losses are significantly reduced and extremely high efficiency is achieved. The proposed converter has fully utilized the low-switching-loss advantage of SiC MOSFETs and the low-cost advantage of Si devices, which shows significant superiority in high-end grid-connected inverter and rectifier applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources, and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

A quasi-Z-source inverter (qZSI) could achieve buck/boost conversion as well as dc to ac inversion in a single-stage topology, which reduces the structure cost when compared to a traditional two-stage inverter. Specifically, the buck/boost conversion was accomplished via shoot-through state which took place across all phase legs of the inverter. In this paper, instead of using traditional dual-loop-based proportional integral (PI)-P controller, a type 2 based closed-loop voltage controller with novel dc-link voltage reference algorithm was proposed to fulfill the dc-link voltage tracking control of a single-phase qZSI regardless of any loading conditions, without the need of inner inductor current loop. A dc–ac boost inverter with similar circuit parameters as a qZSI was used to verify the flexibility of the proposed controller. The dynamic and transient performances of the proposed controller were investigated to evaluate its superiority against the aforementioned conventional controller. The integrated proposed controller and qZSI topology was then employed in static synchronous compensator application to perform reactive power compensation at the point of common coupling. The effectiveness of the proposed approach was verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

Three-phase three-leg inverter is one of the most popular topologies for inverters. When short-circuit fault occurs, the inverter is generally switched to the current-controlled mode from voltage-controlled mode to limit the fault currents. In this situation, the inverter becomes equivalent to a symmetric, three-phase, positive sequence current source. However, the voltage limiting may occur under asymmetrical fault. In this paper, a closed-loop model based on time-domain is originally developed as a means to investigate the fault current characteristics under asymmetrical fault. Based on the proposed model, a more intuitive insight into fault currents is presented as follows. 1) The positive sequence fundamental component of three-phase currents can still track the symmetric current references. 2) The magnitude of fault phase currents (ignoring the harmonics) will vary between 1 and $\sqrt 3 $ times of magnitude of current limiting references. Based on the conclusion, although the magnitudes of fault phase currents can be reduced by adopting smaller current limiting references, the actual magnitudes of fault phase currents will still vary in a range depending on the load impendence of healthy phase. Therefore, the reliable action of the protection devices is greatly affected and the selective protection cannot be realized. Furthermore, in order to achieve completely controllable fault currents under asymmetrical fault, two alternative current limiting strategies are presented with reverse current limiting references, and with current limiting references based on the introduced phase angle regulation. The theoretical results are validated by simulations and experimental results. [ABSTRACT FROM AUTHOR]

Pulse generator in an ultrasound system produces electrical pulsing signals to drive piezoelectric transducer, which causes mechanical vibration of the crystals and generates sound waves. Different from conventional imaging short pulses, high-power ultrasonic system for therapeutic applications requires MHz pulses bursts of up to tens of milliseconds. The capability of switching high voltage (±90 V) at multi-MHz, delivering effective power efficiently, is crucial for practical systems. The advantages of low device loss at high switching frequency, and high power density make gallium nitride (GaN) high electron mobility transistors better devices than traditional silicon (Si) MOSFETs in such system. The GaN-based high-frequency transformer push–pull inverter presented in this paper is capable to produce high energy pulsating output with burst pulse length up to 50 ms and bipolar pulse amplitude of 180 Vpp. The maximum pulse frequency can be up to 10 MHz. The peak output power is 90 W with power density of 50.85 W/in2. The peak power for all the 128 pulser channels reaches up to 11.5 KW with average power of 192 W. This is the highest output power for pulse drivers that have been reported. A novel power transistor based RF switch circuit is also proposed in this design as the interface between image signal, high power signal, and return signal. [ABSTRACT FROM AUTHOR]

This paper introduces a high-gain single-stage boosting inverter (SSBI) for alternative energy generation. As compared to the traditional two-stage approach, the SSBI has a simpler topology and a lower component count. One cycle control was employed to generate ac voltage output. This paper presents theoretical analysis, simulation and experimental results obtained from a 200 W prototype. The experimental results reveal that the proposed SSBI can achieve high dc input voltage boosting, good dc–ac power decoupling, good quality of ac output waveform, and good conversion efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

With increasingly prominent role of rail transit in the entire urban transport system, an auxiliary inverter is used increasingly. The complicated and fluctuating load condition of the auxiliary inverter implies special designs about structure and control strategy are necessary. For this purpose, a comprehensive control strategy is proposed. First of all, this paper proposes a structure that is capable of suppressing unbalanced voltage. Second, the control strategy based on the resonant controller is proposed, which can balance split capacitors voltage, is capable of suppressing the effect of unbalanced load and nonlinear load. This paper introduces the design method of the control system in detail. Then, this paper simulates the proposed comprehensive control strategy in MATLAB. Finally, experimental results are presented, which fully demonstrate the excellent performance of the comprehensive control strategy. [ABSTRACT FROM PUBLISHER]

This paper proposes a new class of on-board chargers for electric vehicles (EVs). Instead of being placed on-board as a separate unit, the three-phase (fast) chargers reutilize the existing components in EVs, which are already used for the propulsion. These are primarily the inverter and the machine, which however have to be multiphase (with more than three phases). The concept is valid for all multiphase propulsion drives with a prime number of phases higher than three and a single neutral point in motoring and is illustrated in detail for the five-phase inverter/five-phase machine configuration. During the charging mode, electromagnetic torque is not produced in the machine so that the rotor does not require mechanical locking. Hardware reconfiguration between propulsion and fast charging is required, but it is achieved with only two switches, which are the only two nonintegrated elements. The integrated topology is explained in this paper, together with the control scheme, and extension from five phases to higher phase numbers is illustrated using the seven-phase system as an example. Finally, the propulsion-mode operation with complete suppression of low-order harmonics, which map into the second plane, is achieved for the five-phase machine. Experimental verification of theoretical results and proposed control is provided for both charging and vehicle-to-grid mode of operation, as well as for propulsion. [ABSTRACT FROM PUBLISHER]

Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high-power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application. [ABSTRACT FROM AUTHOR]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

Direct ac/ac topologies for ac-to-ac power conversion benefit from the absence of dc-link capacitors, and therefore, are highly reliable and have low cost as compared to the traditional voltage-source inverter (VSI)-based topologies. This paper deals with one of the more important tradeoffs considered in designing highly efficient converters: Losses. It is shown in this paper that the direct ac/ac converters have an inherently higher efficiency than their VSI-based back-to-back counterparts due to a dramatic reduction in switching losses (nearly 60%). Further, this paper compares the performance of three different device types (SiC MOSFETs, hybrid Si IGBT/SiC diode, and Si IGBTs) using wide-range device characterization that help to create detailed loss models. It is conjectured that traditional datasheets lack the level of detail needed for computing losses in direct ac/ac converters, and the availability of a multivalue voltage, current, and temperature-based loss profile is advocated. Using the obtained loss models, a comparison is drawn between the considered devices through simulations when operated in a 13-kV/1-MW direct ac/ac power flow controller, the controllable network transformer (CNT). The same loss-models are also used to compute losses in an experimental prototype of a 720-V, 10-kVA CNT and the results are compared with direct efficiency measurements. A similar computation is carried out for another experimental prototype at a 6.7-kV, 400-kVA, three-level, paralleled CNT. These experimental tests are used to confirm the validity of the analytical results presented in this paper. [ABSTRACT FROM AUTHOR]

Impedance networks cover the entire of electric power conversion from dc (converter, rectifier), ac (inverter), to phase and frequency conversion (ac-ac) in a wide range of applications. Various converter topologies have been reported in the literature to overcome the limitations and problems of the traditional voltage source, current source as well as various classical buck-boost, unidirectional, and bidirectional converter topologies. Proper implementation of the impedance-source network with appropriate switching configurations and topologies reduces the number of power conversion stages in the system power chain, which may improve the reliability and performance of the power system. The first part of this paper provides a comprehensive review of the various impedance-source-networks-based power converters and discusses the main topologies from an application point of view. This review paper is the first of its kind with the aim of providing a “one-stop” information source and a selection guide on impedance-source networks for power conversion for researchers, designers, and application engineers. A comprehensive review of various modeling, control, and modulation techniques for the impedance-source converters/inverters will be presented in Part II. [ABSTRACT FROM AUTHOR]

Leakage current minimization is one of the most important considerations in transformerless photovoltaic (PV) inverters. In the past, various transformerless PV inverter topologies have been introduced, with leakage current minimized by the means of galvanic isolation and common-mode voltage (CMV) clamping. The galvanic isolation can be achieved via dc-decoupling or ac-decoupling, for isolation on the dc- or ac-side of the inverter, respectively. It has been shown that the latter provides lower losses due to the reduced switch count in conduction path. Nevertheless, leakage current cannot be simply eliminated by galvanic isolation and modulation techniques, due to the presence of switches' junction capacitances and resonant circuit effects. Hence, CMV clamping is used in some topologies to completely eliminate the leakage current. In this paper, several recently proposed transformerless PV inverters with different galvanic isolation methods and CMV clamping technique are analyzed and compared. A simple modified H-bridge zero-voltage state rectifier is also proposed, to combine the benefits of the low-loss ac-decoupling method and the complete leakage current elimination of the CMV clamping method. The performances of different topologies, in terms of CMV, leakage current, total harmonic distortion, losses and efficiencies are compared. The analyses are done theoretically and via simulation studies, and further validated with experimental results. This paper is helpful for the researchers to choose the appropriate topology for transformerless PV applications and to provide the design principles in terms of common-mode behavior and efficiency. [ABSTRACT FROM AUTHOR]

This paper presents and compares control strategies for three-phase open-end winding drives operating in the flux-weakening region. A six-leg inverter with a single dc link is associated with the machine in order to use a single energy source. With this topology, the zero-sequence circuit has to be considered since the zero-sequence current can circulate in the windings. Therefore, conventional overmodulation strategies are not appropriate when the machine enters in the flux-weakening region. A few solutions dealing with the zero-sequence circuit have been proposed in the literature. They use a modified space vector modulation or a conventional modulation with additional voltage limitations. This paper describes the aforementioned strategies, and then, a new strategy is proposed. This new strategy takes into account the magnitudes and phase angles of the voltage harmonic components. This yields better voltage utilization in the dq frame. Furthermore, inverter saturation is avoided in the zero-sequence frame, and therefore, zero-sequence current control is maintained. Three methods are implemented on a test bed composed of a three-phase permanent-magnet synchronous machine, a six-leg inverter, and a hybrid digital signal processor /field-programmable gate array controller. Experimental results are presented and compared for all strategies. A performance analysis is conducted as regards the region of operation and the machine parameters. [ABSTRACT FROM AUTHOR]

This paper proposes a switched-capacitor multilevel inverter for high-frequency ac power distribution systems. The proposed topology produces a staircase waveform with higher number of output levels employing fewer components compared to several existing switched-capacitor multilevel inverters in the literature. This topology is beneficial where asymmetric dc voltage sources are available, e.g., in case of renewable energy farms based ac microgrids and modern electric vehicles. Utilizing the available dc sources as inputs for a single inverter solves the major problem of connecting several inverters in parallel. Additionally, the need to stack voltage sources, like batteries or supercapacitors, in series which demand charge equalization algorithms, are eliminated as the voltage sources employed share a common ground. The inverter inherently solves the problem of capacitor voltage balancing as each capacitor is charged to the value equal to one of the input voltage every cycle. State analysis, losses, and the selection of capacitance are examined. Simulation and experimental results at different distribution frequencies, power levels, and output harmonic content are provided to demonstrate the feasibility of the proposed multilevel inverter topology. [ABSTRACT FROM PUBLISHER]