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This paper presents the development of a solar cell inspection manufacturing execution system (MES). The main objective of the MES is to detect micro cracks in the manufacturing process of solar cells. Hence, to accept or reject a solar cell during the assembling unit. The proposed MES consists of three stages, at first stage, the inspection system will be placed on the manufacturing process of the solar cell. After the solar cell has been manufactured, it will pass under an in-line electroluminescent (EL) system. At this stage, an OR operation between a healthy/no-crack and the inspected solar cell image will be obtained. This OR operation will generate a better calibration for the cracks in the photovoltaic solar cell image. The final calibrated image presents a high quality, and low noise structure, thus easier to identify the micro cracks size, location, and orientation. The last stage evaluates the calibrated image using the plot profile which is well known as the distance in pixels versus the gray level of the image. The plot profile will indicate whether to accept or reject the solar cell, 10% confidence interval for the gray level was used to identify the upper and lower detection limits. [ABSTRACT FROM AUTHOR]

Defective die on a wafer map tend to cluster in distinguishable patterns, and such defect patterns can provide crucial information to identify equipment problems or process failures in the semiconductor manufacturing. Therefore, it is important to accurately and efficiently classify the defect patterns. In this paper, we propose a novel clustering-based defect pattern detection and classification framework for wafer bin map (WBM). The proposed framework has many advantages. Outlier detection and defect cluster pattern extraction can be done at the same time; arbitrarily shaped cluster patterns can be detected; and there is no need to specify the number of clusters in advance. Based on WBM property, the parameters used in the clustering algorithm are fixed so that parameter sensitivity can be avoided. Since the defect patterns are classified based on extracted features, no labeled data and no supervised classification training are needed and single-type patterns as well as mixed-type patterns can be found. Extensive experiments conducted on a real-world WM-811K dataset has shown the superiority of proposed framework. The proposed framework can also be used in a big data environment to accelerate performance. [ABSTRACT FROM AUTHOR]

Overlay errors depict misalignment between neighboring pattern layers on the wafer and are a critical measure of quality in lithography processes. In addition, stack-up overlay errors, which describe misalignments across non-neighboring layers, have also been shown to be important for product performance. Models relating overlay errors to tool parameters are the foundation of control methods that utilize in-process error measurements to adapt controllable parameters to minimize those errors. Unfortunately, these models are subject to noise and modeling errors whose characteristics cannot be accurately modeled, in that assumptions of Gaussianity or independence of noise terms, or perfect knowledge of model parameters cannot be ascertained. This paper proposes a methodology for robust control of lithography errors that is capable of handling parametric uncertainties in overlay models, as well as shortcomings in describing the noise and modeling errors. A series of simulations was conducted using a model available in the literature, as well as a model and data from a major 300 mm semiconductor fab. The results illustrate advantages of the proposed robust approach, with benefits increasing with higher levels of uncertainties. The results also depict specific improvements of errors in outer regions of the wafer, which are known to suffer from lower yields. [ABSTRACT FROM AUTHOR]

The detection of wafer faults in early process steps through monitoring and analyzing multivariate process trace data contribute to wafer yield improvements. Standard classification algorithms have been generally used for fault detection and classification (FDC). However, this approach can cause information loss while extracting statistical features from the trace data and cannot consider class imbalance situations where much fewer faulty wafers are generated than normal wafers. In addition, the approach does not consider normal wafer-to-wafer (W2W) variations and sensor noise inherent in the trace data. These drawbacks significantly degrade FDC performance. This paper proposes a method that builds an FDC model only with trace data of normal wafers in which W2W variations and sensor noise exist. The one-class FDC method detects the occurrence of abnormal trace patterns that cause wafer faults by removing W2W variations and sensor noise from raw traces by using denoising autoencoders, and this method finds the fault-introducing process parameters with the occurrence times. In experiments using the trace data of etch and chemical vapor deposition processes, the proposed method exhibited 1% and 6% higher performance than the best-performing method among comparison methods in terms of the geometric mean of the normal and fault detection accuracies. [ABSTRACT FROM AUTHOR]

In the process of double-sided lapping, the surface shape of the lapping wheel changes because of uneven wear, which affects the quality of the workpiece, especially the surface shape accuracy of the workpiece (bow, warp, and total thickness variance). Lapping trajectory is the primary reason for uneven wear on the wheel surface. Therefore, the uniformity of the lapping wheel wear during the double-sided lapping process will be investigated based on the trajectory distribution in this paper. First, the kinematics of double-sided lapping is analyzed, and the lapping trajectory equation is established. Then, the simulation calculation is conducted using MATLAB software to obtain the trajectory distribution characteristics of the wheel surface. The wear uniformity of the wheel surface is analyzed according to the distribution density of the trajectory. The wear model of the lapping wheel surface is established. Finally, double-sided lapping experiments with sapphire slices are carried out. Under varied workpiece material removal thicknesses, the changes of the lapping wheel surface profile are measured, and the wear of the lapping wheel surface along the radial direction is obtained and compared with the calculation results. The calculation results are basically consistent with the experimental results, which proves the correctness of the double-sided lapping wheel surface wear model. [ABSTRACT FROM AUTHOR]

In the via-middle process of 3-D integrated circuit manufacturing, through-silicon via (TSV) annealing causes mechanical stress not only to its surrounding structures, including liner and landing pad, but also the contacts nearby. This process may result in a noticeable pop-out in TSVs and/or contacts, thus complicating the subsequent chemical mechanical polishing (CMP). In addition, residual stress may cause delamination or crack. In this paper, we conducted detailed simulations of the residual stress and pop-out mechanisms for TSVs and neighboring contacts. Our primary focus was on the interplay of TSV-induced and contact-induced stresses and their combined impact on pop-out height. In addition, we conducted a sensitivity analysis of key parameters, including distance, plasticity, annealing temperature, and the distribution of neighboring contacts. This paper showed that these parameters notably affect the stress and the pop-out of TSVs and contacts. This in turn is expected to complicate the subsequent CMP steps. Finally, we applied the linear superposition method to predict stress and validated its accuracy by comparing the results with finite element analysis simulation. The results of the comparison demonstrated that the superposition method was accurate. Therefore, it could be used to predict the stress for full-chip design. [ABSTRACT FROM PUBLISHER]

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS for nanoscale technologies. In this paper, the viability of a mixed-signal design for FinFET-based technologies using a nanoscale current-starved voltage controlled oscillator (VCO) is investigated. Design issues are analyzed and a comparison between a CMOS VCO and a FinFET-based VCO is presented. The figures-of-merit used for comparison are center frequency and frequency–voltage ( f – V ) characteristics under process variation. Models are developed for the f – V characteristics of both the CMOS and FinFET VCOs. In addition, width quantization-aware modeling has been performed for the FinFET-based VCO using a polynomial metamodel, which can be used for further optimization. The quantization aware modeling is highly accurate as evident from a correlation coefficient R^2 of 0.999 and root mean square error of 6.2 MHz. The FinFET VCO has 5.5 \times faster oscillation frequency with 2.6% variability as opposed to 19.7% for the CMOS VCO. To the best of the authors’ knowledge, this is the first paper that examines FinFET technology with respect to process variation in mixed signal designs at the circuit level, and presents a quantitative as well as qualitative comparison between CMOS and FinFET technologies. [ABSTRACT FROM PUBLISHER]

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index. [ABSTRACT FROM AUTHOR]

This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs in integrated device manufacturing. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail—sensitivity to time, design cost, and production volume; platform designs; process postponement solutions; and design penalties. The model suggests that designers and fabrication facilities must collaborate extensively on the design and realizations of product platforms for state-of-the-art integrated circuit products to remain economically viable. [ABSTRACT FROM AUTHOR]

Due to increasing global competition, effective resource utilization is critical for maintaining competitive advantages. However, little research has been done to address space utilization of wafer fabrication facility. This paper aims to design a novel index, overall space effectiveness (OSE), to diagnose the fab layouts and identify directions for improving space usage effectiveness to enhance the overall space productivity as partial effort for total resources management. Furthermore, the proposed OSE can be extended to incorporate other critical performance indices such as cycle time, throughput, and revenue for effective management. Focusing on real settings of a leading semiconductor manufacturing company, a number of case studies were conducted and compared. The results have shown OSE gaps among various fabs and the proposed OSE can effectively derive improvement directions. This paper concludes with discussions on value propositions and future research directions. [ABSTRACT FROM PUBLISHER]

Semiconductor manufacturing is a highly innovative branch of industry, where a high degree of automation has already been achieved. For example, devices tested to be outside of their specifications in electrical wafer test are automatically scrapped. In this paper, we go one step further and analyze test data of devices still within the limits of the specification, by exploiting the information contained in the analog wafermaps. To that end, we propose two feature extraction approaches with the aim to detect patterns in the wafer test dataset. Such patterns might indicate the onset of critical deviations in the production process. The studied approaches are: 1) classical image processing and restoration techniques in combination with sophisticated feature engineering and 2) a data-driven deep generative model. The two approaches are evaluated on both a synthetic and a real-world dataset. The synthetic dataset has been modeled based on real-world patterns and characteristics. We found both approaches to provide similar overall evaluation metrics. Our in-depth analysis helps to choose one approach over the other depending on data availability as a major aspect, as well as on available computing power and required interpretability of the results. [ABSTRACT FROM AUTHOR]

Process variability is one of the major concerns in semiconductor manufacturing in advanced technology nodes. This paper explains an all-digital technique to estimate the impact of threshold voltage (${V}_{\text{th}}$) of NMOS device under test (NDUT) using a reconfigurable ring oscillator (RRO) which consists of a chain of threshold voltage measurement cell (TVMC). The difference of periods of RRO due to two voltage levels, i.e., ${V}_{\text {dd}}$ and (${V}_{\text {dd}}-{V}_{\text {th}}$) at the intermediate node provides information about the impact of threshold voltage of an NDUT. A lognormal model is developed to extract the threshold voltage information from the RRO period difference. The maximum difference in predicting the threshold voltage from the proposed model and through SPICE simulation is found to be less than 1.5%. Measured results from 26 test chips in 130-nm process show the feasibility of estimating the $\ {V}_{\text {th}}$ variability from the proposed RRO test structure. The proposed test circuit with 300 samples of NDUT occupies a silicon area of ${280} \,\, {\times }\,\, {64}\,\, {\mu } \text {m}^{{2}}$. [ABSTRACT FROM AUTHOR]

In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer yield. To enhance the alignment precision, an overlay metrology system measures the overlay error at some markers on the wafer, and the error information is used for constructing an overlay correction model. During the overlay alignment, the layout of the markers has a significant impact on the correction of the overlay error. After the maximum number of available markers has been determined based on the quality and turn-around time of the target device, the positions of those markers should be determined in such a way that the overlay error correction model shows robust performance for future wafers. In this paper, we propose a sparse particle swarm optimization algorithm to find an optimal marker layout in terms of robust performance characterized by the overlay error prediction and irregularity of marker positions. In the experiment, the performance of the marker layouts suggested by several search algorithms was tested on three different layers, and the proposed algorithm demonstrated superiority over the other algorithms. [ABSTRACT FROM AUTHOR]

Normalized cross-correlation (NCC) is used in many machine vision applications for industrial inspection. However, the high computational cost of NCC impedes real-time inspection. In this paper, we propose a modified low-complexity NCC scheme to discover the location of missing integrated circuits (ICs) in automatic printed-circuit board (PCB) inspection. In the proposed scheme, 2-D sub-images in the matching process are converted into 1-D feature descriptors. The running sub-images are scanned vertically and horizontally, augmented with spatial statistical measures, and then transformed by the discrete cosine transform (DCT) to create the feature descriptors. Experimental results of template matching on a 32-image dataset of PC and mobile phone PCBs show that the proposed scheme is more efficient and outperforms the traditional NCC and other schemes based on 1-D representations. Also, signal-to-noise measures show the robustness of the proposed technique against noise. [ABSTRACT FROM AUTHOR]

In a cluster tool for semiconductor manufacturing, a wafer waits within a chamber after processing until it is unloaded by the robot. Such wafer delays degrade wafer quality due to residual gases and heat, even cause quality failures. A cluster tool mostly operates in a ${K}$ -cyclic schedule, where an identical timing pattern repeats for each ${K}$ cycles, because of sporadic disruptions in process times or robot task times and the closed-architecture of the tool scheduler. In addition, it is hard to predict the ${K}$ -cyclic schedule that the tool will reach. Such a ${K}$ -cyclic schedule makes wafer delays at each chamber repeat ${K}$ different values. Therefore, such variability of wafer delays increases the risk of quality failure. Therefore, we examine the maximum wafer delay among all possible ${K}$ -cyclic schedules called the worst-case wafer delay in this paper. We first characterize the maximum cyclicity ${K}$ of tool schedules. We then develop closed-form formulas for most frequently used wafer flow patterns and an optimization model that computes the worst-case wafer delay. We also identify factors that affect the worst-case wafer delay and their influences by experiments. Finally, we suggest tool operation guidelines for lowering the worst-case wafer delay. [ABSTRACT FROM AUTHOR]

The characteristic curve (CC) of a production system is a function describing the behavior of cycle time (CT) versus throughput (TP). In systems with unlimited buffers, this function typically has a knee-type shape. Operating the system below the knee is not efficient, since TP can be increased without an appreciable increase in CT. Operating above the knee is also counterproductive—CT becomes extremely large without a significant increase of TP. Thus, the desirable operating point is at the knee. In order to operate the system at or close to the knee, some knowledge of its CC is necessary. In this paper, an analytical/empirical method for calculating CCs of single-product re-entrant lines is developed using the so-called bottleneck workcenter model of systems at hand. Based on this method, open- and closed-loop raw material release policies, which ensure operating at the desired point of CC, are provided. The development is carried out in terms of the First Buffer First Served (FBFS) and Last Buffer First Served (LBFS) dispatch policies, although CCs for other dispatch policies can be investigated in a similar manner. In addition, it is shown by simulations that the method developed can be used for evaluating CC of a model of a scaled-down wafer fab, which includes multiple workcenters and batching, as long as the severity of the bottleneck workcenter is sufficiently high. [ABSTRACT FROM AUTHOR]

Particle contamination in the dry etching chamber is one of the major issues in the semiconductor manufacturing. Particles on the wafer surface may cause wafer defects and yield loss. Therefore, particle monitoring is important to support contamination control and predictive maintenance activities. To achieve this goal, this paper proposes a virtual metrology (VM) method to estimate the deposit accumulation on the chamber wall, which can be a major root cause of the particle contamination. In the proposed method, the piecewise linear approximation (PLA) is employed and modified to derive a general segmentation template for the trace signals. Based on the trace segmentation template, important features that relate to the deposit accumulation are better extracted and modeled. To justify the effectiveness of the proposed method, we validate our method on the etching data from three different maintenance cycles. In the results, the proposed method with trace segmentation has improved performance compared to the VM model that does not segment the data, as well as the VM model that partitions the trace data by step number. The deposit accumulation indicator given by the proposed method demonstrates a slow trend over etching cycles and it matches well with the off-line metrology measurements. [ABSTRACT FROM AUTHOR]

A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers. Various defect patterns occur due to increasing wafer sizes and decreasing features sizes, which makes it very complex and unreliable process to identify them. In this paper, we propose a voting ensemble classifier with multi-types features to identify wafer map defect patterns in semiconductor manufacturing. Our research contents can be summarized as follows. First, three distinctive features such as density-, geometry-, and radon-based features were extracted from raw wafer images. Then, we applied four machine learning classifiers, namely logistic regression (LR), random forests (RFs), gradient boosting machine (GBM), and artificial neural network (ANN), and trained them using extracted features of original data set. Then their results were combined with a soft voting ensemble (SVE) technique which assigns higher weights to the classifiers with respect to their prediction accuracy. Consequently, we got performance measures with accuracy, precision, recall, ${F}$ -measure, and AUC score of 95.8616%, 96.9326%, 96.9326%, 96.7124%, and 99.9114%, respectively. These results show that the SVE classifier with proposed multi-types features outperformed regular machine learning-based classifiers for wafer maps defect detection. [ABSTRACT FROM AUTHOR]

An automatic defect classification (ADC) system identifies and classifies wafer surface defects using scanning electron microscope images. By classifying defects, manufacturers can determine whether the wafer can be repaired and proceed to the next fabrication step. Current ADC systems have high defect detection performance. However, the classification power is poor. In most work sites, defect classification is performed manually using the naked eye, which is unreliable. This paper proposes an ADC method based on deep learning that automatically classifies various types of wafer surface damage. In contrast to conventional ADC methods, which apply a series of image recognition and machine learning techniques to find features for defect classification, the proposed model adopts a single convolutional neural network (CNN) model that can extract effective features for defect classification without using additional feature extraction algorithms. Moreover, the proposed method can identify defect classes not seen during training by comparing the CNN features of the unseen classes with those of the trained classes. Experiments with real datasets verified that the proposed ADC method achieves high defect classification performance. [ABSTRACT FROM AUTHOR]

In this paper, an extended state observer (ESO)-based run to run (RtR) controller is presented to suppress various stochastic disturbances emerging in the semiconductor manufacturing process. Using the internal model control theory, the relationship between the ESO-RtR controller and the exponentially weighted moving average (EWMA) controller, and the relationship between the ESO-RtR controller and double EWMA controller are discussed. The stable region of the proposed ESO-RtR controller is calculated and discussed by using the Jury’s test. Furthermore, the ESO-RtR controller is extended to a nonlinear form (i.e., nonlinear ESO-RtR controller) to improve its disturbance compensation capability. Finally, numerical simulations and an industrial example are provided to demonstrate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

In modern semiconductor manufacturing, one type of measured particle count data contains excess zeros, and the ratio of zeros in the measurements is usually larger than 50%. This type of particle count sample data cannot be well modeled by popular defect models such as Poisson, zero-inflated Poisson, generalized zero-inflated Poisson, and Neyman and Gamma-Poisson models. In this paper, a threshold-Poisson model was proposed to describe the particles with excess zero counts, and the method for parameter estimation was developed. Via comparison with those popular models by using 15 measured samples, it showed that the measurements are better modeled by the threshold-Poisson model. A control chart called threshold-c control chart was proposed and the control limits were derived. A reasonable minimum sample size for constructing control chart was also discussed based on simulations. [ABSTRACT FROM AUTHOR]

In this paper, a $0.18~{\mu }\text{m}$ n-type lateral DMOS (LDMOS) is researched. By optimized manufacture process and device structures, ultra-low specific on resistance (${R} _{\mathrm {onsp}}$) is achieved. Pbody and n-type drift region are all full self-aligned implantation (FSAI). For different structures, the uniformities of the dc parameters affected by the process variation are researched. Experimental results show that: by optimizing manufacture process and device structures, the FSAI nLDMOS has competitive ${R} _{\mathrm {onsp}}$ compared with other technologies. For Breakdown voltage equals to 42 V and 52 V, the ${R} _{\mathrm {onsp}}$ are 18.7 $\text{m}{\Omega \bullet }$ mm2 and 30 $\text{m} {\Omega \bullet }$ mm2, respectively. For FSAI-nLDMOS, both simulation and experiment demonstrated that the shift of the dc parameters generated by the process variation is superior to the other technologies. Moreover, only one n-type drift region with filed oxide is used. The device is fabricated in bulk-silicon without epitaxy. These leads to the low cost of the fabrication. [ABSTRACT FROM AUTHOR]

Device packaging techniques continue to evolve. Modern packages connect components directly using different 3-D interconnect technologies. As the 3-D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect technologies available in 3-D-Stacked IC devices do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer bonding and extreme wafer thinning steps in the 3-D System on Chip integration technology schemes enable the increase of 3-D interconnect density. During the extreme wafer thinning process pathfinding and development, different thinning techniques were evaluated to target a final Si thickness specification. In this paper, metrology use cases that were applied in this pathfinding and development phase are demonstrated. Techniques, such as wafer level interferometry, wafer edge inspection and metrology, wafer front side metrospection, and wafer high resolution topography techniques were used to investigate process issues. Metrology data enabled us to determine where the extreme wafer thinning process could be improved. The same techniques were used to validate the improvements and to monitor process stability. [ABSTRACT FROM AUTHOR]

A solar cell manufacturing process typically has multiple, serial fabrication stages. In general, there are limited quality inspection and control points along the multiple fabrication stages, resulting in inconsistent product quality at the final stage. The existing studies on solar cell manufacturing focus on offline quality monitoring after completion of all manufacturing stages. Thus, an effective in-process method of detecting changes in key stages in terms of product quality is necessary to mitigate the effect of the quality fluctuation. This paper proposes an in-process method of detecting the process changes in terms of product quality by studying multichannel sensing signals collected in the epitaxy stage. This stage is an important stage of material layer formation and considerably influences the solar conversion efficiency of the final product. Interpretable geometric features are obtained by considering the process knowledge for each channel of sensing data. A decision-level data fusion method is further proposed to integrate the changes detected from each sensing signal. The proposed method is demonstrated via a real case from solar cell manufacturing processes. [ABSTRACT FROM AUTHOR]

This paper demonstrates overcoming of the Abbe diffraction limit (ADL) on image resolution. Here, terahertz multispectral reconstructive imaging has been described and used for analyzing nanometer size metal lines fabricated on a silicon wafer. It has also been demonstrated that while overcoming the ADL is a required condition, it is not sufficient to achieve sub-nanometer image resolution with longer wavelengths. A nanoscanning technology has been developed that exploits the modified Beer-Lambert’s law for creating a measured reflectance data matrix and utilizes the “inverse distance to power equation” algorithm for achieving 3-D, sub-nanometer image resolution. The nano-lines images reported herein, were compared to scanning electron microscope (SEM) images. The terahertz images of 70 nm lines agreed well with the transmission electron microscope images. The 14 nm lines by SEM were determined to be ~15 nm. Thus, the wavelength dependent Abbe diffraction limit on image resolution has been overcome. Layer-by-layer analysis has been demonstrated where 3-D images are analyzed on any of the three orthogonal planes. Images of grains on the metal lines have also been analyzed. Unlike electron microscopes, where the samples must be in the vacuum chamber and must be thin enough for electron beam transparency, terahertz imaging is non-destructive, non-contact technique without laborious sample preparation. [ABSTRACT FROM AUTHOR]

In order to maintain a competitive edge in the face of increasing global competition in the semiconductor memory market, device makers in the IC memory industry need to continuously improve their productivity by implementing novel manufacturing strategies that are applicable to the rapid market changes characteristic of the industry. Conventional wafer productivity strategies typically only focus on maximizing gross die out, a strategy which does not address wafer productivity for profitability, i.e., return on investment (ROI), with respect to current market situations, since ROI is significantly influenced not only by the number of gross die out, but also by other factors both within the manufacturing line, for example by the number of photolithography shots per wafer, and also by external factors, most importantly the market price of the memory devices being produced. In this paper, we propose a novel productivity model based on ROI and use the ROI-based model to evaluate wafer maps and thereby to determine optimal chip sizes for maximizing fab productivity. To evaluate wafer productivity accurately, we predicted yields from various wafer map configurations using deep neural networks, and, to search for productivity-maximal wafer maps in extremely large search spaces, we adopted differential evolution as the optimization technique. Comparison results have demonstrated that our proposed method effectively improved wafer productivity by up to 7.96%, in contrast with the old method. By incorporating these market-oriented indicators into standard yield models, we offer a new way for memory device manufacturers to maximize productivity and maintain competitive advantage for their semiconductor fabrication lines. [ABSTRACT FROM AUTHOR]

This paper presents the fabrication and characterization of a low parasitic capacitance and low-stress Si interposer for 2.5-D/3-D integration of stress sensitive MEMS devices. The glass reflow process is utilized to isolate Si posts (through silicon interposer) from Si substrate of a low resistivity to form vertical electrical interconnection. A process is developed and a dummy Si interposer is fabricated. Using the fabricated samples, the Si interposer is characterized in terms of resistance, parasitic capacitance, breakdown voltage, and residue stress test. Air-gapped Si interconnection is measured with a resistance of 0.9 Ω, a parasitic capacitance of 85.12 fF and a breakdown voltage of 250 V at least. The residual stress of Si interposer is also investigated through infrared flare technology and shows a result that less than 30 MPa around the Si interconnection at 350 °C. [ABSTRACT FROM AUTHOR]

In this paper, the evolution of various lithographic processes aimed at fabricating robust tantalum nitride (TaN) resistors in GaAs-based BiFET and BiHEMT technologies are discussed in detail. Such approaches include the common image reverse photograph process (via amine poisoning) using a positive tone resist, the use of a chemically amplified negative tone resist, and also straight patterning of a positive tone resist. The aforementioned approaches were found to have their own unique challenges as it applied to printing robust TaN-based resistors approaching nearly a micron in width which is needed for high density mixed signal designs. We will explore many of these challenges in detail for the various lithography schemes. [ABSTRACT FROM AUTHOR]

To examine surface quality of light emitting diode (LED) substrates, human visual inspection is commonly used. However, manual inspection is not reliable because patterns of an integrated substrate are small and repeating. This paper describes a machine vision method for auto-detecting defects embedded on LED substrates. Image of arranged substrates is first grabbed. A global image restoration scheme based on non-negative matrix factorization (NMF) is used to reconstruct a non-negative matrix approximation (NMA) using a matrix of lower dimension and a weight matrix with non-negative elements. Repeating patterns of NMF output, i.e., NMA, can be considered similar to its input counterpart that defects have been excluded. Defects thus can be efficiently revealed by subtracting grabbed image from NMA. A procedure to determine proper basis space size of a specific image using pseudo singular value and a procedure to initialize a proper pair of factors using non-negative double singular value decomposition are also described. The proposed method is compared with methods of Lu and Tsai (2005), Lu and Tsai (2008), Perng and Chen (2010) and Chen and Perng (2011). Overall, results show that G-measure for proposed method under conditions of normal and various exceptions is higher than other available low-rank approximation methods. [ABSTRACT FROM AUTHOR]

Automatic color classification for solar cells is challenging because of the tiny color difference and low contrast. To address this problem, a color feature selection and classification frame is proposed in this paper. First, an intuitive multi-color space feature performance evaluation scheme is presented to select the optimal color subspaces that help to enormously enlarge the tiny color difference of solar cell images. And the optimal color subspaces can also be illustrated by employing multi-color space visualization method with combinational Mosaic images. Second, a nine-dimensional feature vector consisting of mean, variance, and skewness in the three optimal subspaces is extracted by utilizing the serial fusion technique. Third, an improved Gaussian mixture model in supervised manner for color classification is proposed by employing a k-means method based on adjacent rules, which helps to eliminate isolated points and enhances the classification performance. Finally, experimental results show that the overall performance of the proposed method achieves 97.9%, and outperform other algorithms especially for the tiny color difference of solar cell images. [ABSTRACT FROM AUTHOR]

The latest advances in a GaN on SiC RF technology for powering radar systems and particle accelerators are reported. Unlike research-grade technologies based on novel materials, the technology presented here is highly manufacturable as it is based on commercially available GaN on SiC epitaxial wafers and the AlGaN/GaN high electron mobility transistor (HEMT) structure. However, compared to state-of-the-art GaN on SiC RF technology operating from 28 to 50 V, the approach and results presented in this paper explore core transistor designs that are suitable for operation with a bias voltage ranging from 75 to 150 VDC. Wafer processing is similar to typical GaN HEMT process modules for commercially available 28 – 50 V technology and therefore can be easily implemented in existing GaN on SiC manufacturing lines. The approach results in power densities > 10 W/mm at hundred watts power levels which is very desirable in mega-watts RF systems. The results presented in this publication illustrate some of the benefits achievable in radar systems and RF power sources for particle accelerators. [ABSTRACT FROM AUTHOR]

There are many different methodologies for a line startup, process transfer, line conversion, and process upgrade in semiconductor IC manufacturing. In our startup of a 200 mm bulk acoustic wave filter line converted from an existing 150 mm production line, a methodology of copy, scale, develop, and match (CSDM) was introduced. This methodology includes four phases of matching (unit qualification, short flow verification, pathfinder validation, and qualification lot process) between 150 mm and 200 mm process, different failure mode effects analysis (DFMEA) for the risk assessment of the differences between two processes, process flow breakdown with process blocks and sub-blocks, a decide, define, determine, and design method of process evaluation with short loop flow process monitors based on DFMEA assessment. Following this CSDM methodology throughout the conversion process ensures that both electrical and reliability performances of 200 mm product wafers match to those of the 150 mm line. The first 200 mm full flow pathfinder lot with electrical yield on parity to 150 mm line yield. In this paper, the application of this CSDM methodology is discussed in detail. [ABSTRACT FROM AUTHOR]

Automated material handling systems (AMHSs) used in semiconductor fabrication are sophisticated and integrated control systems that transfer materials from one machine to another within a manufacturing facility via hundreds of vehicles. Vehicular congestion in AMHSs causes significant production inefficiency. In this paper, we demonstrate the reasons for and classification of congestion, and suggest congestion metrics for material handling systems. We develop and implement a congestion monitoring system (CMS) based on the proposed metrics at an actual manufacturing site. We provide practical case studies on three applications to address the effectiveness of CMS: 1) congestion monitoring; 2) redistribution of routing; and 3) enhancing a routing algorithm. Simulation results demonstrated that the proposed routing algorithm decreased the average delivery time by 12.41% in heavy congestion. The shorter average delivery time reduces the loss in production by at least 1%. [ABSTRACT FROM AUTHOR]

Electrical discharge damage is an unpredictable source of yield loss and a constant challenge to device reliability for the micro-electronics industry. There is considerable history and established methodology for handling charging effects for the silicon semiconductor sector, but literature is generally limited for GaAs and III–V compound semiconductor manufacturing. In this paper, electrical charging and subsequent discharge defects created during isolation implant processing of epitaxial wafers combining hetero-junction bipolar transistor and HEMT are discussed. As is common in semiconductor fabrication, a combination of the circuit layout, process sequence and tool configuration formed the ideal condition for a surge of electrical charging related yield failures. Through extensive examination and analysis, the primary source and mechanism of the failure were identified. These findings lead to development of proper detection and the resolution of the issue through key process improvements that ultimately enhanced yield and the GaAs integrated circuit die robustness against charging induced damage. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to introduce a novel concept for integrating enhancement mode (E-mode) and depletion mode (D-mode) AlGaN/GaN HEMTs in the same fabrication process. Unlike existing E/D integration technologies (gate recess etching, fluorine implantation, etc.), the proposed technology does not involve process steps that damage the semiconductor layer and therefore more reliable devices are to be expected. It allows control of 2DEG density under the gate region by means of external mechanical stress applied to the AlGaN barrier layer. The stress is introduced by a dedicated SiNx passivation film. E-mode and D-mode GaN HEMTs with state-of-the-art dc performance were fabricated on the same wafer using the proposed technology. The process flow for E/D transistors fabrication is presented as well. [ABSTRACT FROM AUTHOR]

In this paper, we directly compare the influence of sputtered and chemical vapor deposited TiN liners on the contact resistance of large tungsten filled vias with an aspect ratio of 3:1. Scanning transmission electron microscopy, energy-dispersive X-ray spectroscopy, and time-of-flight secondary ion mass spectrometry studies revealed that during WF6-based tungsten chemical vapor deposition (CVD), fluorine diffuses through a poor physical vapor deposited (PVD) TiN barrier layer and reacts with the underlying titanium and aluminum to form high resistive compounds. Aside from depositing a thicker TiN PVD barrier, the replacement of the 40 nm PVD layer with a thinner TiN CVD liner has led to significantly reduced via resistances with very small deviations across the wafer and lot. We show that the CVD layer has a superior barrier performance against fluorine penetration, provides a conformal coverage and can be used at a reduced thickness compared to the PVD process. [ABSTRACT FROM AUTHOR]

In the semi-conductor industry, factories ramp their production capacity in parallel with tool (machine) installations. Ramp capacity, and subsequently wafer starts, are aligned with additional installs of the most expensive tool. Subsequently, starts are set to the full capacity of that limiting toolset. In this paper, we argue that this may not be best method to maximize output over the ramp period and that by keeping ramp starts below constraint capacity, increased levels of cumulative output can be achieved for a desired planning horizon (e.g., the first year of production). A mathematical framework of the problem is provided to support our hypothesis, together with numerical examples and a set of simulation experiments. [ABSTRACT FROM AUTHOR]

In this paper, CMOS wafer level ring oscillator frequency variability improvement >40% is demonstrated by either spatial source/drain activation or ion implantation super scan in FinFET technology. Yield improvement (up to 17%) is verified with better within wafer uniformity and with no intrinsic device performance degradation. Furthermore, the combination of super scan and spatial source/drain activation is suggested for optimized variability improvement benefits from individual device type uniformity tuning (super scan) and all device type uniformity tuning (from spatial S/D activation). [ABSTRACT FROM AUTHOR]

Multi-wafer planetary type chemical vapor deposition (CVD) reactors are widely used in thin film growth and suitable for large scale production. In this paper, numerical modeling has been carried out to simulate transport phenomena and epitaxial silicon growth in a planetary CVD reactor for the SiH2Cl2–H2–HCl system. A chemical reaction model using temperature dependent reaction rate is proposed and validated using experimental data. Based on the model, the effect of various operation conditions such as satellite rotational speed, species concentration, operating temperature and pressure is considered to determine the key factor influencing the growth rate and uniformity. The results reveal that the growth rate and uniformity are strongly related to total flow rate, species concentration and operating pressure, but are not affected by rotational speed of the satellite in case of high flow rates. Growth rates are found to be increased from 0.02 $\mu \text{m}$ /min at operating pressure of 10 torr to approximately 0.16 $\mu \text{m}$ /min at 150 torr. Growth deposition non-uniformity decreases from 80% for total flow rate of 460 slm to 13% for total flow rate of 46 slm. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, a wafer bin map (WBM) represents the results of wafer testing for dies using a binary pass or fail value. For WBMs, defective dies are often clustered into groups of local systematic defects. Determining their specific patterns is important, because different patterns are related to different root causes of failure. Recently, because wafer sizes have increased and the process technology has become more complicated, the probability of observing mixed-type defect patterns, i.e., two or more defect patterns in a single wafer, has increased. In this paper, we propose the use of convolutional neural networks (CNNs) to classify mixed-type defect patterns in WBMs in the framework of an individual classification model for each defect pattern. Through simulated and real data examples, we show that the CNN is robust to random noise and performs effectively, even if there are many random defects in WBMs. [ABSTRACT FROM AUTHOR]

The rise of industry 4.0 and data-intensive manufacturing makes advanced process control (APC) applications more relevant than ever for process/production optimization, related costs reduction, and increased efficiency. One of the most important APC technologies is virtual metrology (VM). VM aims at exploiting information already available in the process/system under exam, to estimate quantities that are costly or impossible to measure. Machine learning (ML) approaches are the foremost choice to design VM solutions. A serious drawback of traditional ML methodologies is that they require a features extraction phase that generally limits the scalability and performance of VM solutions. Particularly, in presence of multi-dimensional data, the feature extraction process is based on heuristic approaches that may capture features with poor predictive power. In this paper, we exploit modern deep learning (DL)-based technologies that are able to automatically extract highly informative features from the data, providing more accurate and scalable VM solutions. In particular, we exploit DL architectures developed in the realm of computer vision to model data that have both spatial and time evolution. The proposed methodology is tested on a real industrial dataset related to etching, one of the most important semiconductor manufacturing processes. The dataset at hand contains optical emission spectroscopy data and it is paradigmatic of the feature extraction problem in VM under examination. [ABSTRACT FROM AUTHOR]

Virtual metrology (VM) is often applied in semiconductor manufacturing when process measurements cannot be obtained without delay or without impacting the cycle time. When the process condition is varying, the modeling results can be inaccurate if a single VM model is adopted. Also, the large number of variables in the process data increases the difficulty of obtaining good predictions. To improve the accuracy of the metrology value prediction, it is necessary to select and apply only the significant variables in modeling. This paper proposes a just-in-time approach for VM modeling, along with a variable shrinkage and selection method that uses Gaussian process regression. The proposed method is validated using semiconductor process data and found to be superior compared to conventional methods. [ABSTRACT FROM AUTHOR]

The bottom-up fabrication of nanostructures can simultaneously face large uncertainties from experimental runs (R), physical understanding (P), and measurement (M). No systematic strategy has been reported to manage these three types of uncertainties, abbreviated as RPM, concurrently to achieve better understanding of nano fabrication processes. Previously, we developed cross-domain model building and validation (CDMV) approach to handle large physical and measurement (PM) uncertainties in nano fabrication process modeling. In this paper, we propose to prioritize RPM uncertainties and to incorporate the analysis of run variations into process modeling. Under a Bayesian hierarchical framework, this new strategy will first handle PM uncertainties at the basic level to identify a model structure using CDMV approach. The rationale is that the uncertainty due to experimental runs should not fundamentally change the process physics or the model structure, but impacts on the model parameters. At a lower hierarchy, process model parameters varying or invariant to runs are treated as random effects or fixed effects to be identified respectively. Demonstrated in a nanowire growth process example, the new strategy not only assists to establish an improved process model, but also to uncover the variation sources contributing to large run variations. The obtained physical insights can guide further process investigation. Note to practitioners: experimental investigation of nanofabrication processes often encounters large uncertainties due to a lack of conclusive understanding of process physics, measurement noise, and variability among experimental runs. Trial-and-error strategy is commonly adopted under this scenario to explore the process physics with little guidance, resulting in increased cost of experimentation or fabrication. This paper presents an alternative strategy to make more efficient use of data to manage large RPM uncertainties and achieve better process understandings for process improvement. [ABSTRACT FROM PUBLISHER]

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 \mu \textm top entrant critical dimension and 50 \mu \textm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 \mu \textm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating. [ABSTRACT FROM AUTHOR]

This paper provides an overview of new approaches for assessing and addressing requirements for carrier logistics in semiconductor manufacturing and discusses solutions for optimizing the efficiency of capital equipment installed in the fab. An exploration of crucial influencing factors (both on the material handling as well as on the equipment side) will be followed by a discussion of different approaches to the challenges and an assessment of the impact of the proposed improvements. This paper also demonstrates how effective equipment throughput can be improved by the proposed methods. [ABSTRACT FROM AUTHOR]

Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3-D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes a new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g., bad transistor with very high threshold voltage) a series of measurement under various test conditions was performed and analysed. In order to overcome a limitation of the contact chain size and enable data collection from larger sample of contacts, we proposed to implement the gated chains in addressable arrays, increasing their density and failure rate observability. Finally, the paper presents the examples of electrical failure modes detected by those chains in FinFET process. [ABSTRACT FROM AUTHOR]

In this paper, a cost-effective, easy-install and fast measurement and analysis method to obtain seismic response of semiconductor manufacturing equipments was developed and its validity was discussed. In the developed method, micro-vibration measurement experiments are first carried out to obtain transfer functions and coherence functions from the floor to arbitrary part of equipment. Using obtained transfer function, seismic response of the arbitrary part of equipment is analyzed with seismic floor response input. In this paper, the developed method was applied to a vertical furnace and a lithography system and their transfer functions were experimentally obtained. It has been confirmed that with additional excitation on the floor near the equipment is effective to improve the accuracy of obtained transfer functions. The validity of developed analysis method was confirmed by the good agreement between the analytical result and the experimental result obtained with a shaking table. The developed method is to be useful to estimate seismic damage of various types of semiconductor manufacturing equipment as well as to take seismic countermeasures. [ABSTRACT FROM AUTHOR]

This paper reports results of a study on copper voids seen in a back end of line (BEOL) module. The experiment was designed to study the effect of multiple parameters that can influence the occurrence of voids and their process margins. This work also reports the effect of changes in copper seed thickness on the product’s lifetime and reliability. [ABSTRACT FROM AUTHOR]

The IEEE Transactions on Semiconductor Manufacturing congratulates Yonghwi Kwon and Youngsoo Shin whose paper Optical Proximity Correction Using Bidirectional Recurrent Neural Network With Attention Mechanism was selected as the Best paper for 2021. The paper was selected from all the papers that appeared in 2021 by a team of Associate Editors. This paper applied recurrent neural networks to optical proximity correction for lithographic processing for integrated circuits. The challenge in determining a correction value comes from correlation: correction of one segment affects the correction value of other segments due to the optical proximity effect. This paper broke new ground by showing that Recurrent Neural Networks, which has been mainly applied to time series data, can be effectively applied to spatial data. Clearly, Machine Learning is rapidly moving from R&D into full flow manufacturing where the interplay between each aspect of a single process step has exponential increased in complexity requiring new approaches. Three additional papers were recognized with an Honorable Mention: [ABSTRACT FROM AUTHOR]

In this paper, we describe an innovative method to form an ultralong ultralow loop for wire bonding. A resister was used to form kinks and simplify the capillary trace, which yielded a loop-like “n”-shape with two kinks immediately above the first and second bonds that can support the entire long-span loop. A 3-D finite element model was developed to simulate the n-loop formation, and the loop profiles of an n-loop, M-loop, and standard loop were compared. In this paper, we show that this novel n-loop can almost halve the looping time compared to that for the M-loop; and the n-loop can avoid wire sag for a 5000- $\mu $ m-long span. Furthermore, the loop height and wire verticality near the second bond can be modified by regulating the horizontal and vertical positions of the resister. [ABSTRACT FROM PUBLISHER]