Search

Paper-based digital microfluidic biochips (PB-DMFBs) have emerged as the most promising solution to biochemical applications in resource-limited regions. However, like silicon chips, the reliability of PB-DMFBs is affected by physical defects. Even worse, since electrodes, conductive wires, and droplet routings are entangled on the same layer, multiple faults may occur simultaneously. Such faults not only cause waste of samples and human resource but also affect the correctness of the diagnostics. In this paper, we propose a reliability scheme with emphasis on design-for-reliability (DfR) and probability-based fault tolerance to ensure the correct functionality of PB-DMFBs with multiple faults. • Multiple fault assumption is considered for electrode open fault and wire open fault models. • Design-for-Reliability design flow is proposed for alternative droplet paths to bypass the faulty electrodes. • On-the-fly fault tolerance procedure is proposed to tolerate the faulty electrodes. • The proposed procedure has the least dependence on sensors for fault tolerance automation. [ABSTRACT FROM AUTHOR]

Internet of Things (IoT) powered by high level synthesis (HLS) provides huge opportunity of progress in the area of hardware design. However, the present era of hardware design involves globalization which poses security threat to the design integrators that rely on third party intellectual property (IP) cores for increasing design productivity at reduced design time. This paper presents for the first time in the literature, a low cost optimized hardware Trojan secured HLS approach for hardware (or application specific core) designs that is based on single or nested loop control data flow graphs (CDFG) applications. The paper presents multiple novel vendor allocation schemes (each with its own attribute of delay and area) as security constraint that yield Trojan secured schedules at behavioral level. Demonstration of the proposed approach on a nested loop case study asserts our proposed theory. Results on standard benchmarks indicate significant reduction in final solution cost compared to a similar approach. [ABSTRACT FROM AUTHOR]

Thanks to its richness in extractable features, Hyperspectral images (HSI) find an accelerated use in medical, industrial, agricultural, and environmental fields. In this paper, we present a wavelet-based reduction technique that creates a Hypercube containing the most significant features extracted from the original HSI and representing a multi-dimensional array that is utilized for training a Convolutional Neural Network (CNN), which is designed here to classify different types of surfaces or materials. The performance of this approach is tested and proved using two distinct datasets. Then, we compare the same approach with the PCA, a widely used reduction method. The most important contribution of this paper is the implementation of an FPGA-based parallel accelerator to train the same suggested CNN in only 10% of the computational time compared to the classical CPU-based techniques. The Microblaze will be explained and exploited here to play the role of an embedded microprocessor. • A Wavelet-based technique gives a reduced Hypercube rich in pixels spectrum features. • A CNN is designed to classify different types of surfaces or materials. • An FPGA-based parallel design is created to reduce 90% of the CNN training time. • The Microblaze is used to play the role of an embedded microprocessor. [ABSTRACT FROM AUTHOR]

SRAM cells in spacecraft or space stations are susceptible to single event upset (SEU) caused by high-energy particle impacts. Conventional 6 T SRAM cells are more prone to soft errors in this environment. In this paper, we propose a new highly stable soft-error immune SRAM cell with multi-node upset recovery (SIMR-18 T). This design is an improvement from the Quatro-10 T. The design not only tolerates all SEU and performs well in double node upset (DNU). This paper mainly compares with other structures in terms of read and write access time, static noise margin, and critical charge. The write access time of this cell (11.75 ps) is lower than all other cells. The static noise margin for write, about 1010.11 mV, is 151.87% of that of the QUATRO12T. • Compared with other designs, this structure has higher write and hold static noise margin (WSNM and HSNM). • This design not only tolerates all signal event upset (SEU) and performs well in double node upset (DNU). • This structure has a larger critical charge (Q c) of about 90fc. [ABSTRACT FROM AUTHOR]

This paper investigates three substitution box (S-box) designs for lightweight ciphers. The proposed designs involve functional decomposition, which is preferable as compared to the look-up tables or logic gates-based S-box designs due to their advantages, as outlined in this paper. The aim is to reduce the number of literals at the input of the S-box to achieve resource reduction in the overall circuit design of the encryption algorithms. The proposed S-box architectures provide optimized resource mapping for specific target hardware, and high throughput along with lesser energy consumption compared to state-of-the-art designs. The proposed S-box designs are applied to the substitution layers of symmetric lightweight block ciphers with a standard security level. In order to be fair in comparison, the overall cipher designs are targeted for similar FPGA-based implementation as used in existing works, while the architectures of the individual 4-bit S-boxes are evaluated using SAED90 nm standard cell libraries. The performance of the proposed S-box designs is observed to be superior at RFID and ISM frequency ranges which can be deployed in applications constrained to low resources as well as demanding high performance and medium security. • Three S-box architectures are proposed using functional decomposition techniques. • The proposed designs are applied to the substitution layer of each cipher i.e., GIFT, Midori, PRESENT and RECTANGLE. • The throughput and energy of the architectures are evaluated for RFID and ISM band frequencies to manifest the utility of lightweight ciphers in IoT applications. [ABSTRACT FROM AUTHOR]

The multiple-node upset (MNU) phenomenon caused by charge sharing increases rapidly in advanced nano-scale latches, making it more critical to design hardened latches for MNU. This paper proposed a low overhead quadruple-node upset self-recoverable latch based on a triple-mode redundancy latch named LQNTL, which consists of three modules with data feedback interlocking within each module to achieve high reliability. Simulation results show that the proposed LQNTL reduces power consumption, delay, PDP, and area by 69.76%, 6.35%, 71.68%, and 10%, respectively, compared to the latest soft-error tolerant latch of the same fault tolerance. The analysis of PVT variation shows that the LQNTL is more stable for the process corner, supply voltage, and temperature variations. • In this paper, a low overhead QNU self-recoverable latch, LQNTL, based on triple-mode redundancy, is proposed to provide complete QNU resilience while maintaining the minimum cost in terms of PDP. • The HSPICE simulation under the 32 nm PTM shows the proposed structure fully tolerates the QNU and is QNU self-recoverable. • PVT variation analysis indicates that LQNTL has stability on delay and power consumption. • Compared with the recent QNU self-recoverable latch named QNURL, LQNTL reduces power consumption, delay, PDP, and area overhead by 69.76%, 6.35%, 71.68%, and 10%, respectively. [ABSTRACT FROM AUTHOR]

Hardware Trojan detection is a crucial problem with many dimensions and high complexity. Side channel analysis based methods are advantageous for not requiring Trojan activation but deeply suffer from process variations, the inability to detect small Trojans as well as the requirement for golden chips. In this paper, a non-invasive, golden chip free delay based hardware Trojan detection method is proposed. It exploits the inherent spatial correlations to suppress the Trojan hiding effect of the variations. The method is verified using post-manufacturing simulations under an elaborative variation model considering both inter and intra die components. The results reveal that although delay-alone approach fails to detect minimal Trojans, the proposed method achieves the detection securing more than 91% percent of a circuit on average. Moreover, if the trigger detection in cooperation with the payload detection is utilized, the detection probability exceeds 99%. • The aim of the paper is delay based hardware Trojan detection. • The design and test houses are assumed to be trusted while the fab is untrusted. • The method suppresses variations, which hide the effect of the hardware Trojan. • It gets advantage of spatial correlations existed inherently in chips. [ABSTRACT FROM AUTHOR]

The development of ARX-based lightweight block ciphers has been plagued by the difficulty of theoretical security analysis. SAND solves this problem better by obtaining an equivalent representation based on a synthetic S-box. This paper analyzed SAND in terms of diffusivity and found that it can be optimized. SAND has the issue of slow diffusion after the initial plaintext and key are all 0. On the other hand, it takes at least 11 rounds for SAND to reach full diffusion without AddRoundKey. Thus, this paper proposes a high-diffusion architecture SAND-2 to address the above issues. Firstly, issue 1 is solved by replacing the AND operation with a NAND operation and calling the round function dynamically. Then, in order to solve issue 2, P1 and P2 permutations are introduced into G 0 and G 1 , respectively. The full diffusion speed of SAND-2 is 63.7% increased compared to SAND. In addition, the comparison results of hardware indicators show that the hardware resources of SAND-2 are slightly lower, and the throughput is 10% higher than SAND. Finally, the security analysis shows that SAND-2 reaches the upper bound of the resisting differential analysis in fewer rounds. • SAND-2 diffusion speed is 63.7% increased by SAND. • SAND-2 throughput is 10% higher than SAND. • SAND-2 is more secure than SAND. [ABSTRACT FROM AUTHOR]

This paper proposes a 13-bit two-step single-slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be +0.8/-0.8 LSB and +2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 60% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors. • The frame rate of CMOS image sensor with large array is difficult to improve. • A high speed and high resolution column level analog-to-digital conversion method. • A correction method for solving non-ideal effect in a two-step analog-to-digital converter circuit. • The conversion time of a 13 bit resolution column parallel analog-to-digital converter reaches 512 ns. [ABSTRACT FROM AUTHOR]

This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively. • LPDNUR and HSDNUR fully achieve SNU and DNU recovery. • Average power of LPDNUR is 24.59% lower on average than other SRAM hardened since stack structure. • WAT and RAT of HSDNUR are 24.14% and 35.71% lower than other SRAM hardened on average by using TG. [ABSTRACT FROM AUTHOR]

This paper comments on the some mistakes which have been observed in Tripathi et al. (2023) [1]. We have specifically pointed out the following mistakes of Tripathi et al. (2023) [1]. i) Presented (41, 32) SEC-DAEC-TAEC H-matrix in Fig. 3 of Tripathi et al. (2023) [1]. ii) Presented error detection and correction coverage in Table 6 of Tripathi et al. (2023) [1]. The corrected versions of the above mentioned mistakes have been presented in this paper. Also the FPGA-based synthesis result of corrected encoder and decoder circuits based on the corrected (41, 32) H -matrix have been presented here. [ABSTRACT FROM AUTHOR]

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0. 18 μ m , CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μ V at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μ W and occupies 8194 μ m 2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design. • The BBFC OP-AMP avoids external R, C elements to achieve improved compensation. • Feedback for offset, noise minimization and self-biasing in load, tail source. • BBFC OP-AMP based CFIA offers wide BW without degrading gain, improves NEF and FoM. • Taguchi DoE and ANOVA provide sizes of MOS transistors to achieve optimized results. • High tunable gain, high CMRR and low power promising for the biomedical applications. [ABSTRACT FROM AUTHOR]

Internet of Things (IoT) has gained popularity in recent years and has engulfed nearly every industry. The widespread use of numerous ubiquitous computing devices in the low-resource domain has resulted in a new set of privacy and security concerns. To address the problem of security in resource-constrained devices, many lightweight algorithms have been developed. This paper proposes optimized hardware implementations of the lightweight PRINCE block cipher, with the aim of providing adequate security while maximizing resource efficiency. The proposed architecture uses fewer resources and provides a reasonable trade-off between area footprint and efficiency. In the proposed unrolled pipelined architecture, the encryption round is divided into three sub-stages, with registers inserted in between. Using this design approach, the operating frequency is greatly improved. As a result, this architecture adapts itself effectively to high-performance applications. This paper also proposes serial-based and round-based architectures for resource-constrained devices. The proposed unrolled sub pipeline PRINCE block cipher is implemented on the Virtex-6-FF784 and Virtex-4-FF668 FPGA device families and achieved substantial improvements in throughput of 13.057% and 113%, respectively, as well as efficiency of 8.109% and 113.734% respectively. The proposed architecture is evaluated on a variety of grayscale images, and the security analysis is performed using MATLAB software. Aside from that, the proposed architecture uses the CBC-mode of operation. The security analysis and encryption outputs show that the proposed architecture is an effective choice for image encryption and provides sufficient security to the cipher images. • Propose a serial architecture which reduces the number of utilized resources that suggests reduction in area for resource constrained devices. • Propose an unrolled pipeline architecture which achieves high throughput, and low latency implementation. • Propose a round-based architecture and provides a comparison of all proposed designs with existing implementations. • All the implementations are analyzed by using different security analyses for image encryption applications that secure their immunity against various statistical and differential attacks. [ABSTRACT FROM AUTHOR]

The exponential function is one of the basic elementary functions, which plays an irreplaceable role in mathematics and is also widely used in practical activities such as life and production. In this paper, a new 5D memristive exponential hyperchaotic system (MEHS) is proposed, which includes an exponential term and a nonlinear flux-controlled memristive model. Fundamental dynamics characteristics of the system are analyzed using phase diagram, Lyapunov exponential spectrum and bifurcation diagram. When appropriate parameter sets are selected, the MEHS exhibits a rich set of dynamic behaviors, including the coexistence of periodic and periodic attractors, periodic and chaotic attractors, chaotic and hyperchaotic attractors. In addition, the Field Programmable Gate Array (FPGA) is used to realize the 5D MEHS, and the experimental results are consistent with the numerical simulation results on MATLAB. Finally, an image encryption application based on the 5D MEHS is presented. The security analysis shows the feasibility and effectiveness of the image encryption algorithm. • In this paper, a 5D memristive exponential hyperchaotic system (MEHS) is constructed. • The proposed 5D MEHS shows rich dynamic behaviors. • Besides, we design a digital circuit based on FPGA to realize the 5D MEHS. • Finally, an image encryption based on the 5D MEHS is proposed. [ABSTRACT FROM AUTHOR]

This paper proposes an improved equivalent source (ES) model based on particle swarm optimization (PSO) to predict the radiated emissions of a 2.4 GHz ISM band patch antenna. The proposed model uses near-field data to extract an equivalent set of infinitesimal electric dipoles representation. Characterized by their positions, orientations, and currents, these dipoles can reproduce the same field distribution as the target device under test (DUT). To build an accurate equivalent dipole model, a numerical experiment is performed and presented in this paper, where many variable selections of observation points and dipole numbers and locations of the dipole plane are examined, with the aspiration of determining a suitable conversion problem. Based on the proper combination of the two methods (ES-PSO), the complete modeling procedure consists of the application of the pseudo-inverse method to find the minimum norm solution to the least-square problem. Then, the obtained solution is provided to the PSO algorithm to initialize the search for the best-fit dipole parameters. The PSO method can further enhance the stability of the obtained dipole solution and improve the accuracy of the far field prediction. Promising and encouraging results in terms of field prediction at higher planes above the DUT are obtained. • Model the radiated emissions from a patch antenna using an equivalent source method. • Solving an inverse problem from field to source for near field-far field conversion. • Mitigating the effect of ill-conditioned system by preforming numerical experiment. • Improving the stability of the equivalent sources using particle swarm optimization. [ABSTRACT FROM AUTHOR]

Since static power gradually dominates on-chip network power, power gating has been widely studied as a way to mitigate this trend. Even though many power gating methods reduce static power, they introduce new problems such as higher latency and hardware overhead, network disconnections, and low scalability. A new power gating method is therefore needed that can effectively reduce static power without sacrificing the benefits of the on-chip network. In this paper, we propose an efficient power gating method for virtual channels. Firstly, neighboring routers no longer exchange and store each other's power states with handshake signals, and each router independently decides when to sleep or wake up based on traffic loads. Secondly, in order to eliminate flit stalls and reduce network latency, we propose a modified credit-based flow control and provide a detailed hardware implementation. Finally, bypasses allow packets to reach processing elements (PEs) or downstream routers without waking up sleeping virtual channels, which reduces breakeven time (BET) violations and cumulative wake-up latency while ensuring network connectivity. Based on the evaluation, under real applications, the proposed power gating method reduces static energy by an average of 82.5% compared to the baseline, while increasing latency overhead by 13.7% and area overhead by 6.48%. • This paper proposes a power gating method for virtual channels that saves as much energy as possible while reducing the overhead caused by power gating. • Routers' power states are transparent to each other, so they do not need to exchange or save power states via handshake signals. Routers decide when to sleep or wake up based on upcoming traffic loads. • We propose a modified credit-based flow control and provide a detailed hardware implementation. It reuses the conventional flow control logic and hardware to its maximum extent and eliminates flit stalls. • Packets can reach a processing element (PE) or downstream router via bypasses without waiting for virtual channels to wake up, reducing latency and ensuring network connectivity. [ABSTRACT FROM AUTHOR]

Due to the vigorous and ever-evolving demands of the IoT field, resource-constrained devices are being deployed in such areas and several new challenges like sequestration and surveillance, have come into the picture. Multiple lightweight designs have been recommended to overcome the security issues for resource-constrained devices. In applications requiring data to be transmitted fast between various devices, loop unrolling and subsequent pipelining architectures are extremely efficient. In this paper, several efficient hardware implementations of Simeck cipher such as loop unrolling architecture and outer round pipelining technique have been proposed in order to achieve high throughput. This paper has also proposed a bit serialized architecture of the Simeck cipher that reduces the area footprint and used in less resource applications. Our Simeck Serial architecture is 29.5 times more efficient than LiCi cipher and occupies only 7% of the area occupied by LiCi cipher. Similarly, our proposed serial architecture occupies only 13% and 25% of total slices occupied by X 192 and XTEA respectively while still performs 184% and 161% more efficiently. All three architectures are evaluated and compared on the basis of throughput, area utilization, and power consumption for their implementations in different FPGA platforms. • In unroll loop architecture of Simeck cipher, all rounds are unrolled which ultimately vastly reduces the latency while providing an optimum trade-off between area footprint and performance. This makes the design fit for applications demanding less latency. • The proposed outer round pipelining architecture is in turn derived from the full loop unrolling architecture where the loop unrolling greatly simplifies the key scheduling and the round function of the Simeck cipher. With the installation of registers in between each round, throughput is significantly improved and the area footprint is also reduced making design relevant for low resource and high-speed applications. • The proposed serial architecture for Simeck cipher utilizes only 17 slices making it extremely area efficient. [ABSTRACT FROM AUTHOR]

This paper proposed a dynamic current-enhancement technique based on AC coupling network and feedforward compensation capacitor for current-feedback low-dropout regulators (LDOs). Compared with traditional reported current-feedback LDOs, this design exhibits wider input voltage range, greater load capacity and fast transient response, yet no extra power consumption is introduced. Moreover, a complete stability analysis under full load range is given in this paper. The proposed LDO is fabricated in SMIC 0. 18 μ m CMOS process. The input voltage range is 0.8–2.2 V and the maximum load current is 50 mA. The experiment results indicate that the overshoot and undershoot are 76 mV and 141 mV respectively when the load current is varied from 0 to 50 mA within 300 ns under the load of 100 pF load capacitor. • This paper proposed a dynamic current-enhancement technique for current-feedback lowdropout regulators. It significantly reduces the overshoot and undershoot and improves large signal transient response. More importantly, it is not implemented at the expense of more quiescent current. [ABSTRACT FROM AUTHOR]

The paper presents an adaptive WTA circuit where the firing of a neuron depends on input stimuli and the circuit self-adapts which in turn allow the loosing neuron to win. The CMOS based design have been simulated at 45 nm CMOS process which occupies less chip area (of about 12 × 25 μm2) and consume low power (about 124 nW). The design is stable as temperature coefficient is about 11.5 μV/°C and noise figure is about 11.6 nV/Hz. The self-adaption feature depends on the value of capacitor ratio which is equal to 50 fF. A visual brain feature called Binocular Rivalry (BR) has been demonstrated and explained using simulated results of proposed circuit. Three features of visual brain; superimposition of images obtained from two eyes; binocular rivalry when different images are presented to eyes: suppression and dominance of images, and neural adaption, have been explained using circuit simulation. The real time images processed using image processing illustrating BR features has also been implemented to circuit for real time operations. The time taken for neural adaption which causes switching of images in human brain when distinguish images are provided to eyes is about 0.2s, as demonstrated in circuit simulations using BR images. The proposed design can be implanted in machines (humanly robots) with which it can see, learn and self-adapt like a human visual brain. The circuit and the concept can also be implemented in devices used in assistive technology for helping visually disabled or less able persons. The Papers proposes a novel idea of CMOS based hardware for implementing BR features in machines. • Binocular Rivalry and its functionality. • Visualization and its effect with the help of image processing. • Relationship between CMOS circuits and images to get better understanding. • Emulate features of suppression and dominance and also neural adaptation. • The neural adaption leads to the concept of perceptual awareness. [ABSTRACT FROM AUTHOR]

With growing interest in near-threshold voltage regime (NTV) to make energy-efficient circuits, their operation has become less reliable and prone to errors. A soft error is one of the significant reliability concerns in Static random access memories (SRAM) cells, and due to technology scaling, the sensitivity of these SRAM cells to soft errors has increased. The SRAM memories are more susceptible to the radiation effects, mainly Single Event Upsets (SEU). This paper presents a 10T SRAM cell, which gives an energy-efficient operation with high noise margins and is radiation hardened by design. We implement the novel memory cell in an industrial 65-nm CMOS technology and ASAP7 7-nm Fin-FET technology in the NTV regime. The proposed memory cell reduces the area overhead from the QUCCE10T and QUCCE12T cells by 12% and 25% in 65-nm technology. In 65- nm technology, the proposed SRAM cell significantly improves HSNM/RSNM by 24/14% over the recently reported RHPD12T cell with nearly equal WSNM. We also verify the radiation hardness of the proposed memory cell in 32- nm CMOS technology using TCAD simulations. In 32-nm technology, the proposed SRAM cell provides radiation hardness up to the value of LET = 35 MeV cm2/mg. • This paper presents a 10T SRAM cell, which gives an energy-efficient operation with high noise margins and is radiation hardened by design. • The proposed memory cell implement in an industrial 65-nm CMOS technology and ASAP7 7-nm Fin-FET technology in the NTV regime. • The proposed memory cell reduces the area overhead from the QUCCE10T and QUCCE12T cells by 12% and 25% in 65-nm technology. • In 65- nm technology, the proposed SRAM cell significantly improves HSNM/RSNM by 24/14% over the recently reported RHPD12T cell with nearly equal WSNM. • We also verify the radiation hardness of the proposed memory cell in 32- nm CMOS technology using TCAD simulations. In 32-nm technology, the proposed SRAM cell provides radiation hardness up to the value of LET = 35 MeV cm2/mg. [ABSTRACT FROM AUTHOR]

The specificity of the 3D integrated circuit and the changes in the design integration flow bring many new problems to the test process, such as reducing the controllability of the test and increasing the test cost. To address these problems, this paper proposes a low-power hybrid test scheme based on multiple reconfigurable linear feedback shift register(LFSRs) for 3D integrated circuit, which can reuse the test vector generator of the pre-binding test phase in the in-binding and post-binding test phase, reconfiguring a new test vector generator with lower test cost. Compared with the method of using the linear feedback shift register(LFSR) of each layer circuit independently as the test vector generator of the whole circuit in the in-binding test phase, the scheme in this paper can effectively utilize the original LFSR of each layer circuit and reduce the area overhead; the reconfigured 3D-LFSR can obtain better test data compression effect and lower test power consumption, improve test efficiency and reduce test time. Experiments have shown a 5% improvement in average test data compression, 53.1% and 9.6% reduction in average and peak power consumption respectively, 28% reduction in test area and 19.6% reduction in test time. • A reconfigurable structure test structure for LFSR is designed in 3D integrated circuits. • The proposed test structure achieves optimization of the in-binding and post-binding test. • The relationship between test power consumption and test time can be adjusted. [ABSTRACT FROM AUTHOR]

Testing of Integrated Circuits (ICs) is essential for weeding out defects before the products are shipped to customers. With the growing complexity of ICs, high-cost specification tests are becoming a bottleneck owing to their lengthy Test Time (TT). TT becomes particularly critical when the overall costs of ICs have to be taken into consideration. Considering the problem that TT takes too long in the traditional test, i. e. , a test with full Test Patterns (TPs), this paper proposes an improved K-Nearest Neighbor (KNN) algorithm to classify the defects, i. e. , this TP selection approach utilizes a classification model to select the valid patterns only, to shorten the TT. Experimental results demonstrate that compared with the traditional method, the proposed method successfully reduces the TT by 1.75 times. Furthermore, the experimental results represent the optimal compromise between TC and Test Quality (TQ). • This paper provides test cost reduction without increasing the defect level obviously. • We find the optimal solution between test cost and test quality. • KNN model was proposed to make it is possessed of stronger applicability and generality. • Test time and test quality have been greatly improved. [ABSTRACT FROM AUTHOR]

Routing is one of the most important and time-consuming stages of physical design. As the process node of semiconductors keeps scaling down, the routing process faces increasing challenges, and the traditional solutions are not sufficiently efficient. In recent years, machine learning has aroused much interest in this context, and an increasing number of algorithms have introduced advanced machine learning techniques to help solve the routing problem. In this paper, we survey the recent development of machine learning-based routing algorithms. • This paper provides an overview of recent published machine learning-based routing algorithms. • Some trends on the development of machine learning-based routing algorithms are revealed. • The possible advantages and disadvantages on machine learning-based routing methods are discussed. [ABSTRACT FROM AUTHOR]

A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs. • A multipath two-stage OTA with boosted slew rate and power efficiency is designed in this paper. • Using the multipath technique in the first stage of the proposed OTA leads to an increase in gain and a decrease in power consumption. • In addition, a high-speed current mirror is applied to increase the phase margin. • Moreover, the power efficiency of the proposed OTA has been boosted compared to the RDFC OTA. [ABSTRACT FROM AUTHOR]

It is intuitively clear that a circuit to be implemented by selectively utilizing standard cells of various non-integer multiple-heights (NIMH) (e.g., mixed use of 6-track, 7.5-track, and 9-track cells) is able to provide a better opportunity in optimizing power, performance, and area over that by using cells of single-height only or of integer multiple-heights only. However, from the cell placement legalization point of view, the issues to be addressed for placement legalization on NIMH designs are very complex. And this paper primarily focuses on introducing novel ideas for row placement when utilizing NIMH cells, which involves determining the row pattern. The most inter-dependent and critical tasks, which are rather unique to the NIMH cell placement legalization problem, are (task 1) for the cells of the same height, distributing and assigning them to a set of distinct rows on a die and (task 2) determining the location of the rows containing cells of the same height. We solve the legalization problem by, starting from an initial row placement, iteratively solving the two tasks by formulating task 1 into an instance of row-capacity constrained network flow problem, followed by solving task 2 which leads to an optimal vertical displacement of the cells in the rows. Meanwhile, through experiments, it is shown that our network flow driven global cell assignment to rows for NIMH cell placement problem tightly linking the optimal determination of row location is able to reduce the total amount of cell displacements from the global (initial) placement by 9.5% and 51.2% in comparison with that produced by a greedy approach and the conventional state-of-the-art NIMH cell placement legalization method, respectively. • This paper primarily focuses on introducing novel ideas for row placement when utilizing NIMH (non-integer multiple-height) cells. • The most inter-dependent and critical tasks are (task 1) for the cells of the same height, distributing and assigning them to a set of distinct rows on a die and (task 2) determining the location of the rows containing cells of the same height. • We solve the legalization problem by iteratively solving the two tasks by formulating task 1 into an instance of row-capacity constrained network flow problem, followed by solving task 2 which leads to an optimal vertical displacement of the cells in the rows. • Our network flow driven global cell assignment to rows is able to reduce the total amount of cell displacements from the global (initial) placement by 29.0% and 62.0% in comparison with that produced by a greedy approach and the conventional state-of-the-art NIMH cell placement legalization method, respectively. [ABSTRACT FROM AUTHOR]

The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common-mode range. Instead of a conventional single dummy switch compensation [1] , the multi-dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed-form equations are derived mathematically to substantiate the proposed technique. For the proof-of-concept, a track-and-hold (T/H) stage has been simulated in 0. 18 μ m CMOS technology with the proposed technique for a 10-bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input-referred third-order intercept point (IIP3) of 13.02 dBm and an input-referred 1 dB compression point (P 1dB) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9 × improvement in mean percentage error (MPE) when simulated across the various process corners and rail-to-rail input common-mode voltage. • The paper presents a multi-dummy switch technique to minimize the charge injection error in a MOS switch. • Mathematical analysis has been carried out to validate the concept. • A design methodology is proposed to limit the charge injection error within ±0.5 LSB for 10-bit track-and-hold circuit. • The presented method is compared with existing single dummy switch compensation technique and the results depict 272% improvement in dynamic linearity. • The proposed method provides 9X improvement in the mean percentage error over the existing method. • The design is simulated in CMOS 180 nm technology and the post-layout simulation results are reported in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a method to decompose an op-amp into its functional blocks. The method is able to recognize functional blocks on a high level of abstraction, such as loads or amplification stages, which have a large set of possible structural implementations. The paper presents a hierarchical library of functional blocks. With increasing hierarchy levels, the structural representation of the functional blocks becomes more variable while its function emerges. We use the hierarchical order to automatically compute the functional decomposition of an op-amp given as a flat netlist. Experimental results illustrate the method. The functional block decomposition enables a comprehensive formalization of design knowledge for computer-aided design of op-amps. An overview is given how the method is applicable to circuit sizing and structural synthesis of op-amps. • New structural analysis method for analog circuits able to decompose whole op-amp topologies into their functional blocks. • A computer-oriented description for each functional block in an op-amp is presented. • Algorithms use the computer-oriented descriptions for automatic recognition. • Two applications for the structural analysis method are presented: circuit sizing and structural synthesis. [ABSTRACT FROM AUTHOR]

In this paper, a novel four-dimensional autonomous chaotic system based on memristive diode bridge is presented, and it consists of a simple linear oscillation and a memristor. According to the mathematical model of the system, the equilibrium point is analyzed, and the phase portraits, time-domain sequences, bifurcation diagrams and Lyapunov exponent spectrums are numerically simulated. The rich dynamical behavior of proposed system is investigated. It includes multistability, offset boosting and chaotic bursting. In addition, the circuit simulation and Field-Programmable Gate Array (FPGA) hardware experiment are carried out to verify the feasibility of the system. Then the application of proposed system in chaotic image encryption is presented. By carrying out some security performance analyses, we show that the proposed system has good security performance. • A memristor chaotic system with simple circuit structure is proposed. • The memristive chaotic system presented in this paper has rich dynamical behaviors. • The dynamical behavior of offset boosting and multi-stable is proposed. [ABSTRACT FROM AUTHOR]

To improve the performance of systolic array processors, this paper designs and implements a novel architecture which supports dynamic dataflows. First, we design three typical systolic array processors, including the output stationary, weight stationary, and input stationary systolic array. Second, we detailedly evaluate the performance of these processors, and find that none of them always perform best in all environments. Finally, based on the characteristics of three different dataflows, this paper designs a novel systolic array processor with dynamic dataflows. The experimental results show that the proposed systolic array processor achieves the best performance for a variety of computing environments. • This paper designs and implements a novel architecture which supports dynamic dataflows. • We Designed the output stationary, weight stationary, and input stationary systolic array. • We detailedly evaluate the performance of these processors. • We can find a systolic array processor always has the best performance in each circumstance. [ABSTRACT FROM AUTHOR]

The investigation of memristive chaotic systems (MCS) with complex dynamics has been an interesting and important research topic. This paper is devoted to constructing a simple and meaningful MCS that has one-equilibrium but has multi-parameter amplitude modulation and large-scale offset boosting. Based on the bifurcation diagrams and Lyapunov exponents, the evolution process of system dynamicsunder the influence of parameters are shown. Consistent results with numerical simulations are observed in circuit experiments, which shows the existence and practicability of the MCS. • A simple one-equiibrium memristive chaotic system is constructed. • Multi-parameter amplitude modulation and large-scale offset boosting are found. • Circuit implementation of the proposed system is given for verifying existence. [ABSTRACT FROM AUTHOR]

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF. • SCA-PUF utilizes the non-linear sunthreshold current of transistors. • SCA-PUF is quite vulnerable to advanced modeling attacks such as LMAs. • RNN-embedded SCA PUF resists LMAs by masking power side-channel information. [ABSTRACT FROM AUTHOR]

The primary requirement for multimedia applications is energy efficient design along with computational efficiency of portable devices. This work proposes an energy efficient MAC with error compensating novel approximate adder and approximate multiplier. The proposed approximate hierarchical adder (AXHA – N) has the advantage of zero carry propagation and consists of only two gate levels which deliver very high speed and very low energy consumption along with the near to zero mean error distances. The proposed approximate 4 - bit multiplier also has no carry propagation from Least Significant Bit (LSB) to Most Significant Bit (MSB), which leads to high speed with very low energy consumption and acceptable error profiles. Higher bit size multipliers can be built using the proposed modified recursive multiplication scheme. This work proposes three variants A X M A C 1 , A X M A C 2 , A X M A C 3 basing on one or both of adder and multiplier being approximate. The proposed A X M A C 3 with any k , has energy savings ranging from 40% to 60% for different A x L when compared to accurate with Mean Error Distance between − 358 and 4305. The MED for A X M A C 3 with k = 8 , A X L = 4 is only 0.7% of the maximum possible value with 60% energy savings. The MED for A X M A C 3 with k = 12 s , A X L = 4 is only 0.8% of the maximum possible value with 57% energy savings. Mean Relative Error Distance (MRED) and Normalised Mean Error Distance (NMED) are also evaluated and presented in the paper for wholesome evaluation of AXMAC. The (Energy savings, MRED, MED) tuple 8 − b i t MAC for design of Adams et al., (2019) with k = 8 is (26.9%, 0.1, − 15048), for proposed A X M A C 3 with similar configuration has (57%, 0.01, 3663). • This work proposes an energy-efficient unsigned MAC with self-error compensating novel approximate adder and approximate multiplier. • The proposed higher size multipliers (AXM - N) recursively using the proposed approximate 4 - bit multipliers by which a balance between error tuning and parallelism can be obtained. • The proposed approximate hierarchical adder has the advantage of zero carry propagation and consists of only two gate levels which deliver very high speed and very low energy consumption along with the near to zero mean error distances. • This work proposes three variants AXMAC1, AXMAC2, AXMAC3 basing on one or both of adder and multiplier being approximate. • The proposed AXM AC3 with any k, has energy savings ranging from 40% to 60% for different AxL when compared to accurate with MED between − 358 and 4305. The deviation i.e., MED for AXMAC3 with k = 8, AXL = 4 is only 0.7% of the maximum possible value for 60% energy savings. The deviation i.e., MED for AXMAC3 with k = 12, AXL = 4 is only 0.8% of the maximum possible value for 57% energy savings. [ABSTRACT FROM AUTHOR]

The aggressive scaling down of the feature size in modern ICs has introduced major bottlenecks in printing layouts using a conventional 193 nm immersion lithography system. As different mitigation techniques have reached their limitations, Next Generation Lithography (NGL) techniques have been gaining popularity. Extreme Ultra-violet Lithography (EUVL) system which uses light having 13. 5 nm wavelength is one of the popular NGL for printing features below 20 nm. However, EUVL faces the problem of flare caused by irregular reflection from clear-field mask surfaces used. It leads to distortion of critical dimension (CD) during layout printing which in turn degrades the performance of the circuit. In this paper, we have formulated a delay-aware global routing problem in order to minimize flare without sacrificing the delay. Two different solvers, namely ILP and SAT-SMT, are employed and the results are compared. Experimental results show a significant reduction in flare without much compromise on delay. • Flare is a phenomenon in Extreme Ultra-violet lithography, which causes layout distortions. • In order to reduce flare, it is required to distribute the layout features conforming to the global flare distribution which can be modelled as a 2D concave function. In addition to that, it is important to take care of the delay during redistribution of the layout features. • For global routing, a set of delay optimized Steiner trees are to be constructed for each of the nets. • The Steiner tree that might lead to the best possible wire distribution for minimizing flare has to be selected for each net. • We have proposed a method based on mathematical programming that can select concurrently a delay-aware Steiner tree for each net such that flare over the layout area can be minimized. We have validated our proposed approach on IBM benchmark circuits to show the effectiveness of delay-aware flare reduction at the global routing stage. [ABSTRACT FROM AUTHOR]