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Sub-threshold designs have become a popular option in many energy constrained applications. However, a major bottleneck for these designs is the challenge in attaining timing closure. Most of the paths in sub-threshold designs can become critical paths due to the purely random process variation on threshold voltage, which exponentially impacts the gate delay. In order to address timing violations caused by process variation, post-silicon tuning is widely used through body biasing technology, which incurs heavy power and area overhead. Therefore, it is imperative to select only a small group of the gates with body biasing for post-silicon-tuning. In this paper, we first formulate this problem as a linear semi-infinite programming (LSIP). Then an efficient algorithm based on the novel concept of Incremental Hypercubic Sampling (IHCS), specially tailored to the problem structure, is proposed along with the convergence analysis. Compared with the state-of-the-art approach based on adaptive filtering, experimental results on industrial designs using 65 nm sub-threshold library demonstrate that our proposed IHCS approach can improve the pass rate by up to 7.3× with a speed up to 4.1×, using the same number of body biasing gates with about the same power consumption. [ABSTRACT FROM AUTHOR]

Memristive device based passive crossbar arrays hold a great promise for high-density and non-volatile memories. A significant challenge of ultra-high density integration of these crossbars is unwanted sneak-path currents. The most common way of addressing this issue today is an integrated or external selecting device to block unwanted current paths. In this paper, we use a memristive device with intrinsic rectifying behavior to suppress sneak-path currents in the crossbar. We systematically evaluate the read operation performance of large-scale crossbar arrays with regard to read margin and power consumption for different crossbar sizes, nanowire interconnect resistances, ON and OFF resistances, rectification ratios under different read-schemes. Outcomes of this study allow improved understanding of the trade-off between read margin, power consumption and read-schemes. Most importantly, this study provides a guideline for circuit designers to improve the performance of oxide-based resistive memory (RRAM) based cross-point arrays. Overall, self-rectifying behavior of the memristive device efficiently improves the read operation performance of large-scale selectorless cross-point arrays. [ABSTRACT FROM AUTHOR]

This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a one׳s-complement scheme instead of a two׳s-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC decoders. [ABSTRACT FROM AUTHOR]

In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with continuous convex functions of the width (height). It is proved that the area of a compact slicing floorplan is a convex function of its width (height). The convexity is shown for the cases with and without dead (empty) space. This feature can be exploited to efficiently optimize the dimensions of layout components with multiple variants, without enumerating all possible combinations. Layout of a voltage-doubler circuit is used to quantitatively verify the proof. [ABSTRACT FROM AUTHOR]

Reliability is becoming one of increasingly critical issues for design of modern integrated circuits, due to the continuous scaling of CMOS technology and emerging nano-scale devices. This paper presents a novel method for reliability analysis in combinational circuits with unreliable devices. By using the concept of equivalent reliability, the proposed method promises improvements over the state-of-the-art methods in terms of efficiency, while keeping a high level of accuracy, in estimating the circuit reliability. This efficiency is achieved due to the fact that this work utilizes input probabilities and gate reliabilities directly for reliability evaluation, instead of taking (or sampling) a huge number of input vectors as with most existing approaches. Simulation results on benchmark circuits show that our approach obtains a significant speedup over other existing methods, especially when the reliability evaluation is repetitively needed for a same circuit in order to provide the reliability improvement for reliability-driven design applications. [ABSTRACT FROM AUTHOR]

Statistical analysis of SRAM has emerged as a challenging issue because the SRAM cell failure probability is extremely small. In this paper, we develop a novel efficient sampling, searching and estimating method to capture the probability of SRAM failure. Particularly, we propose an innovative Adaptive Multi-Level Sliding-Window (AMLSW) method to find the failure boundary in the parameter space with less computational cost. The proposed AMLSW method applies an integrated optimization engine to adaptively explore the failure boundary by sampling a sequence of parameter points and calculating the simulation result in sliding windows. Its key features include ellipsoid transformation, multi-level grid partition and sliding window algorithm to make our method efficient and accurate for finding the SRAM failure probability and failure boundary in parameter space. Furthermore, we provide theoretical analysis on our new AMLSW method. The experimental results of a commercial 65 nm SRAM cell demonstrate that the AMLSW method achieves 1.7–40× runtime speed-up over the existing methods without surrendering accuracy, and dramatically high speed-up over normal M-C sampling method. Moreover, this new method provides the failure boundary in the parameter space as shown in experiments. [ABSTRACT FROM AUTHOR]

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation. Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques. In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques. [ABSTRACT FROM AUTHOR]

Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance of the on-chip interconnection networks. This paper proposes TagNoC, as an on-chip network router architecture with novel hybrid routing approach which reduces latency and power consumption at a fixed cost based on information redundancy. TagNoC is a hybrid routing approach which combines the source and distributed routing methods together. While eliminating packet routing in each router, TagNoC determines the forwarding output port in parallel with input buffering. For a marginal cost increase in header size, as compared to distributed routing techniques, routing latency can be hidden while eliminating power consuming portion of the routing, increasing router throughput and decreasing latency. The proposed TagNoC router is compared to baseline router with distributed routing implementation on a 16-node CMP mesh. Physical implementation of all routers is modeled using synthesized RTL, detailed area analysis, and accurate channel models. Performance evaluation is also carried out utilizing RTL simulation and detailed power analysis on both synthetic and application traffic is performed using post-synthesis gate-level simulation. The simulation results illustrate that TagNoC outperforms as compared to baseline distributed architecture and other source routing methods in terms of power, latency, and throughput. [ABSTRACT FROM AUTHOR]

Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency. [ABSTRACT FROM AUTHOR]

Design of future many-core chips is experiencing a paradigm shift to the so-called power-budgeting design, due to the widening gap between instantaneous power consumption and the allowed maximum power, referred as the power budget. Critical to these many-core chips is the runtime power allocation mechanism which can help optimizing the overall system performance under a limited power budget constraint. In this paper, the power allocation problem ( i.e. , maximizing the system performance under a power budget) is modeled by a combinatorial auction. The problem can be transformed to a knapsack problem and the optimal solution reaches a Walrasian equilibrium. To solve the problem efficiently in a decentralized way, a Hierarchal MultiAgent based Power allocation (HiMAP) method is proposed with an optimal bound. In HiMAP, tiles bid for the opportunity to become active based on the chip׳s total power budget. Upon finishing an auction process, certain tiles will be power gated and/or frequency scaled according to the power allocation decision. Experimental results have confirmed that HiMAP can reduce the execution time by as much as 45% compared to four competing methods. The runtime overhead and cost of HiMAP are also small, which makes it scale well with many-core systems. [ABSTRACT FROM AUTHOR]

In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on / I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal high write and read margins, the highest I on / I off ratio, a fast write, and ultra-low leakage power in the hold “0” state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from −40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400 mV and 500 mV. The study shows that the proposed cell meets the required cell sigma value (6 σ ) under all conditions. [ABSTRACT FROM AUTHOR]

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting scheme from both sides of the SRAM cell. This technique is applied to a 10T-SRAM cell with transmission-gate access devices. The proposed design gives 2.7×, 2.1× faster write time, 82% and 18% improvement in write margin compared with the standard 8T-SRAM cell with and without write assist, respectively. All simulations have been done in TSMC 65 nm CMOS technology. The proposed write assist technique enables 10T-SRAM cell to operate with 24% lower supply voltage compared with standard 8T-SRAM cell with negative bitline write assist. Due to the improved supply voltage scalability a 33% leakage power reduction is achieved. [ABSTRACT FROM AUTHOR]

Three-dimensional integration technology is proposed to break down long wires and increase integration level of emerging complex designs. However, efficiency of this technology heavily depends on the usage of Through-Silicon Vias. TSVs are key solutions for cooling the 3D-chips but they occupy considerable silicon area. Therefore, reducing the number of required TSVs in routing step is very critical in 3D-chips. In this paper, a TSV multiplexing approach is proposed to reduce the number of required routing TSV. We proposed two multiplexed 3D-switchbox architectures. In the first architecture, the TSVs inside the switchboxes are multiplexed while in the second architecture, TSVs are multiplexed between the switchboxes. Moreover, a routing algorithm is suggested to route the FPGA using the multiplexed switchboxes to evaluate the proposed architectures. Experimental results show that the presented architectures and algorithms reduce the number of used TSVs by 64.58% and 71.27% on average for the first and second architectures respectively, in cost of a negligible overheads in total wire length and auxiliary switches. [ABSTRACT FROM AUTHOR]