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Correction of the digital designs have emerged as a major bottleneck at Register Transfer Level (RTL) due to the growing complexity of the digital systems and shortening time-to-market. Existing automated correction methods face problems like large number of error root causes, poor scalability, and multiple design errors. To address these problems, we propose an automatic correction methodology based on a lightweight partial high level synthesis (HLS) flow which takes as inputs a golden C specification and a buggy RTL design and outputs the corrected RTL model. Synthesizing the specification using a HLS tool without considering the buggy RTL to obtain the corrected RTL is not the case because manual RTL optimizations done by the designer should be preserved so that the architecture of the corrected RTL design should be as similar as possible to that of the buggy one. The results on industrial large designs show that the proposed methodology achieves 92.3% less new resources and 81.1% less connections compared to synthesizing the golden specification using a HLS tool without considering the architecture of the buggy RTL design. • A lightweight partial high level synthesis mechanism to correct RTL designs. • Preserving manual RTL optimizations done by the designer. • Addressing the large number of error root causes issue. [ABSTRACT FROM AUTHOR]

Engineering Change Order (ECO) at Register Transfer Level (RTL) has been widely investigated by researchers, but at a higher level of abstraction than RTL, it is not properly addressed. Applying ECO using conventional HLS tools may result in a heavily different RTL in comparison with the original one. In order to minimize this difference, we have proposed a new high-level synthesis methodology, which considers the resulting data-path and its difference from the original one during scheduling and binding of the operations. Experimental results show that our proposed methodology makes only 6.9% changes in the connections of the original data-path in contrast to existing HLS tools, which alter 25.16% of the connections on average. Our methodology exploits 66% less spare cells than the existing HLS tools and makes no change in functional units and registers. • Considering metal mask ECO, by restricting changes only to the connections between resources of the original data-path. • Using difference between the new data-path and original as an optimization target during integrated scheduling and binding. • Proposing a heuristic partitioning method to break up the large synthesis problem in order to tackle scalability issue. [ABSTRACT FROM AUTHOR]

This paper presents a formal technique to verify and debug division circuits on fixed point numbers. The proposed technique is based on a reverse-engineering mechanism of obtaining a high level model of the gate level implementation and also introducing an intermediate representation of the specification that makes equivalence checking between two models possible. The main advantage of this representation is the fact that the specification is dynamically updated according to the information obtained from the implementation. At the end, if two updated models are not equivalent, possible bugs can be localized and then corrected automatically by analyzing the difference, if possible. Experimental results show the robustness of the proposed technique in comparison with other contemporary methods in terms of the run time and also show that two orders of magnitude average speedup is obtained. [ABSTRACT FROM AUTHOR]