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This paper proposes a novel metal–oxide (MOx) thin-film transistors (TFT)-based scan driver circuit with a DC power-supplied buffer. This circuit has two parts: a ‘carry generation block (CGB)’ and an ‘output generation block (OGB).’ The CGB generates a carry pulse by the bootstrapping effect of pull-up TFT with the aid of clock signal; clock-supplied bootstrapping. Then the OGB is controlled by the carry pulse, and the output pulse is generated by the bootstrapping effect of pull-up buffer TFT with DC power supply; DC-supplied bootstrapping. In the proposed circuit, the pull-up TFT in CGB does not need to have wide dimensions because the carry signal is separated from the large capacitive load in the pixel area. Accordingly, the capacitive load of the clock signal is significantly reduced, and the dynamic power consumption associated with clock toggling decreases remarkably compared with the conventional scan driver circuit that uses the clock-supplied bootstrapping for the wide output buffer TFT. In addition, a bootstrapping inverter in OGB makes the output pulse width the same as the clock-high duration, preventing the output pulses from overlapping, which is required for most of the organic light-emitting diode (OLED) pixel circuits with in-pixel compensation.

The small subthreshold swing (SS) of metal–oxide (MOx) thin-film transistors (TFTs) reduces the data voltage (VDAT) range of the organic light-emitting diode (OLED) display pixel circuit. This leads to a large OLED current error when a small change occurs in the gate-to-source voltage (VGS) of the driving TFT in the pixel. Therefore, we propose a new pixel circuit adopting a double-gate TFT structure for the driving TFT, which is mainly driven by the bottom gate with a thicker gate insulator to provide a wide VDAT range. The proposed pixel circuit further expands the VDAT range by employing threshold voltage (VTH) modulation effect depending on the gray level. It also allows for flexible adjustment of the VTH extraction time to reduce OLED current error at low gray levels. SPICE simulation and measured results verify that the proposed pixel circuit reduces the OLED current error rate to less than 10% even with a VTH variation of ±0.5 V or SS variation of ±5% for the current level from 0.1 nA to 30 nA.

We report the effects of grain boundary (GB) protrusion on the off-state current (IOFF) of p-channel polycrystalline silicon thin-film transistors by using three-dimensional technology computer-aided design (TCAD) simulation. We found that the IOFF at a high drain bias, VDS = −10 V, varies more than 10 times as the position of the GB protrusion changes, whereas it varies less than two times if the GB has no protrusion, i.e. has a flat surface. The TCAD analysis showed that the IOFF was mainly caused by band-to-band tunneling and that it increased noticeably when the GB protrusion was located at a certain distance from the highly doped drain region because the GB protrusion intensified the electric field at the drain junction. We also found that the IOFF increases further when the GB line is not perpendicular to the channel direction but has some tilt angle because the GB protrusion necessarily encompassed a critical region that maximized the electric field when it was positioned within the GB protrusion.

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.