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In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200 degrees C, 250 degrees C, 350 degrees C and 450 degrees C) and annealing times. We found that optimal conditions were obtained at 350 degrees C, with transfer characteristics showing a subthreshold slope of 0.5 V/dec, field effect mobility > 100 cm(2)/Vs and threshold voltage around -3.5 V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350 degrees C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for V,(stress) - V-t = -4 V while bias-stress at V-g = V-t and vertical bar V-g(stress)vertical bar >> vertical bar V-ds(stress)vertical bar did not produce appreciable changes in both transfer and output characteristics.

Hydrogenated amorphous silicon thin-film transistors have been fabricated by using electron-beam lithography to define channel length down to 0.2 μm. In this way it has been possible to evidence, for the first time, short-channel effects on these devices. In this work two short-channel effects occurring in 0.2 μm devices are discussed: degradation of the off-current as the source-drain voltage is increased and avalanche increase of the drain current for high source-drain voltage.

Negative bias stress experiments on a-Si:H/a-SiO 2 Thin Film Transistors show that the instability is predominantly related to charge injection in the gate insulator. We propose that charge injection is occurring in a defected region of the gate insulator adjacent to a-Si:H, caused by the effect of activated hydrogen on a-SiO 2 surface during deposition. To investigate the hydrogen influence, we have studied low-energy (100 eV) hydrogen-ion and Ar-ion bombardment effects on a-SiO 2 using synchrotron radiation photoemission spectroscopies. Comparing the two kind of treatments, we show that hydrogen treatment produces predominantly Si-H defects, which are observed to induce gap states in a-SiO 2 .

In this work the application of a-Si:H thin film transistor (TFT) technology in the field of chemical sensors is presented. In particular, two different types of devices have been fabricated: a) Pd-gate hydrogen sensors; b) K+-ion sensitive FET (ISFET). The obtained results show that a-Si:H TFT can be successfully used as gassensitive and ion-sensitive sensors and can represent a promising technology in this area.

In the present paper are shown the characteristics of devices succesfully employing low temperature plasma deposited a-SiO2 as gate insulator with thickness of 40 and 18 nm. They show a very sharp field effect conductivity onset and an on/off current ratio of about 8 orders of magnitude. Due to the very low insulator thickness it is possible to operate these devices in the range between -2 and 5V with on current of the order of 10−5A.

The phenomenon of space-charge density variation induced by illumination in metal/insulator/amorphous semiconductors structures is experimentally and theoretically investigated.

Electronic quality a-SiO 2 have been deposited by PECVD showing high breakdown fields and low trapping probability down to thickness of 16 nm. The transport properties of this material have been analyzed. The Fowler-Nordheim mechanism has been ruled out due a marked temperature sensitivity of the current around room temperature. On the other hand thermally activated transport, such as Schottky or Frenkel-Poole mechanisms, fit reasonably well the experimental data. However a better fit of the overall data seems to support the Schottky as the main transport mechanism in our materials.

Field effect conductance and mobility have been calculated in superlattice thin film transistors by using a classical model. The results show that, for low interface state densities, both computed quantities increase as the number of period is increased, keeping constant the total semiconductor thickness. This model fits well the data already reported for such devices.