1. Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors
- Author
-
A. Bonfiglietti, Luca Maiolo, M. Cuscunà, Alessandro Pecora, A. di Gaspare, Luigi Mariucci, Guglielmo Fortunato, and G. Stracci
- Subjects
thermal annealing ,Materials science ,Annealing (metallurgy) ,Transconductance ,Analytical chemistry ,Field effect ,engineering.material ,Condensed Matter Physics ,Subthreshold slope ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Polycrystalline silicon ,thin film transistor ,Thin-film transistor ,polycrystalline silicon ,Thermal ,Materials Chemistry ,Ceramics and Composites ,engineering ,p-channel - Abstract
In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200 degrees C, 250 degrees C, 350 degrees C and 450 degrees C) and annealing times. We found that optimal conditions were obtained at 350 degrees C, with transfer characteristics showing a subthreshold slope of 0.5 V/dec, field effect mobility > 100 cm(2)/Vs and threshold voltage around -3.5 V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350 degrees C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for V,(stress) - V-t = -4 V while bias-stress at V-g = V-t and vertical bar V-g(stress)vertical bar >> vertical bar V-ds(stress)vertical bar did not produce appreciable changes in both transfer and output characteristics.
- Published
- 2006