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Nowadays, multiple-error occurrence because of multiple transient faults is highly probable in digital circuits especially used in outer space environments. Therefore, concerning such applications, the processing systems performing operations such as addition and multiplication are of great importance and should be redesigned, properly. In this paper, some multiple-error resilient carry look-ahead adders are proposed more efficient than the existing designs. In this manner, at first, two new customized fault-tolerant voters are proposed and analyzed to be used for multiple-error correction/detection in the carry look-ahead adders utilizing a distributed partial triple modular redundancy along with a parity prediction scheme. Then, the new voters are exploited and incorporated into two types of grouped carry look-ahead adder architectures to obtain different designs with a compromise between the area overhead and reliability. Simulation results show that, as well as a complete single error correction/detection, the proposed voters lead to 8–15% area overhead reduction in different carry look-ahead adders while increasing multiple-error correction probability up to 17% and 26% utilizing the first and second proposed voters, respectively, compared to the best existing design. Furthermore, the total multiple error correction/detection probability is improved in different adder architectures in many cases. • Two new customized fault-tolerant voters are proposed with different error correction/detection probabilities and overheads. • All single errors inside these voters will be either corrected or detected. • Compared to previous voters in CLAs, proposed voters have higher fault-tolerance quality while requiring lower overheads. • Two different CLAs, simple grouped and two-level grouped are proposed, evaluated, and compared to the best existing design. • Designed 64-bit CLAs can correct or detect multiple errors incurred by 10 concurrent faults with 90% probability. [ABSTRACT FROM AUTHOR]

Abstract Radiation is a cause of errors in electronics systems, especially on those deployed in space. Memories can suffer from different radiation effects including Single Event Upsets and Multiple Cell Upsets. These effects produce corruption of data and may cause a system malfunction. 3D die-stacked memories have been designed to increase bandwidth, reduce latency and limit power consumption. The shielding characteristic of the 3D structure causes a heterogeneous fault tolerance behaviour of the system where some of the inner dies are invulnerable while the outer dies require different protection levels. Orthogonal Latin Square codes are a class of error correcting codes that are modular and can provide different error correction degrees depending on the number of parity bits used. This paper proposed a solution based on current standards to provide dynamic and heterogeneous error correction capabilities to a 3D memory. To do so, Orthogonal Latin Square codes are used. [ABSTRACT FROM AUTHOR]

Soft errors that corrupt the value of bits stored in registers or memories are a major issue for modern electronic systems. To ensure that they do not cause failures, error detection and correction codes are commonly used to protect memories. When memories are used for a specific application, sometimes it is possible to optimize the protection based on the knowledge of the application. One example is the memories used in network devices for packet processing. In particular, the protection of approximate membership check structures such as Bloom filters has been recently studied showing that it is possible to optimize the protection. Cuckoo filters are an alternative to Bloom filters for approximate membership check that has been recently proposed. Cuckoo filters are interesting as they are competitive in terms of memory usage for low false positive rates and also support the removal of elements. In this paper, the protection of Cuckoo filters against soft errors is studied showing that it can be enhanced by exploiting its structure and using the knowledge of the effects on an error in a Cuckoo filter. [ABSTRACT FROM AUTHOR]

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs. [ABSTRACT FROM AUTHOR]

Aiming at precisely predicting the life of the high-power white light LED (HPWLED), a three-parameter Weibull function and the right approximation method were employed to establish the luminance degradation model. The lumen maintenance data collected according to the IES LM-80-08 lumen maintenance test standard were fitted with and without error corrections, and the pseudo failure time of each HPWLED sample was extrapolated. The statistical analysis on the failure time was achieved by using Weibull distribution, normal distribution, lognormal distribution and Akaike Information Criterion (AIC). Then the life information was acquired. The results indicate that Weibull right approximation luminance degradation model (WRALDM) accurately reflects the variation of the lumen law with time. The failure time is accurately obtained. The best life distributions before and after the error correction to the lumen maintenance data are identified, based on AIC, as Weibull distribution and lognormal distribution, respectively. It is further confirmed by comparing the widths of life confidence interval and the life provided by the IES TM-21-11 method that the HPWLED life using WRALDM has a better accuracy. The optimized model provides researchers and manufacturers with significant guidelines for the further development of life prediction methodology. [ABSTRACT FROM AUTHOR]

Currently, the demand for reliable and high performance computing is increasing due to the enlarging susceptibility of computing circuits to different environmental effects, and the advent of diverse computation-based applications. Arithmetic operators, as the main building blocks of the processing units in computing systems, are exposed to different types of single or multiple errors incurred by different faults which can seriously damage the whole system. In this paper, a new approach is presented to achieve fault-tolerant carry look-ahead adder architectures, much more efficient than the conventional methods, with the characteristic of robustness against multiple simultaneous errors. The proposed method is based on revising the carry generation block to achieve multiple error correction capability, and utilizing a modified parity prediction-based method that in combination with the proposed error correction scheme leads to multiple error detection capability. Verified by simulations, analytical assessments show that, as well as correcting or detecting all single permanent or transient errors, multiple simultaneous errors in the new carry look-ahead adders are corrected or at least detected with a high probability independent of the number of errors. Apart from having more reliability against multiple errors, these adders require lower area overheads compared to the state of the art designs as well as conventional fault-tolerant methods. [ABSTRACT FROM AUTHOR]

Radiation-induced multiple bit upsets (MBUs) degrade the reliability of scaled static random access memory (SRAM)-based field programmable gate arrays (FPGAs). Reducing the correction time for MBU and preventing the error accumulation are the challenges faced by error correction code (ECC) integrated FPGAs. In this paper, a novel built-in ECC using encode-and-compare of the data and parity bits is proposed to reduce the correction time and improve the reliability of FPGA. Implementation has been carried out in FPGA to confirm its effectiveness. The proposed method is 5 times faster than existing CRC based inbuilt error mitigation solution. This work opens a door for 2-D ECC to be universally used in FPGAs for safety-critical applications. [ABSTRACT FROM AUTHOR]

This work presents a new decoding algorithm that extends the error-correction capacity of group testing based (GTB) non-binary error correction codes without modifying the number of parity symbols of the codeword. A list decoding algorithm based on the pattern of the syndromes takes advantage of the parity matrix equation exploiting its structure. The decoding algorithm can be reformulated by detecting superimposed errors (errors that affect to the same parity check equation). The list of superimposed patterns applies the extrinsic information of the non-superimposed locations to correct the errors. The list of non-superimposed locations simply apply a majority-logic pattern. The complexity of the proposed solution is lower, as it does not require complex operations such as multiplications or inversions in the Galois Field and shares the magnitude equations for both cases, keeping the rest of the equations with the same number of comparisons as the original single-symbol error correction algorithm. • New error-correction GTB algorithm with larger correction capacity without increasing parity symbols • Efficient algorithm to correct double-symbol errors • Increasing the coding gain with low complexity for decoding [ABSTRACT FROM AUTHOR]