Search

In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the ION current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. Additionally, the package out of plane deformation has been measured after flip chip to laminate and after molding. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress. It has also been shown that the out of plane deformation is independent of the Cu pillar design.

The influence of via density and passivation thickness on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and advanced copper/low-k processing. The reliability assessment is done using thermal cycling reliability tests, where two dedicated resistance based CPI test structures are analyzed. The data show a correlation between via density and reliability for both passivation modules, where a higher via density reduces the number of failures. In addition, the influence of passivation thickness was determined, where a thinner passivation results in a reduced number of failures. In order to visualize the failures, the interconnect stack was exposed after mechanical removal of the package overmold and Si etching. Cracks were present at the corner of the test chip.

Airgaps can undermine the mechanical properties of nano-interconnects and lead to reliability issues such as back end of line (BEOL) fractures. In this context, interconnect delamination under chip–package interaction (CPI) induced loads is a major failure mode which benefits from in-depth investigation. In this computational study, models of airgaps fabricated using the etch-back approach are developed for 90 nm pitch interconnects and potential mechanical failure modes including the fracture energy release rate (ERR) at various material interfaces are investigated. In addition, capacitance benefits of airgap implementation compared to the mainstream low-k technology are calculated using a capacitance simulator. Subsequently, mechanically conscious airgap design strategies are proposed which allow taking advantage of the maximal capacitive benefits of airgaps and limit the CPI related reliability concerns.

Utilizing Design Of Experiments (DOE) and a decision making procedure, the mechanical performance of different advanced node Back-End-Of-Line (BEOL) configurations is evaluated, where the average peel stress in metal vias is considered as the critical parameter, and is identified with mechanical performance. The goal is to guide the design of the BEOL in its conceptual phase, with respect to the via densities and low-k Young's modulus. The first section of the paper discusses an exploration of the design space X , using the orthogonal method as a selected DOE with which 16 different BEOL configurations are evaluated. The DOE is used to generate regression equations which allow to evaluate the influence of individual design parameters on mechanical performance. Low-k Young's modulus was proved to have dominant effect on reducing the stresses in the vias, and while the influence of the via density is lower, it is still possible to reduce the stresses by increasing the via density. In the second part, a decision making procedure is introduced, with the objective of choosing the optimal design out of a number of existing designs. Designs that are defined in the design space are mapped to the attribute space Y , and to the metric space M , which allows for comparison of individual designs in respect to the stress levels in different BEOL via layers. In this part, all designs are sorted in the metric space, and are ready to be evaluated. Finally, different distance norms (metrics) are introduced as value functions to evaluate individual designs. Based on these norms, an optimal design with high low-k Young's modulus and via 0 density has been identified, along with a number of other designs which show good mechanical performance.

Chip–package interaction (CPI) has become an increasingly important reliability issue in the microelectronics industry. In order to survive the thermally induced stresses during processing or working lifetime, the complex back-end-of-line (BEOL) layer stacks must have sufficient mechanical strength. The understanding of accelerated mechanical tests performed at wafer level, such as shear microprobing, is needed to early detect the risk of failure in the final IC device. In this study, the impact of the BEOL architecture in terms of via density and metal density on the failure location and the amount of observed BEOL failures is demonstrated by performing a large statistical amount of shear microprobing combined with post-mortem focused ion beam (FIB) cross sections. The experimental results are further supported by local bump pull tests, in-situ scanning electron microscopy (SEM) micro beam bending tests and finite element modeling (FEM). A clear correlation was found between the BEOL architecture and the amount of observed BEOL fractures. It was found that the cross sectional metal area in the topmost Z–group has a stronger impact on the amount of BEOL failures compared to the low or medium, X or Y–groups respectively. This trend was explained in terms of elastic shielding effect. Furthermore, both experimental results and FEM show that the via density may play a dominant role in both crack initiation and crack growth. These findings lead to a better understanding of the robustness of interconnect structures and the stresses they can tolerate and may serve as guidelines to develop a CPI-aware design of advanced nano-interconnects.

A computationally-efficient 3D phase-field model for simulating grain growth in through silicon vias (TSVs) is presented. The model is capable of simulating grain growth in the cylindrical shape of a TSV. The results generated from the phase-field simulations are used in a finite element model with anisotropic elastic and isotropic plastic effects to investigate the large statistical distribution of Cu pumping (i.e. the irreversible thermal expansion of TSV) experimentally seen. The model thus allows to correlate the macroscopic plastic deformation with the grain size and grain orientations.

The trend of microelectronic products in the textile or medical field is toward higher functionality, miniaturization, application of new materials and a necessity for deformable electronic circuits for improving the comfort control. In this work, the design of flexible and stretchable interconnections is presented. These interconnections are done by embedding sinuous electroplated metallic wires in a stretchable substrate material. A silicone material was chosen as substrate because of its low stiffness and high elongation before break. Common metal conductors used in the electronic industry have very limited elastic ranges; therefore a metallization design is crucial to allow stretchability of the conductors going up to 100%. Different configurations were simulated and compared among them and based on these results, a horseshoe like shape was suggested. This design allows a large deformation with the minimum stress concentration. Moreover, the damage in the metal is significantly reduced by applying narrow metallization schemes. In this way, each conductor track has been split in four parallel lines of 15 μm and 15 μm space in order to improve the mechanical performance without limiting the electrical characteristics.

This paper deals with a comparison study between SnPb and SnAgCu solder joint reliability. The comparison is based on non-linear finite element modelling. Three packages have been selected: silicon CSP, underfilled flip chip and QFN package. Also the effect of thermal cycling conditions has been investigated. Comparing the induced inelastic strains in the solder joint, the lead-free SnAgCu generally scores better thanks to the lower creep strain rate. On the other hand for the CSP and flip chip package, SnAgCu scores worse for the more extreme loading conditions when the inelastic dissipated energy density is selected as damage parameter. The main reason is that due to the lower creep strain rate, the stresses become higher for SnAgCu resulting in higher hysteresis loops with more dissipated energy per cycle. For the QFN package, SnAgCu scores much better.