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The shift of electronics industry towards the use of lead-free solders in components manufacturing brought also the challenge of addressing the problem of tin whiskers. Manufacturers of high reliability and safety critical equipment in sectors such as defence and aerospace rely increasingly on the use of commercial-of-the-shelf (COTS) electronic components for their products and systems. The use of COTS components with lead-free solder plated terminations comes with the risks for their long term reliability associated with tin whisker growth related failures. In the case of leaded type electronic components such as Quad Flat Package (QFP) and Small Outline Package (SOP), one of the promising solutions to this problem is to “re-finish” the package terminations by replacing the lead-free solder coatings on the leads with conventional tin–lead solder. This involves subjecting the electronic components to a post-manufacturing process known as Hot Solder Dip (HSD). One of the main concerns for adopting HSD (refinishing) as a strategy to the tin whisker problem is the potential risk for thermally induced damage in the components when subjected to this process. This paper details a thermal modelling driven approach to the characterisation of the impact of hot solder dipping on electronic components. Main focus is on the evaluation of the re-finishing process effects on parts’ temperature gradients and heating/cooling rates, and on the advantages of applying an efficient model based process optimisation. Transient thermal finite element analysis is used to evaluate the temperature distribution in Quad Flat Package (QFP) variants during a double-dip hot solder dipping process developed by Micross Components Ltd. Full detailed three-dimensional (3D) models of the components are developed using comprehensive characterisation of the respective package structures and materials based on X-ray, SEM-EDX, cross-sectional metallurgy and 3D CT scan. The thermal modelling approach is validated using thermocouple measurement data for one of the studied parts and by comparing with model temperature predictions. Model results have informed the process optimisation strategy, and through experimentation key process parameters are alerted to provide optimal thermal characteristics. The optimised process settings result in temperature ramp rates at die level within recommended manufacture’s limit. A demonstration and discussion on the influence of the package internal structure and design on the thermal response to HSD is also provided.

This paper presents an integrative application of several numerical analytical techniques and associated analysis tools for design optimization and damage prediction in electronics packages and microsystems. This design-for-reliability approach is based on four different types of numerical techniques that allow (1) high-fidelity modelling, (2) reduced order modelling, (3) numerical optimization and (4) uncertainty analysis. The capabilities and the characteristics of the methods that underpin these four types of modelling and analysis tools are firstly investigated. The integration of the methods and tools is then examined and a methodology for coupling the tools in an optimization process is proposed. This numerical methodology involves the following steps: (1) Define sampling points for the design of interest by design of experiments (DOE) and calculate the design response at each DOE point using high-fidelity analysis; (2) construct reduced order models (ROM) for fast analysis using the obtained response values at the DOE points; (3) Undertake deterministic optimization in the defined design space by ROM; and (4) Probabilistic optimization by including variation and uncertainty of the design in the optimization task. This approach is suitable to address design-for-reliability requirements at early design stages in a wide range of application areas. The application of this approach is demonstrated in a case for minimizing the thermal fatigue damage of flip-chip solder interconnects. Design modifications show that this approach can provide improved reliability of the package and in the same time satisfy a number of design requirements.

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature ( T

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.